xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
User manual
UM10204

NXP Semiconductors
Table 10. Characteristics of the SDA and SCL bus lines for Standard, Fast, and Fast-mode Plus I2C-bus devices[1]
Symbol Parameter Conditions Standard-mode Fast-mode Fast-mode Plus Unit
Min Max Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 0 1000 kHz
tHD;STA hold time (repeated) START condition After this period, the first 4.0 - 0.6 - 0.26 - μs
clock pulse is generated.
tLOW LOW period of the SCL clock 4.7 - 1.3 - 0.5 - μs
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - 0.26 - μs
tSU;STA set-up time for a repeated START 4.7 - 0.6 - 0.26 - μs
condition
tHD;DAT data hold time[2] CBUS compatible masters 5.0 - - - - - μs
(see Remark in Section 4.1)
I2C-bus devices 0[3] -[4] 0[3] -[4] μs
All information provided in this document is subject to legal disclaimers.

0 -
tSU;DAT data set-up time 250 - 100[5] - 50 - ns
tr rise time of both SDA and SCL signals - 1000 20 300 - 120 ns
Rev. 6 — 4 April 2014

tf fall time of both SDA and SCL - 300 20 × 300 20 × 120[8] ns

signals[3][6][7][8] (VDD / 5.5 V) (VDD / 5.5 V)[9]
tSU;STO set-up time for STOP condition 4.0 - 0.6 - 0.26 - μs
tBUF bus free time between a STOP and 4.7 - 1.3 - 0.5 - μs
START condition
Cb capacitive load for each bus line[10] - 400 - 400 - 550 pF
tVD;DAT data valid time[11] - 3.45[4] - 0.9[4] - 0.45[4] μs
tVD;ACK data valid acknowledge time[12] - 3.45[4] - 0.9[4] - 0.45[4] μs

I2C-bus specification and user manual

VnL noise margin at the LOW level for each connected device 0.1VDD - 0.1VDD - 0.1VDD - V
(including hysteresis)
VnH noise margin at the HIGH level for each connected device 0.2VDD - 0.2VDD - 0.2VDD - V
(including hysteresis)
© NXP Semiconductors N.V. 2014. All rights reserved.

[1] All values referred to VIH(min) (0.3VDD) and VIL(max) (0.7VDD) levels (see Table 9).
[2] tHD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

UM10204
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of
SCL.
[4] The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This maximum
must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases
the clock.
48 of 64
 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
[5] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the
User manual
UM10204

NXP Semiconductors
device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this
set-up time.
[6] If mixed with Hs-mode devices, faster fall times according to Table 10 are allowed.
[7] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection
resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[8] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing.
[9] Necessary to be backwards compatible to Fast-mode.
[10] The maximum bus capacitance allowable may vary from this value depending on the actual operating voltage and frequency of the application. Section 7.2 discusses techniques
for coping with higher bus capacitances.
[11] tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
[12] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 4 April 2014

I2C-bus specification and user manual

© NXP Semiconductors N.V. 2014. All rights reserved.

UM10204
49 of 64
NXP Semiconductors UM10204
I2C-bus specification and user manual

tf tr tSU;DAT

70 % 70 %
SDA
30 % 30 % cont.
tHD;DAT tVD;DAT
tf
tHIGH
tr
70 % 70 % 70 % 70 %
SCL 30 % 30 %
30 % 30 % cont.
tHD;STA tLOW
9th clock
S 1 / fSCL
1st clock cycle

tBUF

SDA

tVD;ACK
tSU;STA tHD;STA tSP tSU;STO

70 %
SCL 30 %
Sr P S
9th clock 002aac938

VIL = 0.3VDD
VIH = 0.7VDD
Fig 38. Definition of timing for F/S-mode devices on the I2C-bus

6.2 Hs-mode devices

The I/O levels, I/O current, spike suppression, output slope control and pin capacitance for
I2C-bus Hs-mode devices are given in Table 11. The noise margin for HIGH and LOW
levels on the bus lines are the same as specified for F/S-mode I2C-bus devices.

Figure 39 shows all timing parameters for the Hs-mode timing. The ‘normal’ START
condition S does not exist in Hs-mode. Timing parameters for Address bits, R/W bit,
Acknowledge bit and DATA bits are all the same. Only the rising edge of the first SCLH
clock signal after an acknowledge bit has a larger value because the external Rp has to
pull up SCLH without the help of the internal current-source.

The Hs-mode timing parameters for the bus lines are specified in Table 12. The minimum
HIGH and LOW periods and the maximum rise and fall times of the SCLH clock signal
determine the highest bit rate.

With an internally generated SCLH signal with LOW and HIGH level periods of 200 ns and
100 ns respectively, an Hs-mode master fulfills the timing requirements for the external
SCLH clock pulses (taking the rise and fall times into account) for the maximum bit rate of
3.4 Mbit/s. So a basic frequency of 10 MHz, or a multiple of 10 MHz, can be used by an
Hs-mode master to generate the SCLH signal. There are no limits for maximum HIGH and
LOW periods of the SCLH clock, and there is no limit for a lowest bit rate.

Timing parameters are independent for capacitive load up to 100 pF for each bus line
allowing the maximum possible bit rate of 3.4 Mbit/s. At a higher capacitive load on the
bus lines, the bit rate decreases gradually. The timing parameters for a capacitive bus
load of 400 pF are specified in Table 12, allowing a maximum bit rate of 1.7 Mbit/s. For
UM10204 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.

User manual Rev. 6 — 4 April 2014 50 of 64