Lab 1 Tutorial

CSE 140L, Fall 05

Instructor: C.K. Cheng
Computer Science and Engineering
University of California San Diego
October 1, 2005

Ver Date By Description

1 Oct. 1, 2005 Haikun Zhu Initial release. Email [email protected] for questions.
Rui Shi

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CSE 140L FA05 - Lab 1 Tutorial

1.0 Introduction
This is a step-by-step tutorial for building a full adder in Xilinx ISE 7.1.04i. By the end of this tutorial, you should be
able to
• Create a new design by schematic entry.
• Verify the function of a design by behavioral simulation.
• Map a design to a FPGA device through placement and routing procedures.
• Estimate the performance of the design by timing analysis.

2.0 Create a new design

1. Launch the Xilinx ISE design environment. Under MS Windows, go Start -> Programs -> Xilinx ISE 7.1i -
> Project Navigator. The following window will appear.

FIGURE 1. The main window of Xilinx ISE 7.1.04 design environment.

2. Click on File->New Project. In the pop-up New Project window, type in the project name, which is
FullAdder in this case. Select the location you wish to store your project in. Maker sure you select
schematic in the Top Level Module Type drop-down list. Click Next to continue.

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FIGURE 2. New project pop-up window.

3. Select Spartan2, xc2s30, tq144 and -5 for Device Family, Device, Package and Speed Grade respectively.
Make sure Modelsim is selected as the simulator. Click Next to continue.

FIGURE 3. Choose device for the new project.

4. In the next two dialog windows, you can create new source files or add existing source files, but we will do
this later. Just click Next to finish the wizard.

3.0 Understanding the full adder

Now we are going to build our full adder by laying out its schematic in Xilinx. A 1-bit binary full adder has three
inputs: two addends A and B, a carry-in Ci. The adder adds up the three inputs, which are seen as three binary digits,

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and generates a sum bit S and a carry-out Co. The truth table of the full adder is as follows. Note that the carry out Co
is of weight 2.
Table 1. Truth table of the full adder.
A B Ci S Co
0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 1 1 1

We can deduce the logic expressions of the sum bit S and the carry-out Co (take it as an exercise):

Co = A ⋅ B + A ⋅ Ci + B ⋅ Ci (1)

S = A ⊕ B ⊕ Ci (2)
In some literatures, the carry-out Co is referred to as the majority function, because Co is 1 if and only if at least two
of the three inputs are 1. The sum S is referred to as the parity function, because S is 1 if and only if the number of 1’s
in the three inputs is odd.

If we directly translate Eq. 1 and Eq. 2 into schematic, we will need two 2-input XOR gates, three 2-input AND gates
and two 2-input OR gates. We will show that, however, this is not optimal in terms of number of gates. Rather, we
will build the full adder hierarchically from two half adders.

A half adder has only two inputs: addends A and B, and also produces two outputs: sum S and carry-out Co. It does
not take into account the carry-in, in which sense it is only “half”.
Table 2. Truth table of the half adder.
A B S Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

The logic expressions of S and Co for the half adder are as follows:

Co = A ⋅ B (3)

S = A⊕B (4)
To understand how we can build the full adder from half adders, one remembers that the two addends A, B, carry-in
Ci as well as the sum S are of weight 1, while the carry-out Co is of weight 2. We first use a half adder to add up A and
B, generating an intermediate sum S_int and an intermediate carry-out Co_int1. We then use another half adder to add
up the intermediate sum S_int and the carry-in Ci, producing the final sum S and another intermediate carry-out
Co_int2. Co_int1 and Co_int2 can never be both 1 (could you answer why?), hence are ORed together to generate the
final carry-out Co. Such a design is pictured in Fig. 4. Since a half adder consists of a XOR gate and a AND gate, the
new full adder design needs two 2-input XOR gates, two 2-input AND gate and one 2-input OR gate.

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FIGURE 4. Building a full adder from two half adders.

A B Ci

Half
Adder
Co_int1 S_int
Full Adder
Half
Adder
Co_int2

Co S

From Eq. 3, Eq. 4 and the above figure we can write that

Co = A ⋅ B + Ci ⋅ ( A ⊕ B ) (5)
As an exercise, prove that Eq. 1 and Eq. 5 are equivalent.

4.0 Create the schematic of the full adder

We will first create the schematic of the half adder, then the full adder.

4.1 Create the half adder

1. In the Sources in Project window, right click on FullAdder.ise, select New Source. In the pop-up New
Source window, select Schematic, type in the file name, e.g., HalfAdder. Alternatively, you can do this
through the menu Project->New Source. Click next to finish.

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2. In the ensuing Schematic Editor window, click the Add Symbol icon and the symbol side window
should appear. Find the xor2 gate by selecting Category “Logic”, Symbol “xor2”. Move your mouse to
place it on the canvas at the right-hand side. Add the and2 gate too.

3. Use the wiring tool to make connections. Draw the appropriate wire connections between the gates and
leave excess wires for input and output connections. After it’s done, your schematic should look like this:

FIGURE 5. Schematic of the half adder.

4. Now select the Add I/O Marker tool . In the appearing Add I/O marker Options side window, select the
option that says "Input" and click near the two wires on the left-hand side of the drawing, then select the
option that says "Output" and click near the two wires on the right-hand side of the schematic. After you
have drawn all the IO Connectors, double click on each of them to give them appropriate names (i.e. A, B, S,
Co) respectively.

FIGURE 6. Add I/Os for the half adder.

5. Now we have finished the schematic of a half adder. We need to abstract it as a symbol so that we can re-use
it in the full adder. To do this, click on Tools->Symbol Wizard, use current schematic HalfAdder for Pin
Name Source.

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FIGURE 7. The symbol wizard.

6. Use the default values in the following windows and click Next to finish. However, make sure that the
names and directions of the I/O pins are correct. After it’s done, you’ll see your half adder symbol. Close it.

4.2 Create the full adder

1. Create a new schematic named FullAdder, as you did for the half adder.

2. When the new schematic editor opens, click on the Add Symbol icon , you should be able to see that
your FullAdder project appears in the Categories window. When selected, the HalfAdder appears in the
Symbol window. Click and drag two instances of the HalfAdder symbol on to the canvas.

FIGURE 8. Add the half adder symbol.

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3. Continue to finish the schematic of the full adder. Refer to Fig. 4 for the connections and I/Os.

FIGURE 9. The schematic of the full adder.

4. To print out your schematic, go to File->Print Setup, choose the appropriate paper size and then go to File-
>Print.

Remember to save constantly so that you don’t lose what you have done.

5.0 Behavior Simulation

In this section, we will introduce the concept of test bench and show how to verify the function of our full adder by
behavioral simulation.

5.1 What is a test bench?

A test bench is an entity (usually a VHDL/Verilog program) which is used to verify the correctness of a design. The
design to be verified is called Unit Under Test (UUT). The test bench supplies stimuli to the design, observes the out-
puts of the design, and compares the observed outputs with the expected values. If any mismatch happens, the test
bench issues certain messages signifying that there are errors in the design. Fig. 10 shows the concept of test bench.

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FIGURE 10. A conceptual diagram of the test bench.

Outputs
UUT

...

...
Stimuli

error?

Compare
Expected

..
Outputs
Test Bench

Advanced EDA tools such as Xilinx ISE usually have the capability to automatically generate the test bench. All the
users need to do is specifying the waveforms of the stimuli and the expected outputs; the software produces the test
bench program which can be tailored later on.

5.2 Build the test bench by specifying waveforms

1. Click Project->New Source; in the pop-up window, select Test Bench Waveform, type in the filename
FullAdder_tb. Click next to continue.

FIGURE 11. Adding Test Bench.

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2. Make sure the test bench is associated with the target design FullAdder.

3. Click Next to finish. A Initialize Timing window will show up. In the Clock Information group, select
Combinatorial (or internal clock). In the Combinatorial Timing Information group, specify Check
Outputs 25ns after inputs are assigned, and Assign Inputs 25ns after outputs are checked.

4. Click OK and you’ll see the waveform window of the test bench. The three input signals are marked cyan
while the two output signals are marked yellow. By directly clicking on the waveform you can change the
values of the signal. Just play around a little to get familiar with it. Now specify the waveforms of the three

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inputs as shown in Fig. 12. Notice that the waveforms of A, B and Ci cover all possible 8 combinations. For
each of the eight combinations, draw the expected outputs on the waveforms of Co and S. Recall that the
outputs are supposed to be 25ns later than the inputs as we specified in the previous window. Save the
waveforms after you’re done.

FIGURE 12. Test bench waveforms.

5. In the Process side window, double click on View Generated Test Bench, you’ll see the generated test bench
program. Close it.
6. Now back to the Project Navigator windows, and make sure that you have the test bench waveform you just
created selected in Sources in Project window. In the Process View window, double click Simulate
Behavioral Model. This will open up ModelSim simulation windows and run the test bench simulation. If
ModelSim fails to start, you need to go back to check the license.
7. Check the waveforms to see whether there are any errors. In particular, pay attention to signal tx_error in the
Objects window. tx_error counts how many errors are detected in the simulation. In this case, tx_error is 0
meaning everything looks fine.

FIGURE 13. Waveforms of the behavioral simulation.

6.0 Implementation and Timing Analysis

Next we’ll map the full adder design to the FPGA device that we selected in the beginning of this tutorial. Such a pro-
cess is called implementation.
1. Click on the FullAdder.sch in the Sources in Projects window, you should see Implement Design in the
underlying Processes window. Double click it to execute it. The process can take several minutes depending
on the powerfulness of your machine.
2. To see the timing report, go to Implement Design->Place&Route->Generate Post-Place&Route Static
Timing->Text-based Post-Place&Route Static Timing Report. The timing report will be shown in the right

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window. From the timing report, we see that the critical path (i.e. worst case delay) is from Ci to Co with a
delay of 9.620ns.

FIGURE 14. Timing report of the full adder.

7.0 Post-place & Route Simulation

Post-place & Route simulation is different from behavioral simulation in that we will see the real signal delay in the
waveforms.

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1. Before we run the post-place & route simulation, double click Generate Post-Place & Route Simulation
Model under Implement Design -> Place & Route in the Process View windows.

2. Create a new test bench FullAdder_post_tb.tbw. This time, set Check Outputs 10ns after inputs are
assigned, and Assign Inputs 40ns after outputs are checked. Specify the waveforms as you did for
FullAdder_tb.tbw. When done, double click Simulate Post-Place & Route VHDL Model in the Process
View window.

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3. Again, ModelSim will launch and simulate the test bench with post-place and route timing information. In
the waveforms of Fig. 15, a path delay of 7.906ns is explicitly shown. Compare Fig. 15 with Fig. 13 to see
how they are different.

FIGURE 15. Post-Place & Route Simulation.

Final Note: You may not be able to see the worst case delay in your post-place & route waveforms, because the worst
case delay is input pattern dependant. Put another way, the worst case delay happens only when certain transitions of
the inputs take place. As an exercise, think about what input transitions will exhibit the worst case delay Ci->Co
(9.620ns) of our full adder. Modify your test bench to have the worst case delay shown in the waveforms.

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