VLSI SYSTEMS FOR SIMULTANEOUS IN

LOGIC SIMULATION
Karthik. S Priyadarsini. k Jeanshilpa. V
AP, Department of ECE Research Scholar, Department of CSE AP, Department of ECE
SRMIST VISTAS B.S. Abdur Rahman Crescent IST
Chennai, India Chennai, India Chennai, India
[email protected] [email protected] [email protected]

Abstract— Logic simulation used in conjunction with redundancy. In Verification based on simulation technique, the
functional verification verifies the correctness of an integrated design or circuit is placed below a TB (test bench), then input
circuit. Verification methodologies can be formal or simulation vectors are passed through test bench, and finally the output
based. Formal based methodologies use exhaustive mathematical design is estimated with directed output. A TB contains a code
techniques to prove circuit responses to all possible inputs and all which supports the working of the circuit or design, and at
possible reachable states of the circuit conform to specification. times generates input vectors and also compares the output
These methods do not rely on the generation of input to verify the obtained with directed output. The input vectors can be
design. Simulation based methodologies aims at uncovering produced in advance to simulation and using a database it can
design errors by thoroughly exercising the current model of the
be read into the design at the time of simulation, or it is
circuit. The aim of this paper is to present a platform for efficient
produced during simulation run. Similarly, the directed output
parallel simulation of high level specification of the system
written using RTL/C/C++ language. For the experimental can also be produced. At the end, both the models are
purpose, the Zybo a heterogeneous platform board has been estimated. A simulator is moreover classified as event driven
considered in this work. Zybo board is a development kit which simulator, cycle-based simulator and hardware-emulator. An
provides the designer to develop or test designs. The board event simulator checks a module or logic gate or a group of
contains all the essential interfaces communications and associate code every time an input of the gate or the variable to which
functions to enable a wide range of applications. The most module is responsive. An event represents a shift in value. A
significant part on this board is Xilinx Zynq-7000 All CBS separates as per the clock domain and examines the sub
Programmable SoC (Zynq SoC) which consists of a dual ARM circuit at every triggering edge of the clk in clock domain.
Cortex-A9 CPU based PS (Processing System) as well as Xilinx Hence, event count creates impact in speed of simulator
hardware PL (Programmable Logic) on the same chip and working. A design with little activity or event possibly runs
supports hardware-software co-design. quicker on EDS, whereas a design with large event reckons
runs quicker on CBS. In routine, generally circuits have
Keywords—Zybo, Profiling, ZynQ, Verification enough functions that CBS exceed their EDS copies, although,
simulators based on cycle contain their own flaws. For a design
I. INTRODUCTION
to be counterfeit in a CBS, time domain in the design must be
It is a mandatory step in the development of today’s clearly distinguished. For instance, design with no clock does
multidimensional digital designs. The way the project team is not have clear time domain definition; example is an
put together, one can look at the worth of logic simulation. A asynchronous circuit since no clocks are involved. Hence, it
classic project team typically consists of same amount of cannot be simulated in a CBS.
design and verification engineers. From time to time the
number of verification engineers will be more than the design A hardware emulator or a hardware simulator forms a
engineers, since to validate a design, one must first understand design by means of hardware elements such as microprocessor
the specifications, knowledge of the design and more arrays and programmable ASICs like field programmable gate
important, develop a different design approach from the arrays (FPGAs). Initially, the elements like hardware simulator
specifications. It must be highlighted as the method adopted by are configured to pattern the design. In a processor array based
verification engineer will not be the same as that of the design hardware simulator, the design is converted into set of
engineer. Both would commit the same faults and nothing instructions which is self-same to simulating the design. In
much would be validated if the verification engineer shadows hardware emulator using an FPGA, the FPGAs are configured
the same design style as the design engineer. Hardware or programmed to represents the logic present in the design.
complication growth carries on following Moore’s law, but the Thereby, the outcome of functioning of the hardware is said to
verification difficulty is even more challenging. From be simulation outcome of the design. A hardware simulator
development cycle of a project, one can appreciate the efforts could be either cycle based or it can be like event driven as like
of DV (design verification). History shows that around 70% of a software simulator. So, each kind of simulator has its owned
time is spent on DV when entire project development cycle is programming style guidelines, and these are more rigid than
considered. Verification based on simulation is the most those of software simulators. A circuit could be run on a
frequently used verification method [1] .As, it is specified simulator if only if when it matches all coding needs of the
previously on books and articles, Verification based on software simulator. To support this descriptions containing
simulation is said to be a kind of verification technique by

978-1-5386-4310-5/18/$31.00 2018
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