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Input/Output
Organization

Bus Structure
Processor Memory

Bus

I/O device 1 I/O device n

• Multiple
I/O devices may be connected to the processor and the
memory via a bus.
• Busconsists of three sets of lines to carry address, data and control
signals.

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I/O interface for an input device.

•Each I/O device is
assigned a unique set of
addresses for the registers
in its interface.

•To access an I/O device,

the processor places its
address on the address
lines.
•The device that recognizes the address, responds to the command on
control lines. (Read or Write Operation)

Memory Mapped I/O

 I/O devices and the memory may share the same
address space:
 Any machine instruction that can access memory can
be used to transfer data to or from an I/O device.
 EG: To read the data from DATAIN register and store
it into processor register R2.
Load R2, DATAIN

• EG: To send the contents of register R2 to DATAOUT

register(data register of a display device interface)
Store R2, DATAOUT

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• The status and control registers contain

information relevant to the operation of the I/O
device.
• The address decoder, the data and status
registers, and the control circuitry required to
coordinate I/O transfers.

Address lines
The I/O interface circuit has: Bus Data lines
• Address decoder Control lines
• Control circuit
• Data and Status
registers. Address Control Data and I/O
decoder circuits status registers interface

Address decoder decodes

the address placed on the
address lines thus enabling Input device

the device to recognize its

address.
• Data register holds the data being transferred to or from the processor.
(DATAIN and DATAOUT)
• Status register holds information necessary for the operation of the I/O
device.
• Data and status registers are connected to the data lines, and have unique
addresses.

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 Processor, main memory, and I/O devices are

interconnected by means of a bus.
 Bus provides a communication path for the
transfer of data.
 Bus also includes lines to support interrupts
and arbitration.
 A bus protocol is the set of rules that govern
the behavior of various devices connected to
the bus, as to
 when to place information on the bus,
 when it may load the data on the bus into
one of its registers
 when to assert control signals, etc.

 Bus lines may be grouped into three types:

 Data
 Address
 Control
 Control signals specify:
 Whether it is a read or a write operation ( 𝑅⁄𝑊 )
 Required size of the data, when several operand sizes
(byte, word, half word) are possible.
 Timing information to indicate when the processor and
I/O devices may place data or receive data from the bus.
 Schemes for timing of data transfers over a bus can be
classified into:
 Synchronous,
 Asynchronous.

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Master/Slave

• In any data transfer operation, one device plays

the role of a master.
• This is the device that initiates data transfers by
issuing Read or Write commands on the bus.
• Normally, the processor acts as the master
• The device addressed by the master is referred
to as a slave.

Synchronous Bus
• On a synchronous bus, all devices derive timing
information from a control line called the bus
clock.
• The signal on this line has two phases:
•a high level followed by a low level.
• The two phases constitute a clock cycle.
• The first half of the cycle between the low-to-high
and high-to-low transitions is often referred to as
a clock pulse.

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Synchronous bus
 All devices derive timing information from a
common clock line.
 The clock line has equally spaced pulses which
define equal time intervals.
 In a simple synchronous bus, each of these
pulses constitutes a bus cycle.
 One data transfer can take place during one
bus cycle.

Bus clock

Bus cycle

Synchronous bus (contd..) T ime

Bus clock

Address and
command

Data

t0 t1 t2

Bus cycle
Master places the
device address and Addressed slave places
command on the bus, data on the data lines Master “strobes” the data
and indicates that on the data lines into its
it is a Read operation. input buffer, for a Read
operation.
•In case of a Write operation, the master places the data on the
bus along with the address and commands at time t0.
•The slave strobes the data into its input buffer at time t2.

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 Once the master places the device address and command

on the bus, it takes time for this information to propagate
to the devices:
 This time depends on the physical and electrical
characteristics of the bus.
 Also, all the devices have to be given enough time to
decode the address and control signals, so that the
addressed slave can place data on the bus.
 Width of the pulse t1 - t0 depends on:
 Maximum propagation delay between two devices
connected to the bus.
 Time taken by all the devices to decode the address and
control signals, so that the addressed slave can respond
at time t1.

 At the end of the clock cycle, at time t2, the

master strobes the data on the data lines into
its input buffer if it’s a Read operation.
 “Strobe” means to capture the values of the
data and store them into a buffer.
 When data are to be loaded into a storage
buffer register, the data should be available for
a period longer than the setup time of the
device.
 Width of the pulse t2 - t1 should be longer than:
 Maximum propagation time of the bus plus
 Set up time of the input buffer register of
the master.

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T ime

Address & Bus clock

Data reaches
command Seen by
the master.
appear on the master tAM

bus. Address and

command

Data
Address & tDM
command reach
Seen by slave
the slave. tAS
Address and Data appears
command on the bus.

Data
tDS

t0 t1 t
2

•Signals do not appear on the bus as soon as they are placed on

the bus, due to the propagation delay in the interface circuits.
•Signals reach the devices after a propagation delay which
depends on the characteristics of the bus.

• Att2 the master loads the data into its input

buffer.
• Theperiod t2 – tDM is the set up time for masters
input buffer.
• Datamust remain on the bus for some time after t2
equal to the hold time of the buffer.

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Multiple Cycle Transfers

 Data transfer has to be completed within one clock cycle.
 Clock period t2 – t0 must be such that the longest
propagation delay on the bus and the slowest device
interface must be accommodated.
 Forces all the devices to operate at the speed of the
slowest device.
 Processor just assumes that the data are available at t2 in
case of a Read operation, or are read by the device in case
of a Write operation.
 What if the device is actually failed, and never really
responded?

 Most buses have control signals to represent a response

from the slave.
 Control signals serve two purposes:
 Inform the master that the slave has recognized the
address, and is ready to participate in a data transfer
operation.
 Enable to adjust the duration of the data transfer
operation based on the speed of the participating
slaves.
 High-frequency bus clock is used:
 Data transfer spans several clock cycles instead of just
one clock cycle as in the earlier case.

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Input transfer using multiple clock cycles

Address & command Time
requesting a Read
operation appear on 1 2 3 4
the bus.
Clock

Address

Command
Master strobes data
into the input buffer.
Data

Slave-ready

Slave places the data on the bus, Clock changes are seen by all the devices
and asserts Slave-ready signal. at the same time.

Sequence of events
Clock cycle 1 – master sends address and command information
(Read) on the bus.
Slave receives information and decodes it.
Clock cycle 2 – Slave makes a decision to respond and begins to
access the requested data.
Clock cycle 3 – Data is ready and slave places the data on the bus.
Generates a control signal Slave Ready.
End of clock cycle 3 – on receiving Slave Ready the master strobes
the data into the input buffer.
Clock cycle 4 – bus transfer operation is complete. Master can send
a new address.
Slave Ready – used to synchronize slave and master. If the
addressed slave does not respond master waits for a predefined
amount of time and aborts the operation.

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Asynchronous bus
Data transfers on a bus is based on the use of a handshake protocol
between the master and the slave. A handshake is an exchange of
command and response signals between the master and the slave
 Data transfers on the bus is controlled by a handshake between the
master and the slave.
 Common clock in the synchronous bus case is replaced by two timing
control lines:
 Master-ready,
 Slave-ready.
 Master-ready signal is asserted by the master to indicate to the slave
that it is ready to participate in a data transfer.
 Slave-ready signal is asserted by the slave in response to the master-
ready from the master, and it indicates to the master that the slave is
ready to participate in a data transfer.

 Data transfer using the handshake protocol:

 Master places the address and command
information on the bus.
 Asserts the Master-ready signal to indicate to the
slaves that the address and command information
has been placed on the bus.
 All devices on the bus decode the address.
 Addressed slave performs the required operation,
and informs the processor it has done so by
asserting the Slave-ready signal.
 Master removes all the signals from the bus, once
Slave-ready is asserted.
 If the operation is a Read operation, Master also
strobes the data into its input buffer.

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T ime
Address
and command

Master-ready

Slave-ready

Data

t0 t1 t2 t3 t4 t5

Bus cycle

Handshake control of data transfer during an input operation

• t0
- Master places the address and command information on the
bus. All devices begin to decode this information.
• t1
- Master asserts the Master-ready signal to inform devices
that address and command information is ready. Master-ready
signal is asserted at t1 instead of t0
• t1-t0
– delay to care of skew (two signals transmitted from
one source simultaneously arrive at destination at
different times. Caused by propagation delays). This delay
should be larger than the maximum possible skew.
Decoding of address also takes place during this time.
• t2
- Addressed slave places the data on the bus and asserts the
Slave-ready signal.

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• t2
– t1 – this period depends on the distance between
master and slave and delays in the slave’s circuit.
• t3
- Slave-ready signal arrives at the master, indicating that
input data is available on the bus. After a delay equivalent to
the maximum bus skew and minimum set up time, the
master strobes the data into its input buffer. Now it drops
Master – ready signal to indicate it has received the data.
• t4
- Master removes the address and command information.
The delay between t3 and t4 allows bus skew.
• t5
- Slave receives the transition of the Master-ready signal
from 1 to 0. It removes the data and the Slave-ready signal
from the bus.
• This completes the input transfer.

• In case of an output operation the master places the data on the

data lines at the same time it transmits the address and
command information.
• The selected slave strobes the data into its input buffer when it
receives the Master-Ready signal and sets Slave Ready signal to 1

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• These handshake signals are said to be fully

interlocked, because a change in one signal is
always in response to a change in the other.
• This scheme is known as a full handshake.
• It
provides the highest degree of flexibility and
reliability.

 Advantages of asynchronous bus:

 Handshake protocol eliminates the need for
synchronization between the sender and the
receiver.
 Can accommodate varying delays automatically,
using the Slave-ready signal.
 Disadvantages of asynchronous bus:
 Data transfer rate with full handshake is
limited by two-round trip delays.
 Full Handshake: A change of state in one signal
is followed by a change of state in another
signal
 Data transfers using a synchronous bus
involves only one round trip delay, and hence a
synchronous bus can achieve faster rates.

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Electrical Considerations
• A bus is an interconnection medium to which several devices may be
connected.
• Only one device can place data on the bus at any given time.
• A logic gate that places data on the bus is called a bus driver.
• All devices connected to the bus, except the one that is currently
sending data, must have their bus drivers turned off.
• A tri-state gate, is used for this purpose.
 It has a control input that is used to turn the gate on or off.
 When turned on, or enabled, it drives the bus with 1 or 0,
corresponding to the value of its input signal.
 When turned off, or disabled, it is effectively disconnected from the
bus (its output goes into a high-impedance state that does not affect
the signal on the bus).

Arbitration

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Arbitration
• Twoor more entities may contend for the use of a single
resource.
• Forexample, two devices may need to access a given slave
at the same time. It is necessary to decide which device will
access the slave first.
• The decision is made in an arbitration process performed by
an arbiter circuit.
 The arbitration process starts by each device sending a
request to use the shared resource.
 The arbiter associates priorities with individual requests.
 If it receives two requests at the same time, it grants the
use of the slave to the device having the higher priority
first.

Arbitration
• Consider the case where a single bus is the shared resource.
• Thedevice that initiates data transfer requests for the bus
and becomes the bus master.
• Usually the processor is the bus master.
• Itis possible that several devices in a computer system need
to be bus masters to transfer data.
• Forexample, an I/O device needs to be a bus master to
transfer data directly to or from the computer’s memory.
• Sincethe bus is a single shared facility, it is essential to
provide orderly access to it by the bus masters.

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Arbitration
• A device that wishes to use the bus sends a request to the arbiter.
• When multiple requests arrive at the same time, the arbiter selects
one request and grants the bus to the corresponding device.
• For some devices, a delay in gaining access to the bus may lead to an
error. Such devices must be given high priority.
• If there is no particular urgency among requests, the arbiter may
grant the bus using a simple round-robin scheme.

Bus Arbitration involving two masters

• There are two Bus-request lines, BR1and BR2, and two Bus-grant lines,
BG1and BG2, connecting the arbiter to the masters.
• A master requests use of the bus by activating its Bus-request line.
• If a single Bus-request is activated, the arbiter activates the
corresponding Bus-grant.

This indicates to the selected

master that it may now use the
bus for transferring data.
When the transfer is completed,
that master deactivates its Bus-
request, and the arbiter
deactivates its Bus-grant.

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Granting use of the bus based on

priorities

• Assume that master 1 has the highest priority, followed by the others
in increasing numerical order.
• Master 2 sends a request to use the bus first. Since there are no other
requests, the arbiter grants the bus to this master by asserting BG2.
• When master 2 completes its data transfer operation, it releases the
bus by deactivating BR2.
• By that time, both masters 1 and 3 have activated their request lines.
• Since device 1 has a higher priority, the arbiter activates BG1 after it
deactivates BG2, thus granting the bus to master 1.
• Later, when master 1 releases the bus by deactivating BR1, the
arbiter deactivates BG1 and activates BG3 to grant the bus to master
3.
• Note that the bus is granted to master 1 before master 3 even though
master 3 activated its request line before master 1.

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Accessing I/O
Devices

• The components of a computer system communicate with each

other through an interconnection network.
• The interconnection network consists of circuits needed to transfer
information between the processor, the memory unit, and a number
of I/O devices.

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Memory Mapped I/O

 I/O devices and the memory may share the same address
space:
 Any machine instruction that can access memory can
be used to transfer data to or from an I/O device.
 To read data from the DATAIN register and load into
processor register R2
Load R2, DATAIN
 To send the contents of register R2 to location
DATAOUT, which is a register in an output device.
Store R2, DATAOUT

I/O Device Interface

• Device interface: A circuit that connects an I/O device to the
interconnection network.
• Provides the means for data transfer and for the exchange of status and
control information needed to facilitate the data transfers and govern
the operation of the device.
• The interface includes some registers that can be accessed by the
processor.
 buffer register for data transfers
 Status register to hold information about the current status of the
device
 Control register stores the information that controls the operational
behavior of the device.

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• These data, status, and control registers are accessed by program

instructions as if they were memory locations.
• Typical transfers of information are between I/O registers and the
registers in the processor

Program-Controlled I/O
• Eg: Human-computer interaction—keyboard and display
• The task is to read characters typed on a keyboard, stores these
data in the memory, and displays the same characters on a display
screen.
• A simple way of implementing this task is to write a program that
performs all these functions.
• This method is known as program-controlled I/O.
• It is necessary to ensure that these happen at the right time.
• An input character must be read in response to a key being pressed.
For output, a character must be sent to the display only when the
display device is able to accept it.

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Program-Controlled I/O
• The rate of data transfer from the keyboard to a computer is limited
by the typing speed of the user, which is unlikely to exceed a few
characters per second.
• The rate at which characters can be transmitted to and displayed on
the display device, typically several thousand characters per second.
• This is much slower than the speed of a processor that can execute
billions of instructions per second.
• The difference in speed between the processor and I/O devices creates
the need for mechanisms to synchronize the transfer of data between
them.

Signaling Protocol
Output
• Processor sends the first character
• Waits for a signal from the display that the next character can
be sent.
• It then sends the second character, and so on.
Input
• The processor waits for a signal indicating that a key has been
pressed and its corresponding that a binary code is available in
an I/O register associated with the keyboard.
• Then the processor proceeds to read that code.

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Eg: Keyboard Interface

– 8-bit register that holds the

generated character.
– 8-bit status register

– 8-bit Control Register

• The circuit responds to a key being pressed by producing the code

(Assume 8-bit ASCII) for the corresponding character.
• KIN, set to 1 to indicate that a key has been pressed
• Processor reads the status flag KIN to determine whether a character
code has been placed in KBD_DATA. This is called Polling.
• The processor polls the I/O device.

Display interface

• DISP_DATA : 8-bit register, used to receive characters from the

processor
• DOUT – Status flag to indicate that it is ready to receive
the next character
• The addresses are four bytes higher. This makes all
addresses word-aligned in a 32-bit word computer.

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Data Transfers - KBD Read

• To perform I/O transfers, the processor must execute machine
instructions that check the state of the status flags and transfer data
between the processor and the I/O devices.
• When a key is pressed, the keyboard circuit places the ASCII-encoded
character into the KBD_DATA register and sets the KIN flag to 1.
• Meanwhile, the processor is executing the I/O program which
continuously checks the state of the KIN flag.
• When it detects that KIN is set to 1, it transfers the contents of
KBD_DATA into a processor register.
• Once the contents of KBD_DATA are read, KIN is cleared to 0, by the
interface circuit.
• If a second character is entered at the keyboard, KIN is again set to 1
and the process repeats.

READWAIT Read the KIN flag

Branch to READWAIT if KIN = 0
Transfer data from KBD_DATA to R5

• The Read operation described above may be implemented by the

RISC-style instructions:

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READWAIT: LoadByte R4, KBD_STATUS

And R4, R4, #2
Branch_if_[R4]=0 READWAIT
LoadByte R5, KBD_DATA
The LoadByte and StoreByte operation codes signify that the operand size is a byte,
to distinguish them from the Load and Store operation codes that we have used for
word operands.

• The And instruction is used to test the KIN flag, which is bit b1 of
the status information in R4.
• As long as b1 = 0, the result of the AND operation leaves the value
in R4 equal to zero, and the READWAIT loop continues to be
executed.

Data Transfer – Display Write

• When DOUT is equal to 1, the display is ready to receive a character.
• Under program control, the processor monitors DOUT, and when
DOUT is equal to 1, the processor transfers an ASCII-encoded
character to DISP_DATA.
• The transfer of a character to DISP_DATA clears DOUT to 0.
• When the display device is ready to receive a second character, DOUT
is again set to 1.
WRITEWAIT Read the DOUT flag
Branch to WRITEWAIT if DOUT = 0
Transfer data from R5 to DISP_DATA
The wait loop is executed repeatedly until the status flag DOUT is set to 1 by the display when it is
free to receive a character.

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The Write operation may be implemented as:

WRITEWAIT: LoadByte R4, DISP_STATUS

And R4, R4, #4
Branch_if_[R4]=0 WRITEWAIT
StoreByte R5, DISP_DATA

• The And instruction in this case uses the immediate

value 4 to test the display’s status bit, b2.

Interrupts

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Interrupts
 In program-controlled I/O, when the processor
continuously monitors the status of the device, it does not
perform any useful tasks.
 An alternate approach would be for the I/O device to alert
the processor when it becomes ready.
 Do so by sending a hardware signal called an interrupt
to the processor.
 At least one of the bus control lines, called an interrupt-
request line is dedicated for this purpose.
 Processor can perform other useful tasks while it is
waiting for the device to be ready.

Example
• Consider a task that requires continuous extensive computations to
be performed and the results to be displayed on a display device.
• The displayed results must be updated every ten seconds.
• The ten-second intervals can be determined by a simple timer
circuit, which generates an appropriate signal.
• The processor treats the timer circuit as an input device that
produces a signal that can be interrogated.
• If this is done by means of polling, the processor will waste
considerable time checking the state of the signal.
• A better solution is to have the timer circuit raise an interrupt
request once every ten seconds.
• In response, the processor displays the latest results.

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• The task can be implemented with a program that consists of two

routines, COMPUTE and DISPLAY.
• The processor continuously executes the COMPUTE routine.
• When it receives an interrupt request from the timer, it suspends the
execution of the COMPUTE routine and executes the DISPLAY
routine which sends the latest results to the display device.
• Upon completion of the DISPLAY routine, the processor resumes the
execution of the COMPUTE routine.
• Since the time needed to send the results to the display device is very
small compared to the ten-second interval, the processor in effect
spends almost all of its time executing the COMPUTE routine.

Transfer of control using interrupts.

Program 1
Interrupt Service routine

Interrupt
occurs i
here
i + 1

The routine executed in response to an interrupt request is called the

interrupt-service routine. (DISPLAY routine in our example).

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Interrupt-Service Routine (ISR)

• Assume that an interrupt request arrives during execution of
instruction i. The processor first completes execution of instruction
i. Then, it loads the program counter with the address of the first
instruction of the interrupt-service routine.
• After execution of the interrupt-service routine, the processor
returns to instruction i + 1.
• Therefore, when an interrupt occurs, the current contents of the
PC, which point to instruction i + 1, must be put in temporary
storage in a known location.
• A Return-from-interrupt instruction at the end of the interrupt-
service routine reloads the PC from that temporary storage
location, causing execution to resume at instruction i + 1.
• The return address must be saved either in a designated general-
purpose register or on the processor stack.

• As part of handling interrupts, the processor must inform the device

that its request has been recognized so that it may remove its
interrupt-request signal.
• This can be accomplished by means of a special control signal, called
interrupt acknowledge, which is sent to the device through the
interconnection network.
• The execution of an instruction in the interrupt-service routine that
accesses the status or data register in the device interface implicitly
informs the device that its interrupt request has been recognized.

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 When a processor receives an interrupt-

request, it must branch to the interrupt service
routine.
 It must also inform the device that it has
recognized the interrupt request.
 This can be accomplished in two ways:
 Some processors have an explicit interrupt-
acknowledge control signal for this purpose.
 In other cases, the data transfer that takes
place between the device and the processor
can be used to inform the device.

 Treatment of an interrupt-service routine is very similar to that of

a subroutine.
 However there are significant differences:
 A subroutine performs a task that is required by the
calling program.
 Interrupt-service routine may not have anything in
common with the program it interrupts.
 Interrupt-service routine and the program that it
interrupts may belong to different users.
 As a result, before branching to the interrupt-service
routine, not only the PC, but other information such as
condition code flags and processor registers used by both
the interrupted program and the interrupt service routine
must be stored.
 This will enable the interrupted program to resume
execution upon return from interrupt service routine.

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 Saving and restoring information can be

done automatically by the processor or
explicitly by program instructions.
 Saving and restoring registers involves
memory transfers:
 Increases the total execution time.
 Increases the delay between the time an
interrupt request is received, and the
start of execution of the interrupt-service
routine.
 This delay is called interrupt latency.

• Inorder to reduce the interrupt latency, most

processors save only the minimal amount of
information:
This minimal amount of information includes
Program Counter and processor status
registers.
• Any additional information that must be saved,
must be saved explicitly by the program
instructions at the beginning of the interrupt
service routine and restored at the end of the
routine.

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Design Variations
• Some computers provide two types of interrupts.
• One saves all register contents, and the other does not.
• A particular I/O device may use either type, depending
upon its response time requirements.
• Another interesting approach is to provide duplicate sets
of processor registers.
• In this case, a different set of registers can be used by the
interrupt-service routine, thus eliminating the need to
save and restore registers.
• The duplicate registers are called the shadow registers.

• Interrupts enable transfer of control from one program to another to

be initiated by an event external to the computer.
• Execution of the interrupted program resumes after the execution of
the interrupt-service routine has been completed.
• The concept of interrupts is used in operating systems and in many
control applications where processing of certain routines must be
accurately timed relative to external events.
• The latter type of application is referred to as real-time processing

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Enabling and Disabling Interrupts

• Interrupt-requests interrupt the execution of a program,
and may alter the intended sequence of events:
 Sometimes such alterations may be undesirable, and
must not be allowed.
 For example, an interrupt request from printer should
be accepted only if there are more line to print. Therefore
after printing the last n lines this interrupt should be
disabled.
 Or it may be necessary to guarantee that a particular
sequence of instructions is executed to the end without
interruption
• Processorsgenerally provide the ability to enable and
disable such interruptions as desired.

Enabling and Disabling Interrupts

• Interrupts can be enabled and disabled at both the

processor and I/O device ends.
 The processor can either accept or ignore interrupt
requests.
 An I/O device can either be allowed to raise interrupt
requests or prevented from doing so.
• Thisis achieved by using use some control bits in registers,
that can be accessed by program instructions.

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Enabling and Disabling

Interrupts – Processor end

• The processor has a status register (PS), which contains information

about its current state of operation.
• One bit, IE, of this register is assigned for enabling/disabling
interrupts.
• The programmer can set or clear IE.
• When IE = 1, interrupt requests from I/O devices are accepted and
serviced by the processor.
• When IE = 0, the processor simply ignores all interrupt requests from
I/O devices.

Enabling and Disabling

Interrupts – Device end
• The interface of an I/O device includes a control register that contains
the information that governs the mode of operation of the device.
• One bit in this register is dedicated to interrupt control.
• The I/O device is allowed to raise interrupt requests only when this bit
is set to 1.

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Single Interrupt Request from one Device

• When a device activates the interrupt-request signal, it keeps this
signal activated until it is intimated that the processor has accepted
its request.
• The interrupt-request signal will be active during execution of the
interrupt-service routine, until an instruction that accesses the device
is reached.
• This active request signal will not lead to successive interruptions,
causing the system to enter an infinite loop from which it cannot
recover.
 To avoid interruption by the same device during the execution of
an interrupt service routine:
 First instruction of an interrupt service routine can be Interrupt-
disable.
 Last instruction of an interrupt service routine can be Interrupt-
enable.

Disabling Interrupts at
Processor End
• Processor automatically disable interrupts before starting the
execution of the interrupt-service routine.
• The processor saves the contents of the program counter and the
processor status register.
• After saving the contents of the PS register, with the IE bit equal to
1, the processor clears the IE bit in the PS register, thus disabling
further interrupts.
• Then, it begins execution of the interrupt-service routine.
• When a Return-from-interrupt instruction is executed, the saved
contents of the PS register are restored, setting the IE bit back to 1.
Hence, interrupts are again enabled.

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Sequence of events
1. The device raises an interrupt request.
2. The processor interrupts the program currently being executed
and saves the contents of the PC and PS registers.
3. Interrupts are disabled by clearing the IE bit in the PS to 0.
4. The action requested by the interrupt is performed by the
interrupt-service routine, during which time the device is
informed that its request has been recognized, and in response, it
deactivates the interrupt-request signal.
5. Upon completion of the interrupt-service routine, the saved
contents of the PC and PS registers are restored (enabling
interrupts by setting the IE bit to 1), and execution of the
interrupted program is resumed.

Handling Multiple Devices

• A number of devices capable of initiating interrupts

are connected to the processor. Each of these devices
are operationally independent, there is no definite
order in which they will generate interrupts.
• DeviceX may request an interrupt while an interrupt
caused by device Y is being serviced
• Several
devices may request interrupts at exactly the
same time.

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• This gives rise to a number of questions:

1. How can the processor determine which device is requesting an
interrupt?
2. Given that different devices are likely to require different interrupt-
service routines, how can the processor obtain the starting address of
the appropriate routine in each case?
3. Should a device be allowed to interrupt the processor while another
interrupt is being serviced?
4. How should two or more simultaneous interrupt requests be
handled?

• How these issues are handled vary from one computer to

another, and the approach taken is an important
consideration in determining the computer’s suitability
for a given application.
• When an interrupt request is received it is necessary to
identify the particular device that raised the request.
• If two devices raise interrupt requests at the same time,
it must be possible to break the tie and select one of the
two requests for service.
• When the interrupt-service routine for the selected
device has been completed, the second request can be
serviced.

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Polling to Recognize Interrupt

Request
• When the device raises an interrupt request, it sets the IRQ bit in its
status register to 1.
• To identify the interrupting device the interrupt-service routine polls
all I/O devices in the system.
• The first device encountered with its IRQ bit set to 1 is the device that
should be serviced.
• An appropriate subroutine is then called to provide the requested
service.
• The polling scheme is easy to implement.
• Disadvantage
 Time spent interrogating the IRQ bits of devices that may not be
requesting any service.

Vectored Interrupts
• The device requesting an interrupt may identify itself
directly to the processor.
 Device can do so by sending a special code (4 to 8 bits)
the processor over the bus.
 Code supplied by the device is used to find the
starting address of the interrupt-service routine.
• A commonly used scheme is to allocate permanently an
area in the memory to hold the starting addresses of
interrupt-service routines.
• These addresses are usually referred to as interrupt
vectors and they are said to constitute the interrupt-
vector table.

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• Example, 128 bytes may be allocated to hold a table of 32

interrupt vectors.
• The interrupt vector table is in the lowest-address range.
• The interrupt-service routines may be located anywhere in the
memory.
• When an interrupt request arrives, the information provided
by the requesting device is used as a pointer into the interrupt-
vector table, and the address in the corresponding interrupt
vector is automatically loaded into the program counter.
• When the processor is ready to receive the interrupt vector
code it activates INTA line.
• The i/o device responds by sending the vector code and turning
off INTR signal.

Interrupt Vector Table

Interrupt Starting
Number Address
of ISR
Memory
Low Order Address 1 4 Bytes
: High
2 ISR1 Starting Instruction
: Order
: 3 Address :
: :
128 Bytes :
:
: Return
:
32 ISR2 Starting Instruction
:
INTR
INTR is
INTA deactivated by
Processor Device
the device once
Interrupt Interface
Interrupt vector code is
Logic Vector Code
sent

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Interrupt Nesting
• Previously,
before the processor started executing
the interrupt service routine for a device, it disabled
the interrupts from the device.
• Ingeneral, same arrangement is used when
multiple devices can send interrupt requests to the
processor.
 During the execution of an interrupt service
routine of device, the processor does not accept
interrupt requests from any other device.
 Since the interrupt service routines are usually
short, the delay that this causes is generally
acceptable.

• However, for certain devices this delay may not be acceptable as it may
lead to erroneous operation.
 Which devices can be allowed to interrupt a processor when it is
executing an interrupt service routine of another device?
• A computer that keeps track of the time of day using a real-time clock.
• This is a device that sends interrupt requests to the processor at regular
intervals.
• For each of these requests, the processor executes a short interrupt-
service routine to increment a set of counters in the memory that keep
track of time.
• Proper operation requires that the delay in responding to an interrupt
request from the real-time clock be small in comparison with the
interval between two successive requests.
• To ensure that this requirement is satisfied, it is necessary to accept an
interrupt request from the clock during the execution of an interrupt-
service routine for another device, i.e., to nest interrupts.

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• I/O devices are organized in a priority structure:

 An interrupt request from a high-priority device is accepted while
the processor is executing the interrupt service routine of a low
priority device.
• A priority level is assigned to a processor that can be changed under
program control.
 Priority level of a processor is the priority of the program that is
currently being executed.
 The processor accepts interrupts only from devices that have
priorities higher than its own.
 When the processor starts executing the interrupt service routine of
a device, its priority is raised to that of the device.
 If the device sending an interrupt request has a higher priority than
the processor, the processor accepts the interrupt request.

• Processor’s priority is encoded in a few bits of the

processor status register.
 Priority can be changed by instructions that write
into the processor status register.
 Usually, these are privileged instructions, or
instructions that can be executed only in the
supervisor mode.
 Privileged instructions cannot be executed in the
user mode.
 Prevents a user program from accidentally or
intentionally changing the priority of the processor.
• If there is an attempt to execute a privileged
instruction in the user mode, it causes a special type
of interrupt called as privilege exception.

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Interrupt Nesting
• If nested interrupts are allowed, then each interrupt
service routine must save on the stack the saved
contents of the program counter and the status
register.
• This has to be done before the interrupt-service
routine enables nesting by setting the IE bit in the
status register to 1.

Simultaneous Requests
• When interrupt requests from two or more devices arrive
Simultaneously, the processor must decide which request
to service first.
 Polling the status registers of the I/O
 Priority is determined by the order in which the
devices are polled.
 Vectored interrupts
 Ensure that only one device is selected to send its
interrupt vector code. This is done by using
arbitration circuits

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Controlling I/O Device

Behavior
 Only those devices that are being used in a
program should be allowed to generate
interrupt requests.
 To control which devices are allowed to
generate interrupt requests, the interface
circuit of each I/O device has an interrupt-
enable bit.
 If the interrupt-enable bit in the device
interface is set to 1, then the device is
allowed to generate an interrupt-request.

• Interrupt-enable bit in the device’s interface circuit determines

whether the device is allowed to generate an interrupt request.
• Interrupt-enable bit in the processor status register or the
priority structure of the interrupts determines whether a given
interrupt will be accepted.

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• Only one or two bits in these registers are needed in handling the I/O
transfers.
• The remaining bits can be used to specify other aspects of the operation of the
device, or ignored if they are not needed.
• The keyboard status register includes bits KIN and KIRQ.
• The KIRQ bit is set to 1 if an interrupt request has been raised, but not yet
serviced.
• The keyboard may raise interrupt requests only when the interrupt-enable bit,
KIE, in its control register is set to 1.
• When both KIE and KIN bits are equal to 1, an interrupt request is raised and
the KIRQ bit is set to 1.
• The DIRQ bit in the status register of the display interface indicates whether
an interrupt request has been raised.
• Bit DIE in the control register of this interface is used to enable interrupts.

Processor Control Registers

• Control registers are used to deal with interrupts
• Four processor control registers.
• The status register, PS, includes the interrupt-enable bit, IE, in addition to
other status information.
• The IPS register is used to automatically save the contents of PS when an
interrupt request is received and accepted.
• At the end of the interrupt-service routine, the previous state of the
processor is automatically restored by transferring the contents of IPS into
PS.
Since there is only one register
available for storing the previous
status information, it becomes
necessary to save the contents of
IPS on the stack if nested
interrupts are allowed.

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• The IENABLE register allows the processor to selectively

respond to individual I/O devices.
• When a bit is set to 1, the processor will accept interrupt
requests from the corresponding device.
• The IPENDING register indicates the active interrupt
requests. This is convenient when multiple devices may
raise requests at the same time.
• A program can decide which interrupt should be serviced
first.
• In a 32-bit processor, the control registers are 32 bits
long.
• Hence it is possible to accommodate 32 I/O devices

• These registers cannot be accessed by arithmetic and logic

instructions or Load and Store instructions
• Special instructions or special addressing modes are provided to
access the processor control registers.
• In a RISC-style processor, the special instructions are
MoveControl R2, PS
-loads the contents of the program status register into R2
MoveControl IENABLE, R3
-places the contents of R3 into the IENABLE register
• These instructions perform transfers between control and general-
purpose registers.

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Examples of Interrupt Programs

• Consider again the task of reading a line of characters typed on a
keyboard, storing the characters in the main memory, and displaying
them on a display device
• Assume that
 A specific memory location, ILOC, is dedicated for dealing with
interrupts, and that it contains the first instruction of the
interrupt-service routine.
 The Main program has to read a line from the keyboard and store
the characters in successive byte locations in the memory, starting
at location LINE.
 The interrupt-service routine has been loaded in the memory,
starting at location ILOC.

• Whenever an interrupt request arrives at the processor,

and processor interrupts are enabled, the processor will
automatically:
 Save the contents of the program counter, either in a
processor register that holds the return address or on
the processor stack.
 Save the contents of the status register PS by
transferring them into the IPS register, and clear the IE
bit in the PS.
 Load the address ILOC into the program counter.

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• The Main program has to initialize the interrupt process as

follows:
1. Load the address LINE into a memory location PNTR. The
interrupt-service routine will use this location as a pointer to
store the input characters in the memory.
2. Enable interrupts in the keyboard interface by setting to 1 the
KIE bit in the KBD_CONT register.
3. Enable the processor to accept interrupts from the keyboard by
setting to 1 the KBD bit in its control register IENABLE.
4. Enable the processor to respond to interrupts in general by
setting to 1 the IE bit in the processor status register, PS.

• Once this initialization is completed, typing a character on the

keyboard will cause an interrupt request to be generated by the
keyboard interface.
• The program being executed at that time will be interrupted and the
interrupt-service routine will be executed.
• This routine must perform the following tasks:
1. Read the input character from the keyboard input data register. This
will cause the interface circuit to remove its interrupt request.
2. Store the character in the memory location pointed to by PNTR, and
increment PNTR.
3. Display the character using the polling approach.
4. When the end of the line is reached, disable keyboard interrupts and
inform the Main program.
5. Return from interrupt.

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A RISC-style program that reads a line of characters

using interrupts, and displays the line using polling.

A RISC-style program that reads a line of characters

using interrupts, and displays the line using polling

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A RISC-style program that reads a line of characters

using interrupts, and displays the line using polling

• When the end of the input line is detected the interrupt-service

routine
 Clears the KIE bit in register KBD_CONT, as no further
input is expected.
 Sets to 1 the variable EOL (End Of Line), which was initially
cleared to 0.
• KIE bit is checked periodically by the Main program to
determine when the input line is ready for processing.
• The EOL variable provides a means of signaling between the
Main program and the interrupt-service routine.

• The last three instructions in the Main program are used to set to 1
the interrupt-enable bit in PS.
• Only MoveControl instructions can access the contents of a
control register.
• The contents of PS are loaded into a general-purpose register, R2,
modified and then written back into PS.
• Using the Or instruction to modify the contents affects only the IE
bit and leaves the rest of the bits in PS unchanged.
• When multiple I/O devices raise interrupt requests, it is necessary
to determine which device has requested an interrupt.
• This can be done in software by checking the information in the
IPENDING control register and choosing the interrupt-service
routine that should be executed.

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Example 2
• Suppose a program needs to display a page of
text stored in the memory.
• Thiscan be done by having the processor send a
character whenever the display interface is
ready, which may be indicated by an interrupt
request.
• Assume that both the display and the keyboard
are used by this program, and that both are
enabled to raise interrupt requests.

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Main Program
• Initialize
any variables needed by the interrupt-
service routines, such as the memory buffer pointers.
• Enables interrupts in both the keyboard and display
interfaces.
• Enables
interrupts in the processor control register
IENABLE.
• Enable the processor to respond to interrupts by
setting the IE bit in the processor status register, PS
to 1.
• Note that the immediate value 6, which is loaded
into this register, sets bits KBD and DISP to 1.

• Whenever an interrupt request arrives the processor will

 Automatically save the contents of the program counter (PC) and
then load the address ILOC into PC.
 Save the contents of the status register (PS) by transferring them
into the IPS register, and disable interrupts.
 Identify the interrupting device using processor control register
IPENDING.
• ISR uses registers R2 and R3 hence the contents of these registers
must be saved on the stack and later restored.
• Also save the contents of the subroutine linkage register, because an
interrupt can occur while ISR is being executed and the interrupt-
service routine calls a subroutine.
• The circuit that detects interrupts sets to 1 the appropriate bit in
IPENDING for each pending request.

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• The contents of IPENDING are loaded into general purpose

register R2, and then examined to determine which interrupts
are pending.
• If the display has a pending interrupt, then its ISR is executed.
• If not, then a check is made for the keyboard.
• This may be followed by checking any other devices that could
have pending requests.
• The order in which the bits in IPENDING are checked
establishes a priority for the interrupting devices in case of
simultaneous requests.

• The program parts that handle interrupt requests and provide the
corresponding service to the requesting devices are often referred
to as the interrupt handler.
• The interrupt handler starts at the fixed address ILOC
• The individual ISRs are just subroutines that can be placed
anywhere in the memory.
• In processors that use vectored interrupts, the circuit that detects
interrupt requests automatically loads a different address into the
program counter for each interrupt that is assigned a specific
location in the interrupt-vector table.
• A separate interrupt-service routine is executed to completion for
each pending request, even if multiple interrupt requests are
raised at the same time.

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Exceptions
• Interrupts caused by interrupt-requests sent by I/O devices.
• Interruptscould be used in many other situations where the
execution of one program needs to be suspended and
execution of another program needs to be started.
• In general, the term exception is used to refer to any event
that causes an interruption.
 Interrupt-requests from I/O devices is one type of an
exception.
• Other types of exceptions are:
 Recovery from errors
 Debugging
 Privilege exception

Recovery from Errors

 Many sources of errors in a processor. For example:
1. Error in the data stored.
 Error checking code in memory detects errors in stored data.
 The control hardware detects it and raises interrupt.
2. Error during the execution of an instruction.
 Unusual conditions while executing a program causes processor
to interrupt a program.
 Opcode field not valid.
 Division by zero.
 When such errors are detected, exception processing is initiated.
 Processor takes the same steps as in the case of I/O interrupt-
request.
 It suspends the execution of the current program, and starts
executing an exception-service routine.

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• Difference between handling I/O interrupt-request

and handling exceptions due to errors:
 In case of I/O interrupt-request, the processor
usually completes the execution of an instruction
in progress before branching to the interrupt-
service routine.
 In case of exception processing however, the
execution of an instruction in progress usually
cannot be completed.

Debugging
• Debugger uses exceptions to provide important features:
 Trace,
 Breakpoints.
• Tracemode:
 Exception occurs after the execution of every instruction.
 Debugging program is used as the exception-service routine.
• Breakpoints:
 Exception occurs only at specific points selected by the user.
 TRAP instruction is used for this purpose.
 Debugging program is used as the exception-service routine.

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Privilege exception
• Certain instructions can be executed only when the
processor is in the supervisor mode. These are called
privileged instructions.
• If
an attempt is made to execute a privileged instruction
in the user mode, a privilege exception occurs.
• Privilege exception causes:
 Processor to switch to the supervisor mode,
 Execution of an appropriate exception-servicing
routine.

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