Technical College / Kirkuk

Electronic and Control Techniques Eng. Dept.

Third Year

COMPUTER ARCHITECTURE
(MICROCONTROLLERS)

Prepared by
Dr. Abdulrahman Ikram Siddiq
2015

1
 Contents

Topic Page
1 Background 3
2 Hardware Components 4
3 System Busses 4
4 Memory 5
5 Memory Organization 6
6 Memory Classification 7
7 I/O Device Interfacing 22
8 C and General Purpose P 23
9 AVR Microcontrollers 24
10 Device General Architecture 26
11 Development Boards 28
12 ATMEGA328 28
13 AVR CPU Core 32
14 Instruction Execution Timing 38
15 AVR Memories 41
16 I/O Ports 45
17 Reset and Interrupt Handling 51
18 External Interrupts 54
19 Analog Comparator 55
20 Analog-to-Digital Convertors 55

References:

[1] DATASHEET of ATMEL 8-BIT Microcontroller with 4/8/16/32kbytes in-system

programmable flash.

[2] Muhammad Ali Mazidi, The AVR Microcontroller and Embedded System using
assembly and C, Prentice Hall, 2011.

[3] A lot of similar references in the Internet.

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Background

 A computer system consists of hardware and software components.

 Hardware includes microprocessors, memories, and input/output devices.
 Software includes the operating systems, programming languages, and application
progs.
 Programming languages may be classified as follows:
programming
 A High level language is a set of instructions that let the langs
programmer perform arithmetic, logical, data transfer,
High level
conditional branching, and I/O operations. such as qBASIC,
C++, PASKAL,
VBASIC, ...
 It is not necessary that the programmer has strict information
about the internal structure of the computer system. Low level
such as Assembly
 High level programs are translated to the machine language of and machine lang.

the specific processor using a software called "compiler", to be executed.

 A Low level language is a set of instructions that deal with the internal structure of
the processor and the computer system, to perform arithmetic, logical, data transfer,
conditional branching, and I/O operations.

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 HARDWARE COMPONENTS

SYSTEM BUSES

The hardware of a computer system consists of components connected by wire lines called
busses. There are three types of busses, namely the data bus, address bus, and control bus.

Control Bus

Input Output
Memory
devices devices

Processor

Address Bus

Data Bus

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Data bus: is a set of bi-directional lines used to transfer data between different hardware
components. The number of lines of a data bus depends on the CPU data word size (8 bits,
16 bits, …).

Address bus: is a set of uni-directional lines used by the processor to transfer the address
information to determine a memory location or an I/O device. The number of address lines
depends on the capability of the processor. An n-bit address bus 2n different addresses.
Foe 16-bit address bus, the number of addressable locations is Kbytes.

Control bus: a number of wires used by the processor to control the operation of the other
components of the system, such as memory read, memory write, I/O read, I/O write, … .

MEMORY

A memory chip consists of a large number of memory locations. Each location stores binary
data. The size of a memory location is typically 8 bits (1 Byte). The processor identifies a
location by its address.
Chip Select
Mem. Read 0 01001111
Mem. Write 1 00110011
2 10101010
3 00111100 Memory
Addresses
4 01001101 Locations
5 10011000
6 00011100
ADDRESS
7 10111000

DATA

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6
Memory Classification

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Draw it on the board

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 I/O Port Interfacing

 The data flow between the CPU and the I/O devices is performed through connection
points called ports.
 The ports are under the control of the CPU.
 The CPU identifies (activates) an input or output device by placing its address on the
address bus and enabling the associated port. Then, the data flows through this port.
 For example, in the figures below, the address of the output device is 0xFF00 and the
input device is 0xF000.

CLASS WORK: Design, draw and specify the addresses of a microcomputer system with the
following components:
 CPU (8-bit data bus and 16-bit address bus)
 1 KB ROM and 4 KB RAM
 One input port and one output port (the ports are memory mapped)

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23
  The AVR is a modified Harvard architecture 8-bit RISC single-chip microcontroller,
which was developed by Atmel in 1996.

 The AVR was one of the first microcontroller families to use on-chip flash memory for
program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM
used by other microcontrollers.

 The AVR architecture was conceived by two students at the Norwegian Institute of
Technology (NTH), Alf-Egil Bogen and Vegard Wollan.

 When the technology was sold to Atmel from Nordic VLSI, the internal architecture
was further developed by Bogen and Wollan at Atmel Norway, a subsidiary of Atmel.

 It is commonly accepted that AVR stands for Alf and Vegard RISC processor.

 Among the first of the AVR line was the AT90S8515, which is a 40-pin DIP package
has the same pinout as an 8051 microcontroller, including the external multiplexed
address and data bus.

 The AVR 8-bit microcontroller architecture was introduced in 1997. By 2003, Atmel
had shipped 500 million AVR flash microcontrollers.

BASIC FAMILIES

AVRs are generally classified into the following:

 tinyAVR — the ATtiny series

o 0.5–16 kB program memory

o 6–32-pin package
o Limited peripheral set

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 megaAVR — the ATmega series

o 4–512 KB program memory

o 28–100-pin package
o Extended instruction set (multiply instructions and instructions for handling
larger program memories)
o Extensive peripheral set

 XMEGA — the ATxmega series

o 16–384 KB program memory
o 44–64–100-pin package (A4, A3, A1)
o 32-pin package : XMEGA-E (XMEGA8E5)
o Extended performance features, such as DMA, "Event System", and
cryptography support.
o Extensive peripheral set with ADCs

 Application-specific AVR
o megaAVRs with special features not found on the other members of the AVR
family, such as LCD controller, USB controller, advanced PWM, CAN, etc.

 FPSLIC (AVR with FPGA)

o FPGA 5K to 40K gates
o SRAM for the AVR program code, unlike all other AVRs
o AVR core can run at up to 50 MHz

 32-bit AVRs
In 2006 Atmel released microcontrollers based on the 32-bit AVR32 architecture. They
include SIMD and DSP instructions, along with other audio- and video-processing
features. This 32-bit family of devices is intended to compete with the ARM-based
processors. The instruction set is similar to other RISC cores, but it is not compatible
with the original AVR or any of the various ARM cores.

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 DEVICE GENERAL ARCHITECTURE
 The AVR is a modified Harvard architecture machine, where program and data are
stored in separate physical memory systems that appear in different address spaces,
but having the ability to read data items from program memory using special
instructions.

Von Neumann Model for Stored Program Computers

Harvard Architecture

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 Harvard Architecture Advantages

Separate instruction and data paths

Simultaneous accesses to instructions & data
Hardware can be optimized for access type and bus width.

 Flash, EEPROM, and SRAM are all integrated onto a single chip, removing the need
for external memory in most applications. Some devices have a parallel external bus
option to allow adding additional data memory or memory-mapped devices. Almost
all devices (except the smallest TinyAVR chips) have serial interfaces, which can be
used to connect larger serial EEPROMs or flash chips.

Program memory

 Program instructions are stored in non-volatile flash memory. Although the MCUs are
8-bit, each instruction takes one or two 16-bit words.

 The size of the program memory is usually indicated in the naming of the device itself
(e.g., the ATmega64x line has 64 KB of flash, while the ATmega32x line has 32 KB).

 There is no provision for off-chip program memory; all code executed by the AVR
core must reside in the on-chip flash. However, this limitation does not apply to the
AT94 FPSLIC AVR/FPGA chips.

Internal data memory

 The data address space consists of the register file, I/O registers, and SRAM.

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 DEVELOPMENT BOARDS

 AVRs have a large following due to the

free and inexpensive development tools
available, including development boards
and free development software.

 The AVRs are sold under various names

that share the same basic core, but with
different peripheral and memory
combinations.

 Compatibility between chips in each family is fairly good, although I/O controller
features may vary.

The Arduino physical computing platform is based on an ATmega328.

The ATmega1280 and ATmega2560, with more pinout and memory capabilities, have also been employed
to develop the Arduino Mega platform.

Arduino boards can be used with conventional programming environments (C, assembler, etc.).

USB-based AVRs have been used in the Microsoft Xbox hand controllers. The link between the controllers
and Xbox is USB.

ATMEL 8-BIT MICROCONTROLLER WITH 32KBYTES

IN-SYSTEM PROGRAMMABLE FLASH
Features
 High Performance, CMOS Low Power 8-Bit
Microcontroller
 Advanced RISC Architecture
 131 Powerful Instructions – Most Single
Clock Cycle Execution
 32 x 8 General Purpose Working Registers
 Fully Static Operation
 Up to 20 MIPS Throughput at 20MHz
 On-chip 2-cycle Multiplier

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  High Endurance Non-volatile Memory Segments
 4/8/16/32KBytes of In-System Self-Programmable Flash program memory
 256/512/512/1KBytes EEPROM
 512/1K/1K/2KBytes Internal SRAM
 Data retention: 20 years at 85oC/100 years at 25oC
 Optional Boot Code Section with Independent Lock Bits
 In-System Programming by On-chip Boot Program
 True Read-While-Write Operation
 Programming Lock for Software Security

Peripheral Features
 Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
 One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
 Capture Mode
 Real Time Counter with Separate Oscillator
 Six PWM Channels
 6-channel 10-bit ADC
 Programmable Serial USART
 Master/Slave SPI Serial Interface
 Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
 Programmable Watchdog Timer with Separate On-chip Oscillator
 On-chip Analog Comparator
 Interrupt and Wake-up on Pin Change

Special Microcontroller Features

 Power-on Reset
 Internal Calibrated Oscillator
 External and Internal Interrupt Sources
 23 Programmable I/O Lines
 O erati o ta e 1.8 - 5.5V
 em erat re a e -40oC to 85oC
 eed rade - 4MHz@1.8 - 5.5V, 0 - 10MHz@2.7 - 5.5.V, 0 - 20MHz @ 4.5 - 5.5V
 Power Consumption at 1MHz, 1.8V, 25oC
Active Mode: 0.2mA
Power-dow Mode .1μA
Power-save Mode .75μA

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 PIN CONFIGURATIONS
The Pinout of ATmega48A/PA/88A/PA/168A/PA/328/P is shown below:

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 PIN DESCRIPTIONS
1. VCC: Digital supply voltage.
2. GND: Ground.
3. Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2
 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit).
 The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability.
 As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated.
 The Port B pins are tristated when a reset condition becomes active, even if the clock
is not running.
4.Port C (PC5:0)
 Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit).
 The PC5...0 output buffers have symmetrical drive characteristics with both high sink
and source capability.
 As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated.
 The Port C pins are tristated when a reset condition becomes active, even if the clock
is not running.
5. PC6/RESET
 If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin.
 Note that the electrical characteristics of PC6 differ from those of the other pins of
Port C.
 If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on
this pin for longer than the minimum pulse length will generate a Reset, even if the
clock is not running.
6. Port D (PD7:0)
 Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit).
 The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability.
 As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated.

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  The Port D pins are tristated when a reset condition becomes active, even if the clock
is not running. PC 0:5 ADC(0:5)
7. AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be
externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be
connected to VCC through a low-pass filter.
8. AREF is the analog reference pin for the A/D Converter.

AVR CPU Core

Overview
This section discusses the AVR core architecture in general. The main function of the CPU
core is to ensure correct program execution. The CPU must therefore be able to access
memories, perform calculations, control peripherals, and handle interrupts.

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 In order to maximize performance and parallelism, the AVR uses a Harvard
architecture – with separate memories and buses for program and data.
 Instructions in the program memory are executed with a single level pipelining. While
one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock
cycle.
 The program memory is In-System Reprogrammable Flash memory.
 The fast-access Register File contains 32 x 8-bit general purpose working registers
with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit
(ALU) operation.
 In a typical ALU operation, two operands are output from the Register File, the
operation is executed, and the result is stored back in the Register File – in one
clock cycle.
 Six of the 32 registers can be used as three 16-bit indirect address register pointers
for Data Space addressing – enabling efficient address calculations. One of these
address pointers can also be used as an address pointer for look up tables in Flash
program memory. These added function registers are the 16-bit X-, Y-, and Z-
register, described later in this section.

 The ALU supports arithmetic and logic operations between registers or between a
constant and a register. Single register operations can also be executed in the ALU.

 After an arithmetic operation, the Status Register is updated to reflect information

about the result of the operation.

 Most AVR instructions have a single 16-bit word format. Every program memory
address contains a 16- or 32-bit instruction.
 Program Flash memory space is divided in two sections, the Boot Program section
and the Application Program section.
 Both sections have dedicated Lock bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the
Boot Program section.
 Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user
programs must initialize the SP in the Reset routine (before subroutines or interrupts
are executed). The Stack Pointer (SP) is read/write accessible in the I/O space.
 The data SRAM can easily be accessed through the five different addressing modes
supported in the AVR architecture.

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  A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All interrupts have a separate
Interrupt Vector in the Interrupt Vector table.
 The interrupts have priority in accordance with their Interrupt Vector position. The
lower the Interrupt Vector address, the higher the priority.
 The I/O memory space contains 64 addresses for CPU peripheral functions as
Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed
directly, or as the Data Space locations following those of the Register File, 0x20 -
0x5F. In addition, the ATmega48A/PA/88A/PA/168A/PA/328/P has Extended I/O
space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD
instructions can be used.

ALU – Arithmetic & Logic Unit

 The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers.
 Within a single clock cycle, arithmetic operations between general purpose registers
or between a register and an immediate are executed.
 The ALU operations are divided into three main categories – arithmetic, logical, and
bit-functions.
 Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional format. See the
“Instruction Set” section for a detailed description.

Status Register
 The Status Register contains information about the result of the most recently
executed arithmetic instruction.
 This information can be used for altering program flow in order to perform conditional
operations.
 Note that the Status Register is updated after all ALU operations, as specified in the
Instruction Set Reference.

SREG – AVR Status Register

The AVR Status Register – SREG – is defined as:

Bit 7 – I: Global Interrupt Enable

 The Global Interrupt Enable bit must be set (=1) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers.

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  If the Global Interrupt Enable Register is cleared (=0), none of the interrupts are
enabled independent of the individual interrupt enable settings. The I-bit is cleared
by hardware after an interrupt has occurred, and is set by the RETI instruction to
enable subsequent interrupts.
 The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the instruction set reference.

Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or
destination for the operated bit. A bit from a register in the Register File can be copied into
T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register
File by the BLD instruction.

Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is
useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

Bit 4 – S: Sign Bit, S = N V

The S-bit is always an XOR between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.

Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the
“Instruction Set Description” for detailed information.

Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.

Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.

Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.

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General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are
supported by the Register File:
 One 8-bit output operand and one 8-bit result input
 Two 8-bit output operands and one 8-bit result input
 Two 8-bit output operands and one 16-bit result input
 One 16-bit output operand and one 16-bit result input

 Most of the instructions operating on the Register File have direct access to all
registers, and most of them are single cycle instructions.
 Each register is also assigned a data memory address, mapping them directly
into the first 32 locations of the user Data Space.
 Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X-, Y-
and Z-pointer registers can be set to index any register in the file.

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The X-register, Y-register, and Z-register
 The registers R26...R31 have some added functions to their general purpose
usage. These registers are 16-bit address pointers for indirect addressing of
the data space.
 The three indirect address registers X, Y, and Z are defined as shown below.
 In the different addressing modes these address registers have functions as
fixed displacement, automatic increment, and automatic decrement.

Stack Pointer
 The Stack is mainly used for storing temporary data, for storing local variables
and for storing return addresses after interrupts and subroutine calls.
 Note that the Stack is implemented as growing from higher to lower memory
locations. The Stack Pointer Register always points to the top of the Stack.
The Stack Pointer points to the data SRAM Stack area where the Subroutine
and Interrupt Stacks are located.
 A Stack PUSH command will decrease the Stack Pointer.
 The Stack in the data SRAM must be defined by the program before any
subroutine calls are executed or interrupts are enabled.
 Initial Stack Pointer value equals the last address of the internal SRAM and
the Stack Pointer must be set to point above start of the SRAM.
 The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space.
 The number of bits actually used is implementation dependent.
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  Note that the data space in some implementations of the AVR architecture is
so small that only SPL is needed. In this case, the SPH Register will not be
present.

Instruction Execution Timing

 This section describes the general access timing concepts for instruction
execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated
from the selected clock source for the chip. No internal clock division is used.
 When the device is powered-on, the Program Counter is set to 0.
 The instruction at the location in Flash Memory at the address indicated by the
Program Counter is fetched and placed in the Instruction Register
 The opcode and operands within the instruction are extracted by the
Instruction Decoder
 The control lines from the I.D. activate the particular circuitry within the ALU
that is capable of processing that particular opcode. The ALU executes the
instruction.
 The Program Counter is automatically incremented and the cycle repeats.

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Let’s consider the case of how the ADD instruction is represented as a machine-
executable instruction

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40
 The figure below shows the parallel instruction fetches and instruction
executions enabled by the Harvard architecture and the fast-access Register
File concept. This is the basic pipelining concept to obtain up to 1 MIPS per
MHz with the corresponding unique results for functions per cost, functions per
clocks, and functions per power-unit.

 The figure below shows the internal timing concept for the Register File. In a
single clock cycle an ALU operation using two register operands is executed,
and the result is stored back to the destination register.

AVR Memories

 The AVR architecture has two main memory spaces, the Data Memory and the
Program Memory space.
 In addition, the ATmega48A/PA/88A/PA/168A/PA/328/P features an EEPROM
Memory for data storage.
 All three memory spaces are linear and regular.

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 1. In-System Reprogrammable Flash Program Memory

 The ATmega48A/PA/88A/PA/168A/PA/328/P contains 4/8/16/32Kbytes On-chip In-

System Reprogrammable Flash memory for program storage.
 Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as
2/4/8/16K x 16.
 For software security, the Flash Program memory space is divided into two sections,
Boot Loader Section and Application Program Section in ATmega88PA and
ATmega168PA.
 The Flash memory has an endurance of at least 10,000 write/erase cycles. The
 ATmega48A/PA/88A/PA/168A/PA/328/P Program Counter (PC) is 11/12/13/14 bits
wide, thus addressing the 2/4/8/16K program memory locations.

The following figure shows the Program Memory Map ATmega88A, ATmega88PA,
ATmega168A, ATmega168PA, ATmega328 and ATmega328P

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 2. SRAM Data Memory

 The ATmega48A/PA/88A/PA/168A/PA/328/P is a complex microcontroller with

more peripheral units than can be supported within the 64 locations reserved
in the Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
 The lower 768/1280/1280/2303 data memory locations address both the
Register File, the I/O memory, Extended I/O memory, and the internal data
SRAM. The first 32 locations address the Register File, the next 64 location
the standard I/O memory, then 160 locations of Extended I/O memory, and the
next 512/1024/1024/2048 locations address the internal data SRAM.
 The five different addressing modes for the data memory cover: Direct,
Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect
with Post-increment. In the Register File, registers R26 to R31 feature the
indirect addressing pointer registers.
 The direct addressing reaches the entire data space. The Indirect with
Displacement mode reaches 63 address locations from the base address
given by the Y- or Z register.
 When using register indirect addressing modes with automatic pre-decrement
and post-increment, the address registers X, Y, and Z are decremented or
incremented.
 The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O
Registers, and the 512/1024/1024/2048 bytes of internal data SRAM in the
ATmega48A/PA/88A/PA/168A/PA/328/P are all accessible through all these
addressing modes. The Data Memory Map is shown below

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  The internal data SRAM access is performed in two clkCPU cycles as described
in the figure below:

EEPROM Data Memory

 The ATmega48A/PA/88A/PA/168A/PA/328/P contains 256/512/512/1Kbytes of
data EEPROM memory. It is organized as a separate data space, in which
single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles.

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 I/O Ports

 All AVR ports have true Read-Modify-Write functionality when used as general
digital I/O ports.
 This means that the direction of one port pin can be changed without
unintentionally changing the direction of any other pin with the SBI and CBI
instructions. The same applies when changing drive value (if configured as
output) or enabling/disabling of pull-up resistors (if configured as input).
 Each output buffer has symmetrical drive characteristics with both high sink
and source capability. The pin driver is strong enough to drive LED displays
directly.
 All port pins have individually selectable pull-up resistors with a supply-voltage
invariant resistance.
 All I/O pins have protection diodes to both VCC and Ground as indicated in the
figure below.

I/O Pin Equivalent Schematic

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 A lower case “x” represents the numbering letter for the port, and a lower case
“n” represents the bit number. However, when using the register or bit defines
in a program, the precise form must be used. For example, PORTB3 for bit no.
3 in Port B, here documented generally as PORTxn.

 Three I/O memory address locations are allocated for each port,
Data Direction Register – DDRx, and
Data Register – PORTx,
Port Input Pins – PINx.

 In the Atmega328, there are three 8-bit IO Ports

Port B, Port C & Port D

Pins identified as PBn, PCn or PDn (n=0..7)

 Each pin can be configured as:

Input with internal pull-up

Input with no pull-up (tri-state)
Output low
Output high

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47
48
0

49
50
 00

RESET AND INTERRUPT HANDLING

 The AVR provides several different interrupt sources. These interrupts and the
separate Reset Vector each have a separate program vector in the program
memory space.
 All interrupts are assigned individual enable bits which must be written logic
one together with the Global Interrupt Enable bit in the Status Register in order
to enable the interrupt.
 Depending on the Program Counter value, interrupts may be automatically
disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature
improves software security.
 The lowest addresses in the program memory space are by default defined as
the Reset and Interrupt Vectors.
 The complete list of vectors is shown below. The list also determines the
priority levels of the different interrupts.

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Interrupt Vectors in ATmega328 and ATmega328P

 The lower the address the higher is the priority level. RESET has the highest
priority, and next is INT0 – the External Interrupt Request 0. The Interrupt
Vectors can be moved to the start of the Boot Flash section by setting the
IVSEL bit in the MCU Control Register (MCUCR).
 When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all
interrupts are disabled. The user software can write logic one to the I-bit to
enable nested interrupts.

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  All enabled interrupts can then interrupt the current interrupt routine. The I-bit
is automatically set when a Return from Interrupt instruction – RETI – is
executed.
 There are basically two types of interrupts. The first type is triggered by an
event that sets the Interrupt Flag. For these interrupts, the Program Counter is
vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag.
 Interrupt Flags can also be cleared by writing a logic one to the flag bit
position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and
remembered until the interrupt is enabled, or the flag is cleared by software.
 Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and
remembered until the Global Interrupt Enable bit is set, and will then be
executed by order of priority.
 The second type of interrupts will trigger as long as the interrupt condition is
present. These interrupts do not necessarily have Interrupt Flags. If the
interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
 When the AVR exits from an interrupt, it will always return to the main program
and execute one more instruction before any pending interrupt is served.
 Note that the Status Register is not automatically stored when entering an
interrupt routine, nor restored when returning from an interrupt routine. This
must be handled by software.
 When using the CLI instruction to disable interrupts, the interrupts will be
immediately disabled. No interrupt will be executed after the CLI instruction,
even if it occurs simultaneously with the CLI instruction.
 The following example shows how this can be used to avoid interrupts during
the timed EEPROM write sequence.

C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */

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  When using the SEI instruction to enable interrupts, the instruction following
SEI will be executed before any pending interrupts, as shown in this example.

C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */

Interrupt Response Time

 The interrupt execution response for all the enabled AVR interrupts is four
clock cycles minimum.
 After four clock cycles the program vector address for the actual interrupt
handling routine is executed.
 During this four clock cycle period, the Program Counter is pushed onto the
Stack. The vector is normally a jump to the interrupt routine, and this jump
takes three clock cycles.
 If an interrupt occurs during execution of a multi-cycle instruction, this
instruction is completed before the interrupt is served.
 If an interrupt occurs when the MCU is in sleep mode, the interrupt execution
response time is increased by four clock cycles. This increase comes in
addition to the start-up time from the selected sleep mode.
 A return from an interrupt handling routine takes four clock cycles. During
these four clock cycles, the Program Counter (two bytes) is popped back from
the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is
set.

External Interrupts
 The External Interrupts are triggered by the INT0 and INT1 pins or any of the
PCINT23...0 pins.
 Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or
PCINT23...0 pins are configured as outputs. This feature provides a way of
generating a software interrupt.
 The pin change interrupt PCI2 will trigger if any enabled PCINT[23:16] pin
toggles.
 The pin change interrupt PCI1 will trigger if any enabled PCINT[14:8] pin
toggles.
 The pin change interrupt PCI0 will trigger if any enabled PCINT[7:0] pin
toggles.
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  The PCMSK2, PCMSK1 and PCMSK0 Registers control which pins contribute
to the pin change interrupts.
 Pin change interrupts on PCINT23...0 are detected asynchronously. This
implies that these interrupts can be used for waking the part also from sleep
modes other than idle mode.
 The External Interrupts can be triggered by a falling or rising edge or a low
level. This is set up as indicated in the specification for the External Interrupt
Control Registers – EICRA (INT2:0).
 When the external interrupt is enabled and is configured as level triggered, the
interrupt will trigger as long as the pin is held low.
 Low level interrupts and the edge interrupt on INT2:0 are detected
asynchronously. This implies that these interrupts can be used for waking the
part also from sleep modes other than idle mode. The I/O clock is halted in all
sleep modes except idle mode.

Analog Comparator
 The Analog Comparator compares the input values on the positive pin AIN0
and negative pin AIN1.
 When the voltage on the positive pin AIN0 is higher than the voltage on the
negative pin AIN1, the Analog Comparator output, ACO, is set (=1).

Analog-to-Digital Converter

Features:
• 10-bit Resolution
• 13 - 260μs Conversion Time
• 6 Multiplexed Single Ended Input Channels from the pins of Port A.
• 0 - VCC ADC Input Voltage Range
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler

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Example
More instructions