HVLED815PF

Offline LED driver with primary-sensing and high power factor

up to 15 W
Datasheet - production data

Applications
 AC-DC LED driver bulb replacement lamps
up to 15 W, with high power factor
 AC-DC LED drivers up to 15 W

Description
The HVLED815PF device is a high voltage
primary switcher intended for operating directly
SO16N from the rectified mains with minimum external
parts and enabling high power factor (> 0.90) to
provide an efficient, compact and cost effective
solution for LED driving. It combines a high-
performance low voltage PWM controller chip and
Features an 800 V, avalanche rugged Power MOSFET, in
the same package. There is no need for the
 High power factor capability (> 0.9) optocoupler thanks to the patented primary
 800 V, avalanche rugged internal 6  Power sensing regulation (PSR) technique. The device
MOSFET assures protection against LED string fault (open
 Internal high voltage startup or short).
 Primary sensing regulation (PSR)
Table 1. Device summary
 ± 3% accuracy on constant LED output current
Order code Package Packaging
 Quasi-resonant (QR) operation
 Optocoupler not needed HVLED815PF Tube
SO16N
 Open or short LED string management HVLED815PFTR Tape and reel

 Automatic self supply

February 2014 DocID023409 Rev 5 1/34

This is information on a product in full production. www.st.com

Downloaded from Arrow.com.

 Contents HVLED815PF

Contents

1 Principle application circuit and block diagram . . . . . . . . . . . . . . . . . . . 4

1.1 Principle application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Secondary side demagnetization detection and triggering block . . . . . . . 17
4.5 Constant current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6 Constant voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7 Voltage feedforward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.8 Burst mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 24
4.9 Soft-start and starter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.10 Hiccup mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.11 High power factor implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.12 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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 HVLED815PF List of figures

List of figures

Figure 1. Application circuit for high power factor LED driver - single range input. . . . . . . . . . . . . . . . 4
Figure 2. Application circuit for standard LED driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. OFF-state drain and source current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. COSS output capacitance variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Startup current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Quiescent current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Operating supply current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Quiescent current during fault test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Multi-mode operation of HVLED815PF (constant voltage operation) . . . . . . . . . . . . . . . . . 15
Figure 12. High voltage start-up generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 17
Figure 14. DMG block, triggering block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. Drain ringing cycle skipping as the load is progressively reduced . . . . . . . . . . . . . . . . . . . 18
Figure 16. Current control principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Constant current operation: switching cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Voltage control principle: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 19. Feedforward compensation: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 20. Load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. Hiccup mode OCP: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 22. High power factor implementation connection - single range input . . . . . . . . . . . . . . . . . . 27
Figure 23. Suggested routing for the LED driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 24. SO16N package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 25. SO16N recommended footprint (dimensions are in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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 1 Principle application circuit and block diagram

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1.1 Principle application circuit
Figure 1. Application circuit for high power factor LED driver - single range input

Lin T1 O u tp o u t D i o d e Vout
VIN 1 10 J1
CON1

3
2 9

Cin
Cin
EMI FILTER Bridge Diode R12

+
Rf 3 8 C12 C13
J2 F1 1A_DIP 4 Minimum Load
2 1 Cout Bulk Cout SMD
7

Rsnubber
Lf

Csnubber
CON1

-
5 6 J3
Cf Cf CON1
TRANSFORMER

4
J4 Lf
Principle application circuit and block diagram

CON1 Rf
C10
U1
VIN D5 Rsense HVLED8xxPF
Y 1 - SAFETY
Rsense 1
SOURCE

S nubber D iode
RA 16

DocID023409 Rev 5
DRAIN
R1 (500 - 1.5k)CS 2
CS 15
220pF-1nF DRAIN
RB
C_Vcc (10uF MIN) VCC 3 14
VCC DRAIN

COS Filter (1uF) 4 13

GND DRAIN

ROS C_ILED (10uF) 5 CS RPF D4

ILED

CS Rf b DMG 6 DMG Rdmg

DMG

Cf (330nF-680nF) 7
Rf (8k-15k)
COMP VCC D2
1N 4148
NA 8 R-VCC (10-100ohm)
Cp (1n-10nF) N.A. C_VCC (470nF)

AM13207v1
HVLED815PF
 Figure 2. Application circuit for standard LED driver

Downloaded from Arrow.com.

HVLED815PF

T2 O u tp o u t D i o d e 1 Vout
VIN 1 10 J5
CON1

3
2 9
EMI FILTER Bridge Diode R18

+
Rf 3 8 C16 C27
J7 F2 1A_DIP 4 Minimum Load
2 1 Cout Bulk Cout SMD

Cin
7

Csnubber
Lf

Rsnubber
CON1

-
5 6 J6
Cf Cf CON1
TRANSFORMER

4
J8 Lf

CON1 Rf
C23
U2
Rsense HVLED8xxPF
Y 1 - SAFETY
Rsense 1
SOURCE

S nubber D iode
16
DRAIN
2
CS 15
DRAIN

14

DocID023409 Rev 5
C_Vcc (10uF) VCC 3
VCC DRAIN

4 13
GND DRAIN

C_ILED (10uF) 5
ILED

Rf b DMG 6 DMG Rdmg

DMG

Cf (330nF/680nF) 7
Rf (8.2k-15k)
COMP VCC D8
1N 4148
NA 8 R-VCC (10ohm)
Cp (1nF/10nF) N.A. C_VCC (470nF)

AM13208v1

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Principle application circuit and block diagram
 1.2 Block diagram

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Figure 3. Block diagram

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+ VIN

VCC HV start-up &

Supply Logic
DRAIN
LED
Vref
PROTECTION &
FEEDFORWARD
LOGIC

DEMAG
LOGIC
RDMG DRIVING
DMG CONSTANT LOGIC
Principle application circuit and block diagram

CURRENT
REGULATION
RFB 3.3 V
VILED VCS
Vref 1V
OCP

DocID023409 Rev 5
Constant Voltage RA
Regulation

COMP ILED GND CS R1 SOURCE

RCOMP
CLED
RSENSE
CCOMP

RPF ROS

AM13209v1
HVLED815PF
 HVLED815PF Pin description and connection diagrams

2 Pin description and connection diagrams

Figure 4. Pin connection (top view)

SOURCE 11 16
16 DRAIN
CS 22 15
15 DRAIN
VCC 33 14
14 DRAIN
GND 44 13
13 DRAIN
ILED 55 12
12 N.C.
DMG 66 11
11 N.A.
COMP 77 10
10 N.A.
N.A. 88 9 N.A.

AM13210v1

2.1 Pin description

Table 2. Pin description
No. Name Function

1 SOURCE Source connection of the internal power section.

Current sense input.
Connect this pin to the SOURCE pin (through an R1 resistor) to sense the current flowing in the
MOSFET through an RSENSE resistor connected to GND. The CS pin is also connected
through dedicated ROS, RPF resistors to the input and auxiliary voltage, in order to modulate
the input current flowing in the MOSFET according to the input voltage and therefore achieving
2 CS a high power factor. See Section 4.11: High power factor implementation on page 26 for more
details.
The resulting voltage is compared with the voltage on the ILED pin to determine MOSFET turn-
off. The pin is equipped with 250 ns blanking time after the gate drive output goes high for
improved noise immunity. If a second comparison level located at 1 V is exceeded, the IC is
stopped and restarted after VCC has dropped below 5 V.
Supply voltage of the device.
A capacitor, connected between this pin and ground, is initially charged by the internal high
voltage startup generator; when the device is running, the same generator keeps it charged in
3 VCC
case the voltage supplied by the auxiliary winding is not sufficient. This feature is disabled in
case a protection is tripped. A small bypass capacitor (100 nF typ.) to GND may be useful to
get a clean bias voltage for the signal part of the IC.

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 Pin description and connection diagrams HVLED815PF

Table 2. Pin description (continued)

No. Name Function

Ground.
Current return for both the signal part of the IC and the gate drive. All of the ground
4 GND
connections of the bias components should be tied to a trace going to this pin and kept
separate from any pulsed current return.
Constant current (CC) regulation loop reference voltage.
An external capacitor CLED is connected between this pin and GND. An internal circuit
5 ILED develops a voltage on this capacitor that is used as the reference for the MOSFET’s peak drain
current during CC regulation. The voltage is automatically adjusted to keep the average output
current constant.
Transformer demagnetization sensing for quasi-resonant operation and output voltage monitor.
A negative-going edge triggers the MOSFET turn-on, to achieve quasi-resonant operation
(zero voltage switching).
The pin voltage is also sampled-and-held right at the end of transformer demagnetization to get
6 DMG an accurate image of the output voltage to be fed to the inverting input of the internal,
transconductance-type, error amplifier, whose non-inverting input is referenced to 2.5 V. The
maximum IDMG sunk/sourced current must not exceed ± 2 mA (AMR) in all the VIN range
conditions.
No capacitor is allowed between the pin and the auxiliary transformer.
Output of the internal transconductance error amplifier. The compensation network is placed
7 COMP between this pin and GND to achieve stability and good dynamic performance of the voltage
control loop.
8 N. A. Not available. These pins must be connected to GND.
9 - 11 N. A. Not available. These pins must be left not connected.
12 N. C. Not internally connected. Provision for clearance on the PCB to meet safety requirements.
Drain connection of the internal power section.
13 - 16 DRAIN The internal high voltage startup generator sinks current from this pin as well. Pins connected
to the internal metal frame to facilitate heat dissipation.

2.2 Thermal data

Table 3. Thermal data
Symbol Parameter Max. value Unit

RthJP Thermal resistance, junction to pin 10 °C/W

RthJA Thermal resistance, junction to ambient 110 °C/W
PTOT Maximum power dissipation at TA = 50 °C 0.9 W
TSTG Storage temperature range -55 to 150 °C
TJ Junction temperature range -40 to 150 °C

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 HVLED815PF Electrical specifications

3 Electrical specifications

3.1 Absolute maximum ratings

Table 4. Absolute maximum ratings
Symbol Pin Parameter Value Unit

VDS 1, 13 - 16 Drain-to-source (ground) voltage -1 to 800 V

ID 1, 13 - 16 Drain current(1) 1 A
Single pulse avalanche energy
Eav 1, 13 - 16 50 mJ
(TJ = 25 °C, ID = 0.7 A)
VCC 3 Supply voltage (ICC < 25 mA) Self limiting V
IDMG 6 Zero current detector current ±2 mA
VCS 2 Current sense analog input -0.3 to 3.6 V
VCOMP 7 Analog input -0.3 to 3.6 V
1. Limited by maximum temperature allowed.

3.2 Electrical characteristics

Table 5. Electrical characteristics(1) (2)
Symbol Parameter Test condition Min. Typ. Max. Unit

Power section
V(BR)DSS Drain-source breakdown ID < 100 µA; TJ = 25 °C 800 V
VDS = 750 V; TJ = 125 °C(3)
IDSS OFF-state drain current 80 µA
See Figure 5
ID = 250 mA; TJ = 25 °C 6 7.4
RDS(on) Drain-source ON-state resistance 
ID = 250 mA; TJ = 125 °C(3) 14.8
Effective (energy related) output (3)
COSS See Figure 6
capacitance
High voltage startup generator
VSTART Min. drain start voltage ICHARGE < 100 µA 40 50 60 V
VDRAIN > VStart; VCC < VCCOn
4 5.5 7
ICHARGE VCC startup charge current TJ = 25 °C mA
VDRAIN > VStart; VCC<VCCOn +/- 10%
(4) 9.5 10.5 11.5 V
VCC restart voltage
VCC_RESTART
(VCC falling) After protection tripping 5
Supply voltage
VCC Operating range After turn-on 11.5 23
(4)
VCC_ON Turn-on threshold 12 13 14 V

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 Electrical specifications HVLED815PF

Table 5. Electrical characteristics(1) (2) (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit
(4)
VCC_OFF Turn-off threshold 9 10 11 V
VZ Internal Zener voltage ICC = 20 mA 23 25 27 V
Supply current
ICC_START-UP Startup current See Figure 7 200 300 µA
Iq Quiescent current See Figure 8 1 1.4 mA
Operating supply current
ICC See Figure 9 1.4 1.7 mA
at 50 kHz
Iq(fault) Fault quiescent current See Figure 10 250 350 µA
Startup timer
TSTART Start timer period 105 140 175 µs
Restart timer period during burst
TRESTART 420 500 700 µs
mode
Demagnetization detector
IDmgb Input bias current VDMG = 0.1 to 3 V 0.1 1 µA
VDMGH Upper clamp voltage IDMG = 1 mA 3.0 3.3 3.6 V
VDMGL Lower clamp voltage IDMG = - 1 mA -90 -60 -30 mV
VDMGA Arming voltage Positive-going edge 100 110 120 mV
VDMGT Triggering voltage Negative-going edge 50 60 70 mV

Trigger blanking time after VCOMP  1.3 V 6

TBLANK µs
MOSFET turn-off VCOMP = 0.9 V 30
Line feedforward
RFF Equivalent feedforward resistor IDMG = 1 mA 45 
Transconductance error amplifier
TJ = 25 °C 2.45 2.51 2.57
VREF Voltage reference (3) T V
J = -25 to 125 °C 2.4 2.6
and VCC = 12 V to 23 V
ICOMP = ± 10 µA
gm Transconductance 1.3 2.2 3.2 ms
VCOMP = 1.65 V
(5) Open
Gv Voltage gain loop 73 dB
GB Gain-bandwidth product (5)
500 KHz
Source current VDMG = 2.3 V, VCOMP = 1.65 V 70 100 µA
ICOMP
Sink current VDMG = 2.7 V, VCOMP = 1.65 V 400 750 µA
VCOMPH Upper COMP voltage VDMG = 2.3 V 2.7 V
VCOMPL Lower COMP voltage VDMG = 2.7 V 0.7 V
VCOMPBM Burst mode threshold 1 V
Hys Burst mode hysteresis 65 mV

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 HVLED815PF Electrical specifications

Table 5. Electrical characteristics(1) (2) (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Current reference
VILEDx Maximum value VCOMP = VCOMPL 1.5 1.6 1.7 V
(6)
VILED = 0.41 V, VDMG = 0 V;
VCLED Current reference voltage 207.76 212 216.24 mV
TJ = 25 °C
Current sense
tLEB (5)
Leading-edge blanking 330 ns
TD Delay-to-output (H-L) 90 200 ns
VCSx (4)
Max. clamp value dVcs/dt = 200 mV/µs 0.7 0.75 0.8 V
(4)
VCSdis Hiccup mode OCP level 0.92 1 1.08 V
1. VCC = 14 V (unless otherwise specified).
2. Limits are production tested at TJ = TA = 25 °C, and are guaranteed by statistical characterization in the range
TJ -25 to +125 °C.
3. Not production tested, guaranteed statistical characterization only.
4. Parameters tracking each other (in the same section).
5. Guaranteed by design.
6. Production tested only.

Figure 5. OFF-state drain and source current test circuit

14V Idss
A

VDD DRAIN

2.5V + CURRENT Vin

CONTROL 750V
DMG -

COMP ILED GND CS SOURCE

AM13211v1

Note: The measured IDSS is the sum between the current across the startup resistor and the
effective MOSFET’s OFF-state drain current.

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 Electrical specifications HVLED815PF

Figure 6. COSS output capacitance variation





&RVV>S)@









      
9GV>9@
$0Y

Figure 7. Startup current test circuit

Iccstart-up A 11.8 V

VDD DRAIN

2.5V + CURRENT
CONTROL
DMG -

COMP ILED GND CS SOURCE

AM13213v1

Figure 8. Quiescent current test circuit

Iq_meas A 14V

VDD DRAIN

2.5V + CURRENT
CONTROL
DMG -

33k COMP ILED GND CS SOURCE

3V 0.8V
10k 0.2V

AM13214v1

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 HVLED815PF Electrical specifications

Figure 9. Operating supply current test circuit

Icc 1.5K 2W
A 15V
27k

VDD DRAIN
220k
2.5V + CURRENT 150V
CONTROL
DMG -

10k 10k COMP ILED GND CS SOURCE

10
2.8V
5.6

50 kHz -5V

AM13215v1

Note: The circuit across the DMG pin is used for switch on synchronization.

Figure 10. Quiescent current during fault test circuit

Iq(fault) A 14V

VDD DRAIN

2.5V + CURRENT
CONTROL
DMG -

COMP ILED GND CS SOURCE

AM13216v1

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 Device description HVLED815PF

4 Device description

The HVLED815PF device is a high voltage primary switcher intended for operating directly
from the rectified mains with minimum external parts to provide high power factor (> 0.90)
and an efficient, compact and cost effective solution for LED driving. It combines a high-
performance low voltage PWM controller chip and an 800 V, avalanche rugged Power
MOSFET, in the same package.
The PWM is a current mode controller IC specifically designed for ZVS (“Zero Voltage
Switching”) flyback LED drivers, with constant output current (CC) regulation using primary
sensing feedback (PSR). This eliminates the need for the optocoupler, the secondary
voltage reference, as well as the current sense on the secondary side, while still maintaining
a good LED current accuracy. Moreover, it guarantees a safe operation when short-circuit of
one or more LEDs occurs.
The device can also provide a constant output voltage regulation (CV): it allows the
application to be able to work safely when the LED string opens due to a failure.
In addition, the device offers the shorted secondary rectifier (i.e. LED string shorted due to
a failure) or transformer saturation detection.
Quasi-resonant operation is achieved by means of a transformer demagnetization sensing
input that triggers MOSFET turn-on. This input serves also as both output voltage monitor,
to perform CV regulation, and input voltage monitor, to achieve mains-independent CC
regulation (line voltage feedforward).
The maximum switching frequency is top limited below 166 kHz, so that at medium-light
load a special function automatically lowers the operating frequency while still maintaining
the operation as close to ZVS as possible. At very light load, the device enters a controlled
burst mode operation that, along with the built-in high voltage startup circuit and the low
operating current of the device, helps minimize the residual input consumption.
Although an auxiliary winding is required in the transformer to correctly perform CV/CC
regulation, the chip is able to power itself directly from the rectified mains. This is useful
especially during CC regulation, where the flyback voltage generated by the winding drops.

4.1 Application information

The device is an off-line LED driver with all-primary sensing, based on quasi-resonant
flyback topology, with high power factor capability. In particular, using different application
schematic the device is able to provide a compact, efficient and cost-effective LED driver
solution with high power factor (PF > 0.9 - see application schematic in Figure 1 on page 4)
or with standard power factor (PF > 0.5/0.6 - see application schematic in Figure 2 on
page 5), based on the specific application requirements.
Referring to the application schematic in Figure 1, the IC modulates the input current
according to the input voltage providing the high power factor capability (PF > 0.9) keeping
a good line regulation. This application schematic is intended for a single range input
voltage.
For wide range application a different reference schematic can be used; refer to AN4346
application note for further details.

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 HVLED815PF Device description

Moreover, the device is able to work in different modes depending on the LED's driver load
condition (see Figure 11):
1. QR mode at heavy load. Quasi-resonant operation lies in synchronizing MOSFET's
turn-on to the transformer's demagnetization by detecting the resulting negative-going
edge of the voltage across any winding of the transformer. Then the system works
close to the boundary between discontinuous (DCM) and continuous conduction
(CCM) of the transformer. As a result, the switching frequency is different for different
line/load conditions (see the hyperbolic-like portion of the curves in Figure 11).
Minimum turn-on losses, low EMI emission and safe behavior in short-circuit are the
main benefits of this kind of operation.
2. Valley-skipping mode at medium/ light load. Depending on voltage on COMP pin, the
device defines the maximum operating frequency of the converter. As the load is
reduced, MOSFET's turn-on does not occur any more on the first valley but on the
second one, the third one and so on. In this way the switching frequency is no longer
increased (piecewise linear portion in Figure 11).
3. Burst mode with no or very light load. When the load is extremely light or disconnected,
the converter enters a controlled on/off operation with constant peak current.
Decreasing the load result in frequency reduction, which can go down even to few
hundred hertz, thus minimizing all frequency-related losses and making it easier to
comply with energy saving regulations or recommendations. Being the peak current
very low, no issue of audible noise arises.

Figure 11. Multi-mode operation of HVLED815PF (constant voltage operation)

f osc

Input voltage

f sw Valley-skipping
mode

Burst-mode

Quasi-resonant mode

0
Pinmax
Pin
AM13561v1

4.2 Power section and gate driver

The power section guarantees safe avalanche operation within the specified energy rating
as well as high dv/dt capability. The Power MOSFET has a VDSS of 800 V min. and a typical
RDS(on) of 6 .
The internal gate driver of the Power MOSFET is designed to supply a controlled gate
current during both turn-on and turn-off in order to minimize common mode EMI. Under
UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the
Power MOSFET cannot be turned on accidentally.

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4.3 High voltage startup generator

Figure 12 shows the internal schematic of the high voltage start-up generator (HV
generator). It includes an 800 V-rated N-channel MOSFET, whose gate is biased through
the series of a 12 M resistor and a 14 V Zener diode, with a controlled, temperature
compensated current generator connected to its source.
The HV generator input is in common with the DRAIN pins, while its output is the supply pin
of the device (VCC pin). A mains “UVLO” circuit (separated from the UVLO of the device
that sense VCC) keeps the HV generator off if the drain voltage is below VSTART (50 V
typical value).

Figure 12. High voltage start-up generator: internal schematic

DRAIN

14V 12M

Mains UVLO
Vcc_OK

HV_EN IHV

VCC
CONTROL

Icharge

GND
AM13562v1

With reference to the timing diagram of Figure 13, when power is applied to the circuit and
the voltage on the input bulk capacitor is high enough, the HV generator is sufficiently
biased to start operating, thus it will draw about 5.5 mA (typical) to the VCC capacitor.
Most of this current will charge the bypass capacitor connected between the VCC pin and
ground and make its voltage rise linearly. As soon as the VCC pin voltage reaches the
VCC_ON turn on threshold (13 V typ.) the chip starts operating, the internal Power MOSFET
is enabled to switch and the HV generator is cut off by the Vcc_OK signal asserted high.
The IC is powered by the energy stored in the VCC capacitor.
The chip is able to power itself directly from the rectified mains: when the voltage on the
VCC pin falls below VCC_RESTART (10.5 V typ.), during each MOSFET's off-time the HV
current generator is turned on and charges the supply capacitor until it reaches the VCC_ON
threshold.
In this way, the self-supply circuit develops a voltage high enough to sustain the operation of
the device. This feature is useful especially during constant current (CC) regulation, when
the flyback voltage generated by the auxiliary winding alone may not be able to keep VCC
pin above VCC_RESTART.

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Figure 13. Timing diagram: normal power-up and power-down sequences

VIN

VStart

t
VCC
VccON

Vccrestart

t
DRAIN

t
ICHARGE
5.5 mA

Normal operation Normal operation t

Power-on Power-off
CV mode CC mode

AM13563v1

4.4 Secondary side demagnetization detection and triggering

block
The demagnetization detection (DMG) and triggering blocks switch on the Power MOSFET
if a negative-going edge falling below 50 mV is applied to the DMG pin. To do so, the
triggering block must be previously armed by a positive-going edge exceeding 100 mV.
This feature is used to detect transformer demagnetization for QR operation, where the
signal for the DMG input is obtained from the transformer's auxiliary winding used also to
supply the IC.

Figure 14. DMG block, triggering block

Rdmg DMG DMG BLANKING

CLAMP TIME

Rf b STARTER
Aux

- TURN-ON
LOGIC S
+
110mV Q To Driv er
60mV
From CC/CV Block LEB R

From OCP

AM13564v1

The triggering block is blanked after MOSFET's turn-off to prevent any negative-going edge
that follows leakage inductance demagnetization from triggering the DMG circuit

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erroneously. This TBLANK blanking time is dependent on the voltage on COMP pin: it is
TBLANK = 30 µs for VCOMP = 0.9 V, and decreases almost linearly down to TBLANK = 6 µs for
VCOMP = 1.3 V.
The voltage on the pin is both top and bottom limited by a double clamp, as illustrated in the
internal diagram of the DMG block of Figure 14. The upper clamp is typically located
at 3.3 V, while the lower clamp is located at -60 mV. The interface between the pin and the
auxiliary winding will be a resistor divider. Its resistance ratio as well as the individual
resistance values will be properly chosen (see Section 4.6, Section 4.7 on page 22 and
Section 4.11 on page 26).
Please note that the maximum IDMG sunk/sourced current has to not exceed ±2 mA (AMR)
in all the VIN range conditions. No capacitor is allowed between DMG pin and the auxiliary
transformer.
The switching frequency is top limited below 166 kHz, as the converter's operating
frequency tends to increase excessively at light load and high input voltage.
A starter block is also used to start up the system, that is, to turn on the MOSFET during
converter power-up, when no or a too small signal is available on the DMG pin. The starter
frequency is 2 kHz if COMP pin is below burst mode threshold, i.e. 1 V, while it becomes
8 kHz if this voltage exceeds this value.
After the first few cycles initiated by the starter, as the voltage developed across the auxiliary
winding becomes large enough to arm the DMG circuit, MOSFET's turn-on will start to be
locked to transformer demagnetization, hence setting up QR operation. The starter is
activated also when the IC is in “Constant Current” regulation and the output voltage is not
high enough to allow the DMG triggering.
If the demagnetization completes - hence a negative-going edge appears on the DMG pin -
after a time exceeding time TBLANK from the previous turn-on, the MOSFET will be turned
on again, with some delay to ensure minimum voltage at turn-on. If, instead, the negative-
going edge appears before TBLANK has elapsed, it will be ignored and only the first
negative-going edge after TBLANK will turn-on the MOSFET. In this way one or more drain
ringing cycles will be skipped (““valley-skipping mode”, Figure 15) and the switching
frequency will be prevented from exceeding 1/TBLANK.

Figure 15. Drain ringing cycle skipping as the load is progressively reduced
VDS VDS VDS

t t t
TON TFW TW

TOSC TOSC TOSC

Pin = Pin' Pin = Pin'' < Pin' Pin = Pin''' < Pin''
(limit condition)
AM13565v1

Note: That when the system operates in valley skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET
is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Thus one or more longer switching
cycles will be compensated by one or more shorter cycles and vice versa. However, this
mechanism is absolutely normal and there is no appreciable effect on the performance of
the converter or on its output voltage.

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4.5 Constant current operation

Figure 16 presents the principle used for controlling the average output current of the
flyback converter.
The voltage of the auxiliary winding is used by the demagnetization block to generate the
control signal for the internal MOSFET switch Q. A resistor R in series with it absorbs
a current equal to VILED/R, where VILED is the voltage developed across the capacitor CLED
capacitor.
The flip-flop's output is high as long as the transformer delivers current on secondary side.
This is shown in Figure 17.

Figure 16. Current control principle

Iref

VILED - To PWM Logic

+ CC

R From CS pin

Q
S
Q
Rdmg DMG DEMAG R
LOGIC

Icled
Rf b
Aux ILED

CLED

AM13566v1

Figure 17. Constant current operation: switching cycle waveforms

IPRIM

t
ISEC

TONSEC
Q

ICLED
IREF

t
VILED/R

T
AM13567v1

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The capacitor CLED has to be chosen so that its voltage VILED can be considered as
a constant. Since it is charged and discharged by currents in the range of some ten µA
(IREF = 20 µA typ.) at the switching frequency rate, a capacitance value in the range
4.7 - 10 nF is suited for switching frequencies in the ten kHz. When high power factor
schematic is implemented, a higher capacitor value should be used (i.e. 1 µF - 10 µF).
The average output current IOUT can be expressed as:

Equation 1

Where ISEC is the secondary peak current, TONSEC is the conduction time of the secondary
side and T is the switching period.
Taking into account the transformer ratio N between primary and secondary side, ISEC can
also be expressed as a function of the primary peak current IPRIM:

Equation 2

As in steady state the average current ICLED:

Equation 3

Which can be solved for VILED:

Equation 4

where VCLED = R * IREF and it is internally defined (0.2 V typical - see Table 5: Electrical
characteristics on page 9).
The VILED pin voltage is internally compared with the CS pin voltage (constant current
comparator):

Equation 5

Combining (1), (2), (4), and (5) the average output current results:

Equation 6

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Equation 6 shows that the average output current IOUT does not depend anymore on the
input voltage VIN or the output voltage VOUT, neither on transformer inductance values. The
external parameters defining the output current are the transformer ratio n and the sense
resistor RSENSE.
Equation 6 is valid for both standard and high power factor implementation.

4.6 Constant voltage operation

The IC is specifically designed to work in primary regulation and the output voltage is
sensed through a voltage partition of the auxiliary winding, just before the auxiliary rectifier
diode.
Figure 18 shows the internal schematic of the constant voltage mode and the external
connections.
Due to the parasitic wires resistance, the auxiliary voltage is representative of the output just
when the secondary current becomes zero. For this purpose, the signal on DMG pin is
sampled-and-held at the end of transformer's demagnetization to get an accurate image of
the output voltage and it is compared with the error amplifier internal reference voltage VREF
(2.51 V typ. - see Table 5: Electrical characteristics on page 9).
During the MOSFET's OFF-time the leakage inductance resonates with the drain
capacitance and a damped oscillation is superimposed on the reflected voltage. The S/H
logic is able to discriminate such oscillations from the real transformer's demagnetization.
When the DMG logic detects the transformer's demagnetization, the sampling process
stops, the information is frozen and compared with the error amplifier internal reference.
The internal error amplifier is a transconductance type and delivers an output current
proportional to the voltage unbalance of the two outputs: the output generates the control
voltage that is compared with the voltage across the sense resistor, thus modulating the
cycle-by-cycle peak drain current.
The COMP pin is used for the frequency compensation: usually, an RC network, which
stabilizes the overall voltage control loop, is connected between this pin and ground.
As a result, the output voltage VOUT at zero-load (i.e. no LED on the LED driver output) can
be selected trough the RFB resistor in according to Equation 7:

Equation 7

Where NAUX and NSEC are the auxiliary and secondary turn's number respectively.
The RDMG resistor value can be defined depending on the application parameters
(see Section 4.7: Voltage feedforward block).

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Figure 18. Voltage control principle: internal schematic

Rdmg DMG -
S/H - To PWM Logic
+ EA
+ CV
Rf b 2.5V
Aux DEMAG
LOGIC
From CS pin

COMP
R

AM13568v1

4.7 Voltage feedforward block

The current control structure uses the VCLED voltage to define the output current, according
to Equation 6 in Section 4.5. Actually, the constant current comparator will be affected by an
internal propagation delay TD, which will switch off the MOSFET with a peak current than
higher the foreseen value.
This current overshoot will be equal to:

Equation 8

The previous terms introduce a small error on the calculated average output current set-
point, depending on the input voltage.
The HVLED815PF device implements a line feedforward function, which solves the issue by
introducing an input voltage dependent offset on the current sense signal, in order to adjust
the cycle-by-cycle current limitation.
The internal schematic is shown in Figure 19.

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Figure 19. Feedforward compensation: internal schematic

DRAIN

Rdmg DMG Feedforward .

Logic

Rfb CC -
Aux IFF Block PWM
+ CC LOGIC

Rff

CS SOURCE

Rsense

AM13569v1

During MOSFET's ON-time the current sourced from DMG pin is mirrored inside the
“Feedforward Logic” block in order to provide a feedforward current, IFF.
Such “feedforward current” is proportional to the input voltage according to Equation 9:

Equation 9

Where m is the primary-to-auxiliary turns ratio.

According to the schematic in Figure 19, the voltage on the non-inverting comparator will be:

Equation 10

The offset introduced by feedforward compensation will be:

Equation 11

As RFF >> RSENSE, the previous one can be simplified as:

Equation 12

This offset is proportional to VIN and it is used to compensate the current overshoot,
according to Equation 13:

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Equation 13

Finally, the RDMG resistor can be calculated as follows:

Equation 14

In this case the peak drain current does not depend on input voltage anymore, and as
a consequence the average output current IOUT does not depend from the VIN input voltage.
When high power factor is implemented (see Section 4.11), the feedforward current has to
be minimized because the line regulation is assured by the external offset circuitry (see
Figure 1: Application circuit for high power factor LED driver - single range input on page 4).
The maximum value is limited by the minimum IDMG internal current needed to guarantee
the correct functionality of the internal circuitry:

Equation 15

4.8 Burst mode operation at no load or very light load

When the voltage at the COMP pin falls 65 mV is below the internally fixed threshold
VCOMPBM, the IC is disabled with the MOSFET kept in OFF state and its consumption
reduced at a lower value to minimize VCC capacitor discharge.
In this condition the converter operates in burst mode (one pulse train every
TSTART = 500 µs), with minimum energy transfer.
As a result of the energy delivery stop, the output voltage decreases: after 500 µs the
controller switches on the MOSFET again and the sampled voltage on the DMG pin is
compared with the internal reference VREF. If the voltage on the EA output, as a result of the
comparison, exceeds the VCOMPL threshold, the device restarts switching, otherwise it stays
OFF for another 500 µs period.
In this way the converter will work in burst mode with a nearly constant peak current defined
by the internal disable level. A load decrease will then cause a frequency reduction, which
can go down even to few hundred hertz, thus minimizing all frequency-related losses and
making it easier to comply with energy saving regulations. This kind of operation, shown in
the timing diagrams of Figure 20 along with the others previously described, is noise-free
since the peak current is low.

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Figure 20. Load-dependent operating modes: timing diagrams

COMP

50 mV hysteresis (Hys)
VCOMPL

IDS
t

Normal-mode Burst-mode Normal-mode

t

AM13570v1

4.9 Soft-start and starter block

The soft-start feature is automatically implemented by the constant current block, as the
primary peak current will be limited from the voltage on the CLED capacitor.
During the startup, as the output voltage is zero, the IC will start in constant current (CC)
mode with no high peak current operations. In this way the voltage on the output capacitor
will increase slowly and the soft-start feature will be ensured.
Actually the CLED value is not important to define the soft-start time, as its duration depends
on others circuit parameters, like transformer ratio, sense resistor, output capacitors and
load. The user will define the best appropriate value by experiments.

4.10 Hiccup mode OCP

The device is also protected against short-circuit of the secondary rectifier, short-circuit on
the secondary winding or a hard-saturated flyback transformer. An internal comparator
monitors continuously the voltage on CS pin and activates a protection circuitry if this
voltage exceeds an internally fixed threshold VCSdis (1 V typ. - see Table 5: Electrical
characteristics on page 9).
To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the
first time the comparator is tripped, the protection circuit enters a “warning state”. If in the
subsequent switching cycle the comparator is not tripped, a temporary disturbance is
assumed and the protection logic will be reset in its idle state; if the comparator will be
tripped again a real malfunction is assumed and the device will be stopped.
This condition is latched as long as the device is supplied. While it is disabled, however, no
energy is coming from the self-supply circuit; hence the voltage on the VCC capacitor will
decay and cross the UVLO threshold after some time, which clears the latch. The internal
start-up generator is still off, then the VCC voltage still needs to go below its restart voltage
before the VCC capacitor is charged again and the device restarted.

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Ultimately, this will result in a low-frequency intermittent operation (hiccup mode operation),
with very low stress on the power circuit. This special condition is illustrated in the timing
diagram of Figure 21.

Figure 21. Hiccup mode OCP: timing diagram

VCC
Secondary diode is shorted here

VccON

VccOFF

Vccrest

VCS t
1V
Vcsdis

VDS t
Two switching cycles

t
AM13571v1

4.11 High power factor implementation

Referring to the principle application schematic in Figure 1 on page 4, two contributions are
added on the CS pin in order to implement the high power factor capability (trough RPF
resistor) and keeping a good line regulation (trough ROS resistor). The application
schematic on Figure 1 is intended for a single range input voltage. For wide range
application a different reference schematic can be used; refer to AN4346 application note
for further details.
Through the RPF resistor a contribution proportional to the input voltage is added on the CS
pin: as a consequence the input current is proportional to the input voltage during the line
period, implementing a high power factor correction. The contribution proportional to the
input voltage is generated using the auxiliary winding, as a consequence a diode in series to
the RPF resistor is needed.
Through the ROS resistor a positive contribution proportional to the average value of the
input voltage is added on the CS pin in order to keep a good line regulation.
The voltage contribution proportional to the average value of the input voltage is generated
trough the low pass filter RA/RB resistor and COS capacitor. A diode in series to the RA/RB
resistor is suggested to avoid the discharge of COS capacitor in any condition.
The R1 resistor between CS and SOURCE pin is needed to add on the CS pin also the
contribution proportional the output current trough the RSENSE resistor.

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Figure 22. High power factor implementation connection - single range input

DRAIN

Rdmg DMG Feedf orward .

Logic1

Rf b CC -
Aux IFF Block1 PWM
+ CC LOGIC2

Rf f

CS SOURCE
RPF R1

ROS Rsense

VIN (after bridge diode) RA RB

COS

AM13572v1

The components selection flow starts from the RDMG resistor: this resistor has to be
selected in order to minimize the internal feedforward effect.
The maximum selectable value is limited by the minimum internal current circuitry IDMG
needed to guarantee the correct functionality of the internal circuitry:

Equation 16

where NAUX and NPRIM are the auxiliary and primary turn's number respectively and VIN_MIN
is the minimum rms input voltage of the application (i.e. 88 V for 110 Vac or 175 V for 230
Vac range).
The RFB resistor defines the VOUT output voltage value in the open circuit condition (no-load
condition, i.e. no LED on the output of LED driver) and it can be selected using the following
relationship:

Equation 17

where NAUX and NSEC are the auxiliary and secondary turn's number respectively and VREF
is the internal reference voltage (VREF = 2.51 V typ - see Table 5: Electrical characteristics
on page 9).
The R1 resistor is typically selected in the range of 500 - 1.5 k in order to minimize the
internal feedforward effect and to minimize the power dissipation on the RA/RB resistor
offset circuitry.

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The RA, RB, ROS resistors are selected to add a positive offset on CS pin in order to keep
a good line regulation over the input voltage range and cab be selected using Equation 18:

Equation 18

Where VOS_TYP is the desired voltage across COS capacitor applying the VIN_TYP typical
input voltage (i.e. VIN_TYP = 220 V for 176/264 Vac input range); FSW is the switching
frequency and can be estimated using Equation 19, where fT and fR are the transition and
resonant frequency respectively:

Equation 19

Equation 20

Equation 21

where CD is the total equivalent capacitor afferent at the drain node.

Based on the desired voltage across the COS capacitor and calculated ROS resistor, then
the sum of RA and RB can then calculated as a results of partitioning divider:

Equation 22

Using the previous ROS resistor value the RPF resistor can be estimated using Equation 23:

Equation 23

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 HVLED815PF Device description

Finally the current sense resistor RSENSE can be estimated in order to select the
desiderated average output current value:

Equation 24

where VCLED is internally defined (0.2 V typical - see Table 5: Electrical characteristics on
page 9).

System design tips

Starting from the previous estimated components value, further fine-tuning on the real LED
driver board could be necessary and it can be easily done considering that:
– Decreasing/increasing the RPF resistor value, the power factor effect
increases/decreases.
– Decreasing/increasing the ROS resistor value, the line regulation effect
increases/decreases.
– Decreasing/increasing the ROS resistor value, the RA + RB resistors value should
be increased/decreased to keep the desiderated voltage across the COS capacitor
(Equation 22).
– Decreasing/increasing the RSENSE resistor value the average output current
increases/decreases (Equation 24).

4.12 Layout recommendations

A proper printed circuit board layout is essential for correct operation of any switch-mode
converter and this is true for the HVLED815PF device as well. Careful component placing,
correct traces routing, appropriate traces widths and compliance with isolation distances are
the major issues.
In particular:
 Current sense resistor (RSENSE) should be connected as close as possible to the
SOURCE pin, maintaining the trace for the GND as short as possible.
 Resistor connected on CS pin (ROS, RPF, R1) should be connected as close as
possible to the pin.
 Compensation network (RCOMP, CCOMP) should be connected as close as possible to
the COMP pin, maintaining the trace for the GND as short as possible.
 Signal ground should be routed separately from power ground, as well from the sense
resistor trace.
 DMG partition resistors (RDMG, RFB) should be connected as close as possible to the
DMG pin, minimizing the equivalent parasitic capacitor on DMG pin.

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 Device description HVLED815PF

Figure 23. Suggested routing for the LED driver

AC

AC

VCC DRAIN

RDMG

DMG

COMP ILED GND SOURCE CS

RFB RPF ROS

RCOMP R1

CLED
CCOMP
RSENSE

AM13573v1

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 HVLED815PF Package information

5 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

Figure 24. SO16N package outline

0016020_F

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Table 6. SO16N package mechanical data

Dimensions (mm)
Symbol
Min. Typ. Max.

A 1.75
A1 0.10 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.80 9.90 10.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27
h 0.25 0.50
L 0.40 1.27
k 0 8°
ccc 0.10

Figure 25. SO16N recommended footprint (dimensions are in mm)

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 HVLED815PF Revision history

6 Revision history
22-Oct

Table 7. Document revision history

Date Revision Changes

26-Jul-2012 1 Initial release.

29-Aug-2012 2 Added Table 2: Pin description on page 7.
Modified TJ value on Table 3: Thermal data.
23-Oct-2012 3 Updated TJ value in note 2 (below Table 5: Electrical characteristics).
Minor text changes.
Added sections from 4.1 to 4.12.
Modified Figure 1: Application circuit for high power factor LED driver
31-Jan-2013 4
- single range input and Figure 2: Application circuit for standard LED
driver.
Updated Section : Features on page 1 (replaced ± 5% by ± 3% in
accuracy on constant LED output current).
Updated Table 5: Electrical characteristics (updated Test condition,
Values and Units of VCLED symbol, added note 6. below Table 5).
18-Feb-2014 5
Updated Section 5: Package information (reversed order of
Figure 24: SO16N package outline and Table 6: SO16N package
mechanical data, updated titles of Figure 24 and Table 6).
Minor modifications throughout document.

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 HVLED815PF

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