TMS320 SECOND-GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

• 80-ns Instruction Cycle Time 68-Pin GB Package†

(Top View)
• 544 Words of On-Chip Data RAM 1 2 3 4 5 6 7 8 9 10 11

• 4K Words of On-Chip Secure Program A

EPROM (TMS320E25) B
• 4K Words of On-Chip Program ROM C
(TMS320C25) D

• 128K Words of Data/Program Space

E
F
• 32-Bit ALU/Accumulator G
• 16 × 16-Bit Multiplier With a 32-Bit Product H

•
J
Block Moves for Data/Program
K
Management
L
• Repeat Instructions for Efficient Use of
Program Space

ADVANCE INFORMATION
• Serial Port for Direct Codec Interface 68-Pin FN and FZ Packages†
(Top View)
• Synchronization Input for Synchronous

READY

CLKR
CLKX
Multiprocessor Configurations

V CC
V CC
D10

D12
D13
D14
D15
D11
D8
D9
• Wait States for Communication to Slow 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
Off-Chip Memories/Peripherals VSS 10 60 IACK
D7 11 59 MSC
• On-Chip Timer for Control Operations D6
D5
12
13
58
57
CLKOUT1
CLKOUT2
• Single 5-V Supply D4
D3
14
15
56
55
XF
HOLDA
• Packaging: 68-Pin PGA, PLCC, and
D2
D1
16
17
54
53
DX
FSX
CER-QUAD D0 18 52 X2 CLKIN
SYNC 19 51 X1
• 68-to-28 Pin Conversion Adapter Socket for INT0
INT1
20 50 BR
21 49 STRB
EPROM Programming INT2 22 48 R/W

• Commercial and Military Versions Available

VCC
DR
23
24
47
46
PS
IS

•
FSR 25 45 DS
NMOS Technology: A0 26 44 VSS
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
— TMS32020 . . . . . . . . . 200-ns cycle time
A10

A12
A13
A14
A15
A1
A2
A3
A4
A5
A6
A7

A8
A9

A11
V SS

V CC

• CMOS Technology:
— TMS320C25 . . . . . . . . 100-ns cycle time
— TMS320E25 . . . . . . . . 100-ns cycle time
— TMS320C25-50 . . . . . . 80-ns cycle time

description
This data sheet provides complete design documentation for the second-generation devices of the TMS320
family. This facilitates the selection of the devices best suited for user applications by providing all specifications
and special features for each TMS320 member. This data sheet is divided into four major sections: architecture,
electrical specifications (NMOS and CMOS), timing diagrams, and mechanical data. In each of these sections,
generic information is presented first, followed by specific device information. An index is provided for quick
reference to specific information about a device.

ADVANCE INFORMATION concerns new products in the Copyright  1991, Texas Instruments Incorporated
sampling or preproduction phase of development.
Characteristic data and other specifications are subject to
change without notice.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 1

TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS

FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN
A0 K1/26 A12 K8/40 D2 E1/16 D14 A5/3 INT2 H1/22 VCC H2/23
A1 K2/28 A13 L9/41 D3 D2/15 D15 B6/2 IS J11/46 VCC L6/35
A2 L3/29 A14 K9/42 D4 D1/14 DR J1/24 MP/MC† A6/1 VSS B1/10
A3 K3/30 A15 L10/43 D5 C2/13 DS K10/45 MSC C10/59 VSS K11/44
A4 L4/31 BIO B7/68 D6 C1/12 DX E11/54 PS J10/47 VSS L2/27
A5 K4/32 BR G11/50 D7 B2/11 FSR J2/25 READY B8/66 XF D11/56
A6 L5/33 CLKOUT1 C11/58 D8 A2/9 FSX F10/53 RS A8/65 X1 G10/51
A7 K5/34 CLKOUT2 D10/57 D9 B3/8 HOLD A7/67 R/W H11/48 X2/CLKIN F11/52
A8 K6/36 CLKR B9/64 D10 A3/7 HOLDA E10/55 STRB H10/49
A9 L7/37 CLKX A9/63 D11 B4/6 IACK B11/60 SYNC F2/19
A10 K7/38 D0 F1/18 D12 A4/5 INT0 G1/20 VCC A10/61
A11 L8/39 D1 E2/17 D13 B5/4 INT1 G2/21 VCC B10/62
† On the TMS32020, MP/MC must be connected to VCC.

SIGNALS I/O/Z‡ DEFINITION

VCC I 5-V supply pins
VSS I Ground pins
X1 O Output from internal oscillator for crystal
X2/CLKIN I Input to internal oscillator from crystal or external clock
CLKOUT1 O Master clock output (crystal or CLKIN frequency/4)
CLKOUT2 O A second clock output signal
D15-D0 I/O/Z 16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/O spaces.
A15-A0 O/Z 16-bit address bus A15 (MSB) through A0 (LSB)
PS, DS, IS O/Z Program, data, and I/O space select signals
R/W O/Z Read/write signal
STRB O/Z Strobe signal
RS I Reset input
INT2-INT0 I External user interrupt inputs
MP/MC I Microprocessor/microcomputer mode select pin
MSC O Microstate complete signal
IACK O Interrupt acknowledge signal
READY I Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction
is complete.
BR O Bus request signal. Asserted when the TMS320C2x requires access to an external global data memory space.
XF O External flag output (latched software-programmable signal)
HOLD I Hold input. When asserted, TMS320C2x goes into an idle mode and places the data, address, and control lines in
the high impedance state.
HOLDA O Hold acknowledge signal
SYNC I Synchronization input
BIO I Branch control input. Polled by BIOZ instruction.
DR I Serial data receive input
CLKR I Clock for receive input for serial port
FSR I Frame synchronization pulse for receive input
DX O/Z Serial data transmit output
CLKX I Clock for transmit output for serial port
FSX I/O/Z Frame synchronization pulse for transmit. Configuration as either an input or an output.
‡ I/O/Z denotes input/output/high-impedance state.

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 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

description
The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speed
controller with the numerical capability of an array processor, thereby offering an inexpensive alternative to
multichip bit-slice processors. The highly paralleled architecture and efficient instruction set provide speed and
flexibility to produce a MOS microprocessor family that is capable of executing more than 12.5 MIPS (million
instructions per section). The TMS320 family optimizes speed by implementing functions in hardware that other
processors implement through microcode or software. This hardware-intensive approach provides the design
engineer with processing power previously unavailable on a single chip.
The TMS320 family consists of three generations of digital signal processors. The first generation contains the
TMS32010 and its spinoffs. The second generation includes the TMS32020, TMS320C25, and TMS320E25,
which are described in this data sheet. The TMS320C30 is a floating-point DSP device designed for even higher
performance. Many features are common among the TMS320 processors. Specific features are added in each
processor to provide different cost/performance tradeoffs. Software compatibility is maintained throughout the
family to protect the user’s investment in architecture. Each processor has software and hardware tools to
facilitate rapid design.

introduction
The TMS32010, the first NMOS digital signal processor in the TMS320 family, was introduced in 1983. Its
powerful instruction set, inherent flexibility, high-speed number-crunching capabilities, and innovative
architecture have made this high-performance, cost-effective processor the ideal solution to many
telecommunications, computer, commercial, industrial, and military applications. Since that time, the
TMS320C10, a low-power CMOS version of the industry-standard TMS32010, and other spinoff devices have
been added to the first generation of the TMS320 family.
The second generation of the TMS320 family (referred to as TMS320C2x) includes four members, the
TMS32020, TMS320C25, TMS320C25-50, and TMS320E25. The architecture of these devices is based upon
that of the TMS32010.
The TMS32020, processed in NMOS technology, is source-code compatible with he TMS32010 and in many
applications is capable of two times the throughput of the first-generation devices. Its enhanced instruction set
(109 instructions), large on-chip data memory (544 words), large memory spaces, on-chip serial port, and
hardware timer make the TMS32020 a powerful addition to the TMS320 family.
The TMS320C25 is the second member of the TMS320 second generation. It is processed in CMOS technology,
is capable of an instruction cycle time of 100 ns, and is pin-for-pin and object-code compatible with the
TMS32020. The TMS320C25’s enhanced feature set greatly increases the functionality of the device over the
TMS32020. Enhancements included 24 additional instructions (133 total), eight auxiliary registers, an
eight-level hardware stack, 4K words of on-chip program ROM, a bit-reversed indexed-addressing mode, and
the low-power dissipation inherent to the CMOS process. An extended-temperature range version
(TMS320C25GBA) is also available.
The TMS320C25-50 is a high-speed version of the TMS320C25. It is capable of an instruction cycle time of less
than 80 ns. It is architecturally identical to the original 40-MHz version of the TMS320C25 and, thus, is pin-for-pin
and object-code compatible with the TMS320C25.
The TMS320E25 is identical to the TMS320C25, with the exception that the on-chip 4K-word program ROM is
replaced with a 4K-word on-chip program EPROM. On-chip EPROM allows realtime code development and
modification for immediate evaluation of system performance.

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TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

Key Features: TMS32020 +5 V GND

• 200-ns Instruction Cycle Time

• 544 Words of On-Chip Data RAM
• 128K Words of Total Data/Program Interrupts 256-Word
Data/Prog
288-Word
Data Data (16)
Memory Space RAM RAM Multi-
• Wait States for Communication to Slower Off-Chip Processor
Memories Multiplier
Interface
• Source Code Compatible With the TMS320C1x 32-BIT ALU/ACC Serial
• Single-Cycle Multiply/Accumulate Instructions Interface

•
Shifters
Repeat Instructions Address (16)
• Global Data Memory Interface Timer

• Block Moves for Data/Program Management

• Five Auxiliary Registers With Dedicated
• On-Chip Clock Generator
Arithmetic Unit
• Serial Port for Multiprocessing or Interfacing • Single 5-V Supply
to Codecs, Serial Analog-to-Digital • NMOS Technology
Converters, etc.
• 68-Pin Grid Array (PGA) Package
Key Features: TMS320C25, TMS320C25-50, TMS320E25
• 80-ns Instruction Cycle Time (TMS320C25-50) +5 V GND

• 100-ns Instruction Cycle Time (TMS320C25)

• 4K Words of On-Chip Secure Program EPROM
(TMS320E25) Interrupts 256-Word 288-Word Data (16)
• 4K Words of On-Chip Program
Data/Prog
RAM
Data
RAM
ROM (TMS320C25)
• 544 Words of On-Chip RAM
MP/MC 4K-Words
ROM/EPROM
Multi-
Processor
• 128K Words of Total Program/Data
Multiplier
Interface
Memory Space
• Wait States for Communications to 32-Bit ALU/ACC
Serial
Interface
Slower Off-Chip Memories
• Object-Code Compatible With the TMS32020
Shifters
Address (16)
• Source-Code Compatible With TMS320C1x Timer

• 24 Additional Instructions to Support

Adaptive Filtering, FFTs, and
Extended-Precision Arithmetic • On-Chip Clock Generator
• Block Moves for Data/Program Management • Single 5-V Supply
• Single-Cycle Multiply/Accumulate Instructions • Internal Security Mechanism (TMS320E25)
• Eight Auxiliary Registers With Dedicated • 68-to-28 Pin Conversion Adapter Socket
Arithmetic Unit
• CMOS Technology
• Bit-Reversed Indexed-Addressing Mode for
• 68-Pin Grid Array (PGA) Package
Radix-2 FFTS
(TMS320C25)
• Double-Buffered Serial Port
• 68-Lead Plastic Leaded Chip Carrier (PLCC)
Package (TMS320C25, TMS320C25-50)
• 68-Lead CER-QUAD Package (TMS320E25)

4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

Table 1 provides an overview of the second-generation TMS320 processors with comparisons of memory, I/O,
cycle timing, power, package type, technology, and military support. For specific availability, contact the nearest
TI Field Sales Office.

Table 1. TMS320 Second-Generation Device Overview

MEMORY PACKAGE
I/O† CYCLE TYP
TYPE
DEVICE ON-CHIP OFF-CHIP TIMER TIME POWER
RAM ROM/EPROM PROG DATA SER (ns) (mW)
PAR DMA PGA PLCC CER-QUAD
TMS32020‡ (NMOS) 544 — 64K 64K YES 16 × 16 YES YES 200 1250 68 — —
TMS320C25‡ (CMOS) 544 4K 64K 64K YES 16 × 16 CON YES 100 500 68 68 —
TMS320C25-50§ (CMOS) 544 4K 64K 64K YES 16 × 16 CON YES 80 500 — 68 —
TMS320E25§ (CMOS) 544 4K 64K 64K YES 16 × 16 CON YES 100 500 — — 68
† SER = serial; PAR = parallel; DMA = direct memory access; CON = concurrent DMA.
‡ Military version available; contact nearest TI Field Sales Office for availability.
§ Military version planned; contact nearest TI Field Sales Office for details.

architecture
The TMS320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard
architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch
and execution. The TMS320 family’s modification of the Harvard architecture allows transfers between program
and data spaces, thereby increasing the flexibility of the device. This modification permits coefficients stored
in program memory to be read into the RAM, eliminating the need for a separate coefficient ROM. It also makes
available immediate instructions and subroutines based on computed values.
Increased throughput on the TMS320C2x devices for many DSP applications is accomplished by means of
single-cycle multiply/accumulate instructions with a data move option, up to eight auxiliary registers with a
dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing.
The architectural design of the TMS320C2x emphasizes overall speed, communication, and flexibility in
processor configuration. Control signals and instructions provide floating-point support, block-memory
transfers, communication to slower off-chip devices, and multiprocessing implementations.
32-bit ALU/accumulator
The 32-bit Arithmetic Logic Unit (ALU) and accumulator perform a wide range of arithmetic and logical
instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch
instructions dependent on the status of the ALU or a single bit in a word. These instructions provide the following
capabilities:
• Branch to an address specified by the accumulator

• Normalize fixed-point numbers contained in the accumulator

• Test a specified bit of a word in data memory

One input to the ALU is always provided from the accumulator, and the other input may be provided from the
Product Register (PR) of the multiplier or the input scaling shifter which has fetched data from the RAM on the
data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the accumulator.
The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the
output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The
contents of the accumulator remain unchanged.

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TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

functional block diagram (TMS320C2x)

SYNC
Program Bus
IS

CLKOUT1
CLKOUT2
X2/CLKIN
DS
PS 16 16 16

X1
16
PFC(16) QIR(16)
R/W
STRB IR(16)
16
READY STO(16)
MUX
BR

Controller
16 ST1(16)
XF
HOLD 16 16 RPTC(8)
HOLDA IFR(6)
MCS(16) PC(16)
MSC
DR
BIO CLKR
RS FSR
16 16 16 DX
IACK
CLKX
Address Stack FSX
MP/MC 16 16 16
3 (8 x 16) RSR(16)
INT(2-0) Program
ROM/ XSR(16)
16 16 EPROM 16
(4096 × 16)
DRR(16)
MUX

A15-A0
16 DXR(16)
Instruction 16 TIM(16)
16 PRD(16)
16
6 IMR(6)
16 16 8 GREG(8)
MUX

D15-D0 16 16
16

Data Bus Program Bus

16
16 16 16 16
16 16
3 9
AR0(16) TR(16)
7 LSB
AR1(16) From IR MUX
3
ARP(3) AR2(16) DP(9) 16
AR3(16) Multiplier

9 Shifter(0-16)
AR4(16)
3 AR5(16) PR(32)
AR6(16)
AR7(16) 32 32
16
ARB(3)
Shifter(-6, 0, 1, 4)
16
MUX 16 32
3
ARAU(16)
MUX
16 16
32
MUX MUX
32
16 16 ALU(32)

Block B2 DATA/PROG 32
(32 × 16) RAM (256 × 16)
Block B0 C ACCH(16) ACCL(16)
Data RAM
Block B1 32
(256 × 16)
16

MUX Shifters (0-7)†

16 16 16 16
Data Bus

LEGEND:
ACCH = Accumulator high IFR = Interrupt flag register PC = Program counter
ACCL = Accumulator low IMR = Interrupt mask register PFC = Prefetch counter
ALU = Arithmetic logic unit IR = Instruction register RPTC = Repeat instruction counter
ARAU = Auxiliary register arithmetic unitMCS = Microcall stack GREG = Global memory allocation register
ARB = Auxiliary register pointer buffer QIR = Queue instruction register RSR = Serial port receive shift register
ARP = Auxiliary register pointer PR = Product register XSR = Serial port transmit shift register
DP = Data memory page pointer PRD = Period register for timer AR0-AR7 = Auxiliary registers
DRR = Serial port data receive registerTIM = Timer ST0, ST1 = Status registers
DXR = Serial port data transmit register TR = Temporary register C = Carry bit

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 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

scaling shifter
The TMS320C2x scaling shifter has 16-bit input connected to the data bus and a 32-bit output connected to the
ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction.
The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign-extended,
depending upon the status programmed into the SXM (sign-extension mode) bit of status register ST1.
16 × 16-bit parallel multiplier
The 16 × 16-bit hardware multiplier is capable of computing a signed or unsigned 32-bit product in a single
machine cycle. The multiplier has the following two associated registers.
• A 16-bit Temporary Register (TR) that holds one of the operands for the multiplier, and

• A 32-bit Product Register (PR) that holds the product.

Incorporated into the instruction set are single-cycle multiply/accumulate instructions that allow both operands
to be processed simultaneously. The data for these operations may reside anywhere in internal or external
memory, and can be transferred to the multiplier each cycle via the program and data buses.
Four product shift modes are available at the Product Register (PR) output that are useful when performing
multiply/accumulate operations, fractional arithmetic, or justifying fractional products.
timer
The TMS320C2x provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM)
register is a down counter that is continuously clocked by CLKOUT1 on the TMS320C25. The timer is clocked
by CLKOUT1/4 on the TMS32020. A timer interrupt (TINT) is generated every time the timer decrements to zero.
The timer is reloaded with the value contained in the period (PRD) register within the next cycle after it reaches
zero so that interrupts may be programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT 1 on the
TMS320C25 or 4 × PRD × CLKOUT 1 cycles on the TMS32020.
memory control
The TMS320C2x provides a total of 544 16-bit words of on-chip data RAM, divided into three separate blocks
(B0, B1, and B2). Of the 544 words, 288 words (blocks B1 and B2) are always data memory, and 256 words
(block B0) are programmable as either data or program memory. A data memory size of 544 words allows the
TMS320C2x to handle a data array of 512 words (256 words if on-chip RAM is used for program memory), while
still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can
be downloaded from external program memory into on-chip RAM and then executed.
When using on-chip program RAM, ROM, EPROM, or high-speed external program memory, the TMS320C2x
runs at full speed without wait states. However, the READY line can be used to interface the TMS320C2x to
slower, less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program
RAM speeds processing while cutting system costs.
The TMS320C2x provides three separate address spaces for program memory, data memory, and I/O. The
on-chip memory is mapped into either the 64K-word data memory or program memory space, depending upon
the memory configuration (see Figure 1). The CNFD (configure block B0 as data memory) and CNFP (configure
block B0 as program memory) instructions allow dynamic configuration of the memory maps through software.
Regardless of the configuration, the user may still execute from external program memory.
The TMS320C2x has six registers that are mapped into the data memory space: a serial port data receive
register, serial port data transmit register, timer register, period register, interrupt mask register, and global
memory allocation register.

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TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

Program Program Data

0(0000h) 0(0000h) 0(0000h)
Interrupts Interrupts
and Reserved On-Chip
and Reserved Memory-Mapped
(External) (On-Chip
ROM/EPROM) Registers
31(001Fh) 31(001Fh) 5(0005h)
32(0020h ) 32(0020h ) 6(0006h)
Reserved Page 0
On-Chip
ROM/EPROM 95(005Fh)
4015(0FAFh)
96(0060h )
4016(0FB0h) On-Chip
127(007Fh) Block B2
Reserved 128(0080h)
4095(0FFFh)
4096(1000h) Reserved Pages 1-3
511(01FFh)
512(0200h)
External On-Chip Pages 4-5
767(02FFh) Block B0
768(0300h)
On-Chip
External Block B1 Pages 6 -7
1023(03FFh)
1024(0400h)

External Pages 8 -511

65,535(FFFFh) 65,535(0FFFFh) 65,535(0FFFFh)

If MP/MC = 1 If MP/MC = 0
(Microprocessor Mode) (Microcomputer Mode on TMS320C25)

(a) Memory Maps After a CNFD Instruction

Program Program Data

0(0000h) 0(0000h) Interrupts 0(0000h)
Interrupts On-Chip
and Reserved and Reserved
(On-Chip Memory-Mapped
(External) Registers
ROM/EPROM)
31(001Fh) 31(001Fh) 5(0005h)
32(0020h ) 32(0020h ) 6(0006h)
On-Chip
ROM/EPROM Reserved Page 0
4015(0FAFh) 95(005Fh)
4016(0FB0h) 96(0060h )
Reserved On-Chip
4095(0FFFh) Block B2
4096(1000h) 127(007Fh)
128(0080h)
Reserved Pages 1-3
511(01FFh)
External 512(0200h)
Does Not
Exist Pages 4-5
External 767(02FFh)
768(0300h)
On-Chip
Block B1 Pages 6 -7
1023(03FFh)
1024(0400h)

65,279(0FEFFh) 65,279(0FEFFh)
External Pages 8 -511
65,280(0FF00h) 65,280(0FF00h)
On-Chip On-Chip
Block B0 Block B0
65,535(0FFFFh) 65,535(0FFFFh) 65,535(0FFFFh)

If MP/MC = 1 If MP/MC = 0
(Microprocessor Mode) (Microcomputer Mode on TMS320C25)

(b) Memory Maps After a CNFP Instruction

Figure 1. Memory Maps

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 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

interrupts and subroutines

The TMS320C2x has three external maskable user interrupts INT2-INT0, available for external devices that
interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT),
and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest
priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on
two-word boundaries so that branch instructions can be accommodated in those locations if desired.
A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle
instruction, the interrupt is not processed until the instruction is completed. This mechanism applies to
instructions that are repeated and to instructions that become multicycle due to the READY signal.
external interface
The TMS320C2x supports a wide range of system interfacing requirements. Program, data, and I/O address
spaces provide interface to memory and I/O, thus maximizing system throughput. I/O design is simplified by
having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the
processor’s external address and data buses in the same manner as memory-mapped devices. Interface to
memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are
made with slower devices, the TMS320C2x processor waits until the other device completes its function and
signals the processor via the READY line. Then, the TMS320C2x continues execution.
A full-duplex serial port provides communication with serial devices, such as codecs, serial A/D converters, and
other serial systems. The interface signals are compatible with codecs and many other serial devices with a
minimum of external hardware. The serial port may also be used for intercommunication between processors
in multiprocessing applications.
The serial port has two memory-mapped registers: the data transmit register (DXR) and the data receive register
(DRR). Both registers operate in either the byte mode or 16-bit word mode, and may be accessed in the same
manner as any other data memory location. Each register has an external clock, a framing synchronization
pulse, and associated shift registers. One method of multiprocessing may be implemented by programming one
device to transmit while the others are in the receive mode. The serial port on the TMS320C25 is double-buffered
and fully static.
multiprocessing
The flexibility of the TMS320C2x allows configurations to satisfy a wide range of system requirements and can
be used as follows:
• A standalone processor
• A multiprocessor with devices in parallel
• A slave/host multiprocessor with global memory space
• A peripheral processor interfaced via processor-controlled signals to another device.
For multiprocessing applications, the TMS320C2x has the capability of allocating global data memory space
and communicating with that space via the BR (bus request) and READY control signals. Global memory is data
memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit
memory-mapped GREG (global memory allocation register) specifies part of the TMS320C2x’s data memory
as global external memory. The contents of the register determine the size of the global memory space. If the
current instruction addresses an operand within that space, BR is asserted to request control of the bus. The
length of the memory cycle is controlled by the READY line.
The TMS320C2x supports DMA (direct memory access) to its external program/data memory using the HOLD
and HOLDA signals. Another processor can take complete control of the TMS320C2x’s external memory by
asserting HOLD low. This causes the TMS320C2x to place its address data and control lines in a
high-impedance state, and assert HOLDA. On the TMS320C2x, program execution from on-chip ROM may
proceed concurrently when the device is in the hold mode.

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TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

instruction set
The TMS320C2x microprocessor implements a comprehensive instruction set that supports both
numeric-intensive signal processing operations as well as general-purpose applications, such as
multiprocessing and high-speed control. The TMS32020 source code is upward-compatible with TMS320C25
source code. TMS32020 object code runs directly on the TMS320C25.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the
same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary
depending upon whether the next data operand fetch is from internal or external memory. Highest throughput
is achieved by maintaining data memory on-chip and using either internal or fast external program memory.
addressing modes
The TMS320C2x instruction set provides three memory addressing modes: direct, indirect, and immediate
addressing.
Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the
instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data
memory address. Indirect addressing accesses data memory through the auxiliary registers. In immediate
addressing, the data is based on a portion of the instruction word(s).
In direct memory addressing, the instruction word contains the lower seven bits of the data memory address.
This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus,
memory is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words.
Up to eight auxiliary registers (AR0-AR7) provide flexible and powerful indirect addressing (five on the
TMS32020, eight on the TMS320C25). To select a specific auxiliary register, the Auxiliary Register Pointer
(ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
There are seven types of indirect addressing: auto-increment or auto-decrement, post-indexing by either adding
or subtracting the contents of AR0, single indirect addressing with no increment or decrement, and bit-reversal
addressing (used in FFTs on the TMS320C25 only) with increment or decrement. All operations are performed
on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary
register and ARP may be modified.
repeat feature
A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table
read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC) is loaded
with either a data memory value (RPT instruction) or an immediate value (RPTK instruction). The value of this
operand is one less than the number of times that the next instruction is executed. Those instructions that are
normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle
instructions.

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 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

instruction set summary

Table 2 lists the symbols and abbreviations used in Table 3, the TMS320C25 instruction set summary. Table 3
consists primarily of single-cycle, single-word instructions. Infrequently used branch, I/O, and CALL instructions
are multicycle. The instruction set summary is arranged according to function and alphabetized within each
functional grouping. The symbol (†) indicates those instructions that are not included in the TMS320C1x
instruction set. The symbol (‡) indicates instructions that are not included in the TMS32020 instruction set.

Table 2. Instruction Symbols

SYMBOL DEFINITION
B 4-bit field specifying a bit code
CM 2-bit field specifying compare mode
D Data memory address field
FO Format status bit
I Addressing mode bit
K Immediate operand field
PA Port address (PA0 through PA15 are predefined assembler symbols
equal to 0 through 15, respectively.)
PM 2-bit field specifying P register output shift code
AR 3-bit operand field specifying auxiliary register
S 4-bit left-shift code
X 3-bit accumulator left-shift field

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TMS320C25

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Table 3. TMS320C25 Instruction Set Summary

ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS

NO. INSTRUCTION BIT CODE

MNEMONIC DESCRIPTION
WORDS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABS Absolute value of accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 1
ADD Add to accumulator with shift 1 0 0 0 0 S I D
ADDC‡ Add to accumulator with carry 1 0 1 0 0 0 0 1 1 I D
ADDH Add to high accumulator 1 0 1 0 0 1 0 0 0 I D
ADDK‡ Add to accumulator short immediate 1 1 1 0 0 1 1 0 0 K
Add to low accumulator with sign
ADDS 1 0 1 0 0 1 0 0 1 I D
extension suppressed
Add to accumulator with shift specified by
ADDT 1 0 1 0 0 1 0 1 0 I D
T register
ADLK† Add to accumulator long immediate with shift 2 1 1 0 1 S 0 0 0 0 0 0 1 0
AND AND with accumulator 1 0 1 0 0 1 1 1 0 I D
ANDK† AND immediate with accumulator with shift 2 1 1 0 1 S 0 0 0 0 0 1 0 0
CMPL† Complement accumulator 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1
LAC Load accumulator with shift 1 0 0 1 0 S I D
LACK Load accumulator immediate short 1 1 1 0 0 1 0 1 0 K
Load accumulator with shift specified by
LACT† 1 0 1 0 0 0 0 1 0 I D
T register
LALK† Load accumulator long immediate with shift 2 1 1 0 1 S 0 0 0 0 0 0 0 1
NEG† Negate accumulator 1 1 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1
NORM† Normalize contents of accumulator 1 1 1 0 0 1 1 1 0 1 X X X 0 0 1 0
OR OR with accumulator 1 0 1 0 0 1 1 0 1 I D
ORK† OR immediate with accumulator with shift 2 1 1 0 1 S 0 0 0 0 0 1 0 1
ROL‡ Rotate accumulator left 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 0
ROR‡ Rotate accumulator right 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 1
SACH Store high accumulator with shift 1 0 1 1 0 1 X I D
SACL Store low-order accumulator with shift 1 0 1 1 0 0 X I D

SBLK† Subtract from accumulator long immediate

2 1 1 0 1 S 0 0 0 0 0 0 1 1
with shift
SFL† Shift accumulator left 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 0
SFR† Shift accumulator right 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1
SUB Subtract from accumulator with shift 1 0 0 0 1 S I D
SUBB‡ Subtract from accumulator with borrow 1 0 1 0 0 1 1 1 1 I D
SUBC Conditional subtract 1 0 1 0 0 0 1 1 1 I D
SUBH Subtract from high accumulator 1 0 1 0 0 0 1 0 0 I D
SUBK‡ Subtract from accumulator short immediate 1 1 1 0 0 1 1 0 1 K
Subtract from low accumulator with sign
SUBS 1 0 1 0 0 0 1 0 1 I D
extension suppressed
† These instructions are not included in the TMS320C1x instruction set.
‡ These instructions are not included in the TMS32020 instruction set.

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 TMS320C25

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Table 3. TMS320C25 Instruction Set Summary (continued)

ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS

NO. INSTRUCTION BIT CODE

MNEMONIC DESCRIPTION
WORDS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Subtract from accumulator with shift specified by
SUBT† 1 0 1 0 0 0 1 1 0 I D
T register
XOR Exclusive-OR with accumulator 1 0 1 0 0 1 1 0 0 I D
Exclusive-OR immediate with accumulator with
XORK† 2 1 1 0 1 S 0 0 0 0 0 1 1 0
shift
ZAC Zero accumulator 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0
ZALH Zero low accumulator and load high accumulator 1 0 1 0 0 0 0 0 0 I D
Zero low accumulator and load high accumulator
ZALR‡ 1 0 1 1 1 1 0 1 1 I D
with rounding
Zero accumulator and load low accumulator with
ZALS 1 0 1 0 0 0 0 0 1 I D
sign extension suppressed
AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS

NO. INSTRUCTION BIT CODE

MNEMONIC DESCRIPTION
WORDS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADRK‡ Add to auxiliary register short immediate 1 0 1 1 1 1 1 1 0 K
Compare auxiliary register with auxiliary
CMPR† 1 1 1 0 0 1 1 1 0 0 1 0 1 0 0 CM
register AR0
LAR Load auxiliary register 1 0 0 1 1 0 R I D
LARK Load auxilliary register short immediate 1 1 1 0 0 0 R K
LARP Load auxilliary register pointer 1 0 1 0 1 0 1 0 1 1 0 0 0 1 R
LDP Load data memory page pointer 1 0 1 0 1 0 0 1 0 I D
LDPK Load data memory page pointer immediate 1 1 1 0 0 1 0 0 DP
LRLK† Load auxiliary register long immediate 2 1 1 0 1 0 R 0 0 0 0 0 0 0 0
MAR Modify auxiliary register 1 0 1 0 1 0 1 0 1 I D
SAR Store auxiliary register 1 0 1 1 1 0 R I D
SBRK‡ Subtract from auxiliary register short immediate 1 0 1 1 1 1 1 1 1 K
† These instructions are not included in the TMS320C1x instruction set.
‡ These instructions are not included in the TMS32020 instruction set.

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TMS320C25

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Table 3. TMS320C25 Instruction Set Summary (continued)

T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS

NO. INSTRUCTION BIT CODE

MNEMONIC DESCRIPTION
WORDS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APAC Add P register to accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1
LPH† Load high P register 1 0 1 0 1 0 0 1 1 I D
LT Load T register 1 0 0 1 1 1 1 0 0 I D
LTA Load T register and accumulate previous product 1 0 0 1 1 1 1 0 1 I D
Load T register, accumulate previous product,
LTD 1 0 0 1 1 1 1 1 1 I D
and move data
Load T register and store P register in
LTP† 1 0 0 1 1 1 1 1 0 I D
accumulator
LTS† Load T register and subtract previous product 1 0 1 0 1 1 0 1 1 I D
MAC† Multiply and accumulate 2 0 1 0 1 1 1 0 1 I D
MACD† Multiply and accumulate with data move 2 0 1 0 1 1 1 0 0 I D
Multiply (with T register, store product in
MPY 1 0 0 1 1 1 0 0 0 I D
P register)
MPYA‡ Multiply and accumulate previous product 1 0 0 1 1 1 0 1 0 I D
MPYK Multiply immediate 1 1 0 1 K
MPYS‡ Multiply and subtract previous product 1 0 0 1 1 1 0 1 1 I D
MPYU‡ Multiply unsigned 1 1 1 0 0 1 1 1 1 I D
PAC Load accumulator with P register 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 0
SPAC Subtract P register from accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 0
SPH‡ Store high P register 1 0 1 1 1 1 1 0 1 I D
SPL‡ Store low P register 1 0 1 1 1 1 1 0 0 I D
SPM† Set P register output shift mode 1 1 1 0 0 1 1 1 0 0 0 0 0 1 0 PM
SQRA† Square and accumulate 1 0 0 1 1 1 0 0 1 I D
SQRS† Square and subtract previous product 1 0 1 0 1 1 0 1 0 I D
† These instructions are not included in the TMS320C1x instruction set.
‡ These instructions are not included in the TMS32020 instruction set.

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 TMS320C25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

Table 3. TMS320C25 Instruction Set Summary (continued)

BRANCH/CALL INSTRUCTIONS

NO. INSTRUCTION BIT CODE

MNEMONIC DESCRIPTION
WORDS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B Branch unconditionally 2 1 1 1 1 1 1 1 1 1 D
BACC† Branch to address specified by accumulator 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1
BANZ Branch on auxiliary register not zero 2 1 1 1 1 1 0 1 1 1 D
BBNZ† Branch if TC bit ≠ 0 2 1 1 1 1 1 0 0 1 1 D
BBZ† Branch if TC bit = 0 2 1 1 1 1 1 0 0 0 1 D
BC‡ Branch on carry 2 0 1 0 1 1 1 1 0 1 D
BGEZ Branch if accumulator ≥ 0 2 1 1 1 1 0 1 0 0 1 D
BGZ Branch if accumulator > 0 2 1 1 1 1 0 0 0 1 1 D
BIOZ Branch on I/O status = 0 2 1 1 1 1 1 0 1 0 1 D
BLEZ Branch if accumulator ≤ 0 2 1 1 1 1 0 0 1 0 1 D
BLZ Branch if accumulator < 0 2 1 1 1 1 0 0 1 1 1 D
BNC‡ Branch on no carry 2 0 1 0 1 1 1 1 1 1 D
BNV† Branch if no overflow 2 1 1 1 1 0 1 1 1 1 D
BNZ Branch if accumulator ≠ 0 2 1 1 1 1 0 1 0 1 1 D
BV Branch on overflow 2 1 1 1 1 0 0 0 0 1 D
BZ Branch if accumulator = 0 2 1 1 1 1 0 1 1 0 1 D
CALA Call subroutine indirect 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 0
CALL Call subroutine 2 1 1 1 1 1 1 1 0 1 D
RET Return from subroutine 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 1 0
I/O AND DATA MEMORY OPERATIONS

NO. INSTRUCTION BIT CODE

MNEMONIC DESCRIPTION
WORDS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BLKD† Block move from data memory to data memory 2 1 1 1 0 1 1 0 1 I D
Block move from program memory to data
BLKP† 2 1 1 1 1 1 1 0 0 I D
memory
DMOV Data move in data memory 1 0 1 0 1 0 1 1 0 I D
FORT† Format serial port registers 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 FO
IN Input data from port 1 1 0 0 0 PA I D
OUT Output data to port 1 1 1 1 0 PA I D
RFSM‡ Reset serial port frame synchronization mode 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 0
RTXM† Reset serial port transmit mode 1 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0
RXF† Reset external flag 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0
SFSM‡ Set serial port frame synchronization mode 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 1
STXM† Set serial port transmit mode 1 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1
SXF† Set external flag 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1
TBLR Table read 1 0 1 0 1 1 0 0 0 I D
TBLW Table write 1 0 1 0 1 1 0 0 1 I D
† These instructions are not included in the TMS320C1x instruction set.
‡ These instructions are not included in the TMS32020 instruction set.

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TMS320C25

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Table 3. TMS320C25 Instruction Set Summary (concluded)

CONTROL INSTRUCTIONS

NO. INSTRUCTION BIT CODE

MNEMONIC DESCRIPTION
WORDS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT† Test bit 1 1 0 0 1 B I D
BITT† Test bit specified by T register 1 0 1 0 1 0 1 1 1 I D
CNFD† Configure block as data memory 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 0 0
CNFP† Configure block as program memory 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 0 1
DINT Disable interrupt 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 1
EINT Enable interrupt 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0
IDLE† Idle until interrupt 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 1
LST Load status register STO 1 0 1 0 1 0 0 0 0 I D
LST1† Load status register ST1 1 0 1 0 1 0 0 0 1 I D
NOP No operation 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0
POP Pop top of stack to low accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1
POPD† Pop top of stack to data memory 1 0 1 1 1 1 0 1 0 I D
PSHD† Push data memory value onto stack 1 0 1 0 1 0 1 0 0 I D
PUSH Push low accumulator onto stack 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 0
RC‡ Reset carry bit 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0
RHM‡ Reset hold mode 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0
ROVM Reset overflow mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0
Repeat instruction as specified by data
RPT† 1 0 1 0 0 1 0 1 1 I D
memory value
Repeat instruction as specified by immediate
RPTK† 1 1 1 0 0 1 0 1 1 K
value
RSXM† Reset sign-extension mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 0
RTC‡ Reset test/control flag 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 0
SC‡ Set carry bit 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1
SHM‡ Set hold mode 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 1
SOVM Set overflow mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1
SST Store status register ST0 1 0 1 1 1 1 0 0 0 I D
SST1† Store status register ST1 1 0 1 1 1 1 0 0 1 I D
SSXM† Set sign-extension mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1
STC‡ Set test/control flag 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 1
TRAP† Software interrupt 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0
† These instructions are not included in the TMS320C1x instruction set.
‡ These instructions are not included in the TMS32020 instruction set.

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 TMS32020

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

TMS32020 PRODUCT NOTIFICATION

Texas Instruments has identified an unusual set of circumstances that will cause the BIT (Test Bit) instruction
on the TMS32020 to affect the contents of the accumulator; ideally, the BIT instruction should not affect the
accumulator. This set of conditions is:
1. The overflow mode is set (the OVM status register bit is set to one.)
2. And, the two LSBs of the BIT instruction opcode word are zero.
a. When direct memory addressing is used, every fourth data word is affected; all other locations are not
affected.
b. When indirect addressing is used, the two LSBs will be zero if a new ARP is not selected or if a new
ARP is selected and that ARP is 0 or 4.
3. And, adding the contents of the accumulator with the contents of the addressed data memory location,
shifted by 2 (bit code), causes an overflow of the accumulator.
If all of these conditions are met, the contents of the accumulator will be replaced by the positive or negative
saturation value, depending on the polarity of the overflow.
Various methods for avoiding this phenomenon are available:
• If the TMS32020 is not in the saturation mode when the BIT instruction is executed, the device operates
properly and the accumulator is not affected.
• Execute the Reset Overflow Mode (ROVM) instruction immediately prior to the BIT instruction and the Set
Overflow Mode (SOVM) instruction immediately following the BIT instruction.
• If direct memory addressing is being used during the BIT instructions, reorganize memory so that the page
relative locations 0, 4, 8, C, 10 . . . are not used.
• If indirect addressing is being used during the Bit instruction, select a new ARP which is not AR0 or AR4.
If necessary, follow the instruction with a LARP AR0 or LARP AR4 to restore the code.
• Use the Test Bit Specified by T Register (BITT) instruction instead of the BIT instruction. The BITT instruction
operates correctly and will not affect the accumulator under any circumstances.
• Replace TMS32020 with TMS320C25 for ideal pin-to-pIn and object-code compatibility. The BIT instruction
on the TMS320C25 executes properly and will not affect the accumulator under any circumstances.

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TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

development support
Together, Texas Instruments and its authorized third-party suppliers offer an extensive line of development
support products to assist the user in all aspects of TMS320 second-generation-based design and
development. These products range from development and application software to complete hardware
development and evaluation systems. Table 4 lists the development support products for the second-generation
TMS320 devices.
System development may begin with the use of the simulator, Software Development System (SWDS), or
emulator (XDS) along with an assembler/linker. These tools give the TMS320 user various means of evaluation,
from software simulation of the second-generation TMS320s (simulator) to full-speed in-circuit emulation with
hardware and software breakpoint trace and timing capabilities (XDS).
Software and hardware can be developed simultaneously by using the macro assembler/linker, C compiler, and
simulator for software development, the XDS for hardware development, and the Software Development
System for both software development and limited hardware development.
Many third-party vendors offer additional development support for the second-generation TMS320s, including
assembler/linkers, simulators, high-level languages, applications software, algorithm development tools,
application boards, software development boards, and in-circuit emulators. Refer to the TMS320 Family
Development Support Reference Guide (SPRU011A) for further information about TMS320 development
support products offered by both Texas Instruments and its third-party suppliers.
Additional support for the TMS320 products consists of an extensive library or product and applications
documentation. Three-day DSP design workshops are offered by the TI Regional Technology Centers (RTCs).
These workshops provide insight into the architecture and the instruction set of the second-generation
TMS320s as well as hands-on training with the TMS320 development tools. When technical questions arise
regarding the TMS320 family, contact the Texas Instruments TMS320 Hotline at (713) 274-2320. Or, keep
informed on the latest TI and third-party development support tools by accessing the DSP Bulletin Board Service
(BBS) at (713) 274-2323. The BBS serves 2400-, 1200- and 300-bps modems. Also, TMS320 application
source code may be downloaded from the BBS.

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 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

Table 4. TMS320 Second-Generation Software and Hardware Support

SOFTWARE TOOLS PART NUMBER
Macro Assembler/Linker
IBM MS/PC-DOS TMDS3242850-02
VAX/VMS TMDS3242250-08
VAX ULTRIX TMDS3242260-08
SUN UNIX TMDS3242550-08

Simulator
IBM MS/PC-DOS TMDS3242851-02
VAX/VMS TMDS3242251-08

C Compiler
IBM MS/PC-DOS TMDX3242855-02
VAX/VMS TMDX3242255-08
VAX ULTRIX TMDX3242265-08
SUN UNIX TMDX3242555-08

Digital Filter Design Package (DFDP)

IBM PC-DOS DFDP-IBM002

DSP Software Library

IBM MS/PC-DOS TMDC3240812-12
VAX/VMS TMDC3204212-18
HARDWARE TOOLS PART NUMBER

Analog Interface Board 2 (AIB2) RTC/AIB320A-06

Analog Interface Board Adaptor RTC/ADP320A-06

EPROM Programmer Adaptor Socket

TMDX3270120
(68 to 28-pin)

Software Development System (SWDS) TMDX3268821

XDS/22 Emulator (see Note) TMDS3262221

XDS/22 Upgrade (TMS32020 to TMS320C2x) TMDX3282226

NOTE: Emulation support for the TMS320C25-50 is available from Macrochip
Research, Inc.; refer to the TMS320 Family Development Support Reference
Guide (SPRU011A) for the mailing address.

IBM is a trademark of International Business Machines Corporation.

PC-DOS is a trademark of International Business Machines Corporation.
VAX and VMS are trademarks of Digital Equipment Corporation.
XDS is a trademark of Texas Instruments Incorporated.

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TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

documentation support
Extensive documentation supports the second-generation TMS320 devices from product announcement
through applications development. The types of documentation include data sheets with design specifications,
complete user’s guides, and 750 pages of application reports published in the book, Digital Signal Processing
Applications with the TMS320 Family (SPRA012A). An application report, Hardware Interfacing to the
TMS320C25 (SPRA014A), is available for that device.
A series of DSP textbooks is being published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board
service provides access to large amounts of information pertaining to the TMS320 family.
Refer to the TMS320 Family Development Support Reference Guide (SPRU011A) for further information about
TMS320 documentation. To receive copies of second-generation TMS320 literature, call the Customer
Response Center at 1-800-232-3200.

specification overview
The electrical specifications for the TMS32020, TMS320C25, TMS320E25, and TMS320C25-50 are given in
the following pages. Note that the electrical specifications for the TMS320E25 are identical to those for the
TMS320C25, with the addition of EPROM-related specifications. A summary of differences between
TMS320C25 and TMS320C25-50 specifications immediately follows the TMS320C25-50 specification.

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 TMS32020

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absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VCC‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VSS Supply voltage 0 V
All inputs except CLKIN 2 VCC + 0.3 V

ADVANCE INFORMATION
VIH High-level input voltage
CLKIN 2.4 VCC + 0.3 V
All inputs except CLKIN – 0.3 0.8 V
VIL Low-level input voltage
CLKIN – 0.3 0.8 V
IOH High-level output current 300 µA
IOL Low-level output current 2 mA
TA Operating free-air temperature (see Notes 1 and 2) 0 70 °C
NOTES: 1. Case temperature (TC) must be maintained below 90°C.
2. RθJA = 36°C/Watt, RθJC = 6°C/Watt.

electrical characteristics over specified free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP§ MAX UNIT
VOH High-level output voltage VCC = MIN, IOH = MAX 2.4 3 V
VOL Low-level output voltage VCC = MIN, IOL = MAX 0.3 0.6 V
IZ Three-state current VCC = MAX –20 20 µA
II Input current VI = VSS to VCC –10 10 µA
TA = 0°C, VCC = MAX, fx = MAX 360 mA
ICC Supply current TA = 25°C, VCC = MAX, fx = MAX 250 mA
TC = 90°C, VCC = MAX, fx = MAX 285 mA
CI Input capacitance 15 pF
CO Output capacitance 15 pF
§ All typical values for ICC are at VCC = 5 V, TA = 25°C.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions should be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either
V CC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling
Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 21

 TMS32020

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

CLOCK CHARACTERISTICS AND TIMING

The TMS32020 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency
of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be fundamental
mode, and parallel resonant, with an effective series resistance of 30 Ω, a power dissipation of 1 mW,
and be specified at a load capacitance of 20 pF.

PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT

fx Input clock frequency TA = 0°C to 70°C 6.7 20.5 MHz
fxs Serial port frequency TA = 0°C to 70°C 50 † 2563 MHz
C1, C2 TA = 0°C to 70°C 10 pF
† Value derived from characterization data; minimum fsx at test = 825 kHz.
ADVANCE INFORMATION

X1 X2/CLKIN

Crystal

C1 C2

Figure 2. Internal Clock Option

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the following table.

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN NOM MAX UNIT
tc(C) CLKOUT1/CLKOUT2 cycle time 195 597 ns
td(CIH-C) CLKIN high to CLKOUT1/CLKOUT2/STRB high/low 25 60 ns
tf(C) CLKOUT1/CLKOUT2/STRB fall time 10 ns
tr(C) CLKOUT1/CLKOUT2/STRB rise time 10 ns
tw(CL) CLKOUT1/CLKOUT2 low pulse duration 2Q – 15 2Q 2Q + 15 ns
tw(CH) CLKOUT1/CLKOUT2 high pulse duration 2Q – 15 2Q 2Q + 15 ns
td(C1-C2) CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high, etc. Q – 10 Q Q + 10 ns

NOTE 3: Q = 1/4tc(C).

22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS32020

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
tc(C) CLKIN cycle time 195 597 ns
tf(CI) CLKIN fall time 10† ns
tr(CI) CLKIN rise time 10† ns
tw(CIL) CLKIN low pulse duration, tc(CI) = 50 ns (see Note 4) 40 ns
tw(CIH) CLKIN high pulse duration, tc(CI) = 50 ns (see Note 4) 40 ns
tsu(S) SYNC setup time before CLKIN low 10 Q – 10 ns
th(S) SYNC hold time from CLKIN low 15 ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
4. CLKIN duty cycle [tr(CI) + tw(CIH)] / tc(CI) must be within 40-60%.

2.15 V

ADVANCE INFORMATION
RL = 825 Ω

From Output
Under Test Test
Point

CL = 100 pF

Figure 3. Test Load Circuit

2.0 V VIH (Min)

1.88 V
0.92 V
VIL (Max)
0.80 V
0

(a) Input

2.4 V VOH (Min)

2.2 V
0.8 V
VOL (Max)
0.6 V
0

(b) Output

Figure 4. Voltage Reference Levels

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 23

 TMS32020

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT
td(C1-S) STRB from CLKOUT1 (if STRB is present) Q – 15 Q Q + 15 ns
td(C2-S) CLKOUT2 to STRB (if STRB is present) – 15 0 15 ns
tsu(A) Address setup hold time before STRB low (see Note 5) Q – 30 ns
th(A) Address hold time after STRB high (see Note 5) Q – 15 ns
tw(SL) STRB low pulse duration (no wait states, see Note 6) 2Q ns
tw(SH) STRB high pulse duration (between consecutive cycles, see Note 6) 2Q ns
tsu(D)W Data write setup time before STRB high (no wait states) 2Q – 45 ns
th(D)W Data write hold time from STRB high Q – 15 Q ns
ten(D) Data bus starts being driven after STRB low (write cycle) 0† ns
tdis(D) Data bus three-state after STRB high (write cycle) Q Q + 30† ns
ADVANCE INFORMATION

td(MSC) MSC valid from CLKOUT1 – 25 0 25 ns

† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.
6. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with
no wait states.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
ta(A) Read data access time from address time (read cycle, see Notes 5 and 7) 3Q – 70† ns
tsu(D)R Data read setup time before STRB high 40 ns
th(D)R Data read hold time from STRB high 0 ns
td(SL-R) READY valid after STRB low (no wait states) Q – 40 ns
td(C2H-R) READY valid after CLKOUT2 high Q – 40 ns
th(SL-R) READY hold time after STRB low (no wait states) Q–5 ns
th(C2H-R) READY hold after CLKOUT2 high Q–5 ns
td(M-R) READY valid after MSC valid 2Q – 50 ns
th(M-R) READY hold time after MSC valid 0 ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.
7. Read data access time is defined as ta(A) = tsu(A) + tw(SL) – tsu(D)R.

24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS32020

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

RS, INT, BIO, AND XF TIMING

switching characteristics over recommended operating conditions (see Note 3 and 8)

PARAMETER MIN TYP MAX UNIT
td(RS) CLKOUT1 low to reset state entered 45 ns
td(IACK) CLKOUT1 to IACK valid – 25 0 25 ns
td(XF) XF valid before falling edge of STRB Q – 30 ns

NOTES: 3. Q = 1/4tc(C).
8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met,
the exact sequence shown in the timing diagrams will occur.

timing requirements over recommended operating conditions (see Note 3 and 8)

MIN NOM MAX UNIT
tsu(IN) INT/BIO/RS setup before CLKOUT1 high 50 ns
th(IN) INT/BIO/RS hold after CLKOUT1 high 0 ns

ADVANCE INFORMATION
tf(IN) INT/BIO fall time 15† ns
tw(IN) INT/BIO low pulse duration tc(C) ns
tw(RS) RS low pulse duration 3tc(C) ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met,
the exact sequence shown in the timing diagrams will occur.

HOLD TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT
td(C1L-AL) HOLDA low after CLKOUT1 low –25† 25 ns
tdis(AL-A) HOLDA low to address three-state 15† ns
tdis(C1L-A) Address three-state after CLKOUT1 low (HOLD mode, see Note 9) 30† ns
td(HH-AH) HOLD high to HOLDA high 50 ns
ten(A-C1L) Address driven before CLKOUT1 low (HOLD mode, see Note 9) 10† ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
9. A15-A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as “address.”

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
td(C2H-H) HOLD valid after CLKOUT2 high Q – 45 ns

NOTE 3: Q = 1/4tc(C).

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 25

 TMS32020

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

SERIAL PORT TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT
td(CH-DX) DX valid after CLKX rising edge (see Note 10) 100 ns
td(FL-DX) DX valid after FSX falling edge (TXM = 0, see Note 10) 50 ns
td(CH-FS) FSX valid after CLKX rising edge (TXM = 1) 60 ns

NOTES: 3. Q = 1/4tc(C).
10. The last occurrence of FSX falling and CLKX rising.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
tc(SCK) Serial port clock (CLKX/CLKR) cycle time 390 20 000† ns
tf(SCK) Serial port clock (CLKX/CLKR) fall time 50‡ ns
50‡
ADVANCE INFORMATION

tr(SCK) Serial port clock (CLKX/CLKR) rise time ns

tw(SCK) Serial port clock (CLKX/CLKR) low pulse duration (see Note 11) 150 12 000 ns
tw(SCK) Serial port clock (CLKX/CLKR) high pulse duration (see Note 11) 150 12 000 ns
tsu(FS) FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0) 20 ns
th(FS) FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0) 20 ns
tsu(DR) DR setup time before CLKR falling edge 20 ns
th(DR) DR hold time after CLKR falling edge 20 ns
† Value derived from characterization data; minimum fsx at test = 825 kHz.
‡ Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
11. The duty cycle of the serial port clock must be within 40-60%.

26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320C25, TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VCC‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Input voltage range: TMS320E25 pins 24 and 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V
All other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V

ADVANCE INFORMATION
VSS Supply voltage 0 V
All inputs except CLKIN/CLKX/CLKR/INT (0-2) 2.35 VCC + 0.3 V
VIH High-level input voltage INT (0-2) 2.5 VCC + 0.3 V
CLKIN / CLKX / CLKR 3.5 VCC + 0.3 V
All inputs except MP/ MC – 0.3 0.8 V
VIL Low-level input voltage
MP/ MC – 0.3 0.8 V
IOH High-level output current 300 µA
IOL Low-level output current 2 mA
TMS320C25, TMS320E25 0 70 °C
TA Operating free-air temperature
TMS320C25GBA – 40 85 °C

electrical characteristics over specified free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP§ MAX UNIT
VOH High-level output voltage VCC = MIN, IOH = MAX 2.4 3 V
VOL Low-level output voltage VCC = MIN, IOL = MAX 0.3 0.6 V
IZ Three-state current VCC = MAX – 20 20 µA
II Input current VI = VSS to VCC – 10 10 µA
Normal 110 185
ICC Low-level input voltage TA = 0°C, VCC = MAX, fx = MAX mA
Idle/HOLD 50 100
CI Input capacitance 15 pF
CO Output capacitance 15 pF
§ All typical values are at VCC = 5 V, TA = 25°.

Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions to be taken to avoid application of any voltage higher than
maximum rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication “Guidelines for Handling
Electrostatic-Discharge Sensitive (ESDS) Devices and Assemblies” available from Texas Instruments

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 27

 TMS320C25, TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

CLOCK CHARACTERISTICS AND TIMING

The TMS32025 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency
of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be either fundamental
or overtone mode, and parallel resonant, with an effective series resistance of 30 Ω, a power dissipation
of 1 mW, and be specified at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned
LC circuit; see the application report, Hardware Interfacing to the TMS320C25 (SPRA014A).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fx Input clock frequency TA = 0°C to 70°C 6.7 40.96 MHz
fxs Serial port frequency TA = 0°C to 70°C 0† 5 120 MHz
C1, C2 TA = 0°C to 70°C 10 pF
† The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down
to fsx = 0 Hz.
ADVANCE INFORMATION

X1 X2/CLKIN

Crystal

C1 C2

Figure 2. Internal Clock Option

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the following table.

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT
tc(C) CLKOUT1/CLKOUT2 cycle time 97.7 597 ns
td(CIH-C) CLKIN high to CLKOUT1/CLKOUT2/STRB high/low 5 30 ns
tf(C) CLKOUT1/CLKOUT2/STRB fall time 5 ns
tr(C) CLKOUT1/CLKOUT2/STRB rise time 5 ns
tw(CL) CLKOUT1/CLKOUT2 low pulse duration 2Q – 8 2Q 2Q + 8 ns
tw(CH) CLKOUT1/CLKOUT2 high pulse duration 2Q – 8 2Q 2Q + 8 ns
td(C1-C2) CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high, etc. Q–5 Q Q+5 ns

NOTE 3: Q = 1/4tc(C).

28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320C25, TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
tc(CI) CLKIN cycle time 24.4 150 ns
tf(CI) CLKIN fall time 5† ns
tr(CI) CLKIN rise time 5† ns
tw(CIL) CLKIN low pulse duration, tc(CI) = 50 ns (see Note 4) 20 ns
tw(CIH) CLKIN high pulse duration, tc(CI) = 50 ns (see Note 4) 20 ns
tsu(S) SYNC setup time before CLKIN low 5 Q–5 ns
th(S) SYNC hold time from CLKIN low 8 ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
4. CLKIN duty cycle [tr(CI) + tw(CIH)]/tc(CI) must be within 40-60%.
+5 V
TMS320C25 fcrystal

ADVANCE INFORMATION
10 kΩ
74HC04
F11 4.7 kΩ
CLKIN

C = 20 pF 0.1 µF
47 pF 74AS04
10 kΩ

fcrystal, (MHz) L, (µH)

TMS320C25 40.96 1.8

TMS320C25-50 51.20 1.0
TMS320E25 40.96 1.8

Figure 3. External Clock Option

Shown above is a crystal oscillator circuit suitable for providing the input clock signal to the TMS320C25,
TMS320E25, and TMS320C25-50. Please refer to Hardware Interfacing to the TMS320C25 (document number
SPRA014A) for details on circuit operation.

2.15 V

RL = 825 Ω

From Output
Under Test Test
Point

CL = 100 pF

Figure 4. Test Load Circuit

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 29

 TMS320C25, TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

2.0 V VIH (Min) 2.4 V VOH (Min)

1.88 V 2.2 V
0.92 V 0.8 V
VIL (Max) VOL (Max)
0.80 V 0.6 V
0 0

(a) Input (b) Output

Figure 5. Voltage Reference Levels

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT
ADVANCE INFORMATION

td(C1-S) STRB from CLKOUT1 (if STRB is present) Q–6 Q Q+6 ns

td(C2-S) CLKOUT2 to STRB (if STRB is present) –6 0 6 ns
tsu(A) Address setup time before STRB low (see Note 5) Q – 12 ns
th(A) Address hold time after STRB high (see Note 5) Q–8 ns
tw(SL) STRB low pulse duration (no wait states, see Note 6) 2Q – 5 2Q + 5 ns
tw(SH) STRB high pulse duration (between consecutive cycles, see Note 6) 2Q – 5 2Q + 5 ns
tsu(D)W Data write setup time before STRB high (no wait states) 2Q – 20 ns
th(D)W Data write hold time from STRB high Q – 10 Q ns
ten(D) Data bus starts being driven after STRB low (write cycle) 0† ns
tdis(D) Data bus three-state after STRB high (write cycle) Q Q + 15† ns
td(MSC) MSC valid from CLKOUT1 – 12 0 12 ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.
6. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait
states.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
ta(A) Read data access time from address time (read cycle, see Notes 5 and 7) 3Q – 35 ns
tsu(D)R Data read setup time before STRB high 23 ns
th(D)R Data read hold time from STRB high 0 ns
td(SL-R) READY valid after STRB low (no wait states) Q – 20 ns
td(C2H-R) READY valid after CLKOUT2 high Q – 20 ns
th(SL-R) READY hold time after STRB low (no wait states) Q+3 ns
th(C2H-R) READY hold after CLKOUT2 high Q+3 ns
td(M-R) READY valid after MSC valid 2Q – 25 ns
th(M-R) READY hold time after MSC valid 0 ns

NOTES: 3. Q = 1/4tc(C).
5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.
7. Read data access time is defines as ta(A) = tsu(A) + tw(SL) – tsu(D)R.

30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320C25, TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

RS, INT, BIO, AND XF TIMING

switching characteristics over recommended operating conditions (see Note 3 and 8)

PARAMETER MIN TYP MAX UNIT
td(RS) CLKOUT1 low to reset state entered 22† ns
td(IACK) CLKOUT1 to IACK valid –6 0 12 ns
td(XF) XF valid before falling edge of STRB Q – 15 ns

NOTES: 3. Q = 1/4tc(C).
8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is
met, the exact sequence shown in the timing diagrams will occur.

timing requirements over recommended operating conditions (see Note 3 and 8)

MIN NOM MAX UNIT
tsu(IN) INT/BIO/RS setup before CLKOUT1 high 32 ns
th(IN) INT/BIO/RS hold after CLKOUT1 high 0 ns

ADVANCE INFORMATION
tf(IN) INT/BIO fall time 8† ns
tw(IN) INT/BIO low pulse duration tc(C) ns
tw(RS) RS low pulse duration 3tc(C) ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is
met, the exact sequence shown in the timing diagrams will occur.

HOLD TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT
td(C1L-AL) HOLDA low after CLKOUT1 low 0 10 ns
tdis(AL-A) HOLDA low to address three-state 0† ns
tdis(C1L-A) Address three-state after CLKOUT1 low (HOLD mode, see Note 9) 20† ns
td(HH-AH) HOLD high to HOLDA high 25 ns
ten(A-C1L) Address driven before CLKOUT1 low (HOLD mode, see Note 9) 8† ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
9. A15-A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as “address.”

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
td(C2H-H) HOLD valid after CLKOUT2 high Q – 24 ns

NOTE 3: Q = 1/4tc(C).

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 31

 TMS320C25, TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

SERIAL PORT TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT
td(CH-DX) DX valid after CLKX rising edge (see Note 10) 75 ns
td(FL-DX) DX valid after FSX falling edge (TXM = 0, see Note 10) 40 ns
td(CH-FS) FSX valid after CLKX rising edge (TXM = 1) 40 ns

NOTES: 3. Q = 1/4tc(C).
10. The last occurrence of FSX falling and CLKX rising.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
tc(SCK) Serial port clock (CLKX/CLKR) cycle time† 200 ns
tf(SCK) Serial port clock (CLKX/CLKR) fall time 25‡ ns
25‡
ADVANCE INFORMATION

tr(SCK) Serial port clock (CLKX/CLKR) rise time ns

tw(SCK) Serial port clock (CLKX/CLKR) low pulse duration (see Note 11) 80 ns
tw(SCK) Serial port clock (CLKX/CLKR) high pulse duration (see Note 11) 80 ns
tsu(FS) FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0) 18 ns
th(FS) FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0) 20 ns
tsu(DR) DR setup time before CLKR falling edge 10 ns
th(DR) DR hold time after CLKR falling edge 20 ns
† The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down
to fsx = 0 Hz.
‡ Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4tc(C).
11. The duty cycle of the serial port clock must be within 40-60%.

32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

EPROM PROGRAMMING

absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VPP‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 15 V
Input voltage range on pins 24 and 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V
† Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to GND.

recommended operating conditions

MIN NOM MAX UNIT
VCC Programming mode supply voltage (see Note 13) 6 V
VCC Read mode supply voltage 4.75 5 5.25 V
VPP Programming mode supply voltage 12 12.5 13 V
VPP Read mode supply voltage (see Note 12) VCC V

ADVANCE INFORMATION
NOTES: 12. VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + IPP. During
programming, VPP must be maintained at 12.5 V (± 0.25 V).
13. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. This device must not be
inserted into or removed from the board when VPP or VCC is applied.

electrical characteristics over specified temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP§ MAX UNIT
IPP1 VPP supply current VPP = VCC = 5.25 V 100 µA
IPP2 VPP supply current (during program pulse) VPP = 13 V 30 50 mA
§ All typical values for ICC are at VCC = 5 V, TA = 25°C.

recommended timing requirements for programming, TA = 25°C, VCC = 6 V, VPP = 12.5 V

(see Notes 14 and 15)
MIN NOM MAX UNIT
tw(IPGM) Initial program pulse duration 0.95 1 1.05 ms
tw(FPGM) Final pulse duration 2.85 78.75 ms
tsu(A) Address setup time 2 µs
tsu(E) E setup time 2 µs
tsu(G) G setup time 2 µs
tdis(G) Output disable time from G 0 130¶ ns
ten(G) Output enable time from G 150¶ ns
tsu(D) Data setup time 2 µs
tsu(VPP) VPP setup time 2 µs
tsu(VCC) VCC setup time 2 µs
th(A) Address hold time 0 µs
th(D) Data hold time 2 µs
¶ Value derived from characterization data and not tested.
NOTES: 14. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and VPP = 12.5 V ± 0.5 V during
programming.
15. Common test conditions apply for tdis(G) except during programming.

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 TMS320C25-50

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VCC‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VSS Supply voltage 0 V
INT0-INT2 2.5 V
ADVANCE INFORMATION

VIH High-level input voltage CLKIN, CLKX, CLKR 3.5 V

Other inputs 2.35 V
MP/MC 0.8 V
VIL Low-level input voltage CLKIN 0.8 V
Other inputs 0.8 V
IOH High-level output current 300 µA
IOL Low-level output current 2 mA
TA Operating free-air temperature 0 70 °C

electrical characteristics over specified free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP§ MAX UNIT
VOH High-level output voltage VCC = MIN, IOH = MAX 2.4 V
VOL Low-level output voltage VCC = MIN, IOL = MAX 0.6 V
IZ High-impedance current VCC = MAX – 20 20 µA
II Input current VI = VSS to VCC – 10 10 µA
Normal 110 185
ICC Supply current TA = 0°C, VCC = MAX, fx = MAX mA
Idle, HOLD 50 100
CI Input capacitance 15 pF
CO Output capacitance 15 pF
§ All typical values are at VCC = 5 V, TA = 25°C.

34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320C25-50

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

CLOCK CHARACTERISTICS AND TIMING

The TMS320C25-50 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2, CLKIN. The frequency of CLKOUT1
is one-fourth the crystal fundamental frequency. The crystal should be in either fundamental or overtone mode,
and parallel resonant, with an effective series resistance of 30 Ω, a power dissipation of 1 mW, and be specified
at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned LC circuit.

PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT

fx Input clock frequency TA = 0°C to 70°C 6.7 51.2 MHz
fsx Serial port frequency TA = 0°C to 70°C 0 6.4 MHz
C1, C2 TA = 0°C to 70°C 10 pF
† The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down to
fsx = 0 Hz.

ADVANCE INFORMATION
X1 X2/CLKIN

Crystal

C1 C2

Figure 6. Internal Clock Option

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLK, with X1 left
unconnected. The external frequency injected must conform to specifications listed in the following table.

switching characteristics over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
tc(C) CLKOUT1, CLKOUT2 cycle time 78.13 597 ns
td(CIH-C) CLKIN high to CLKOUT1, CLKOUT2, STRB high, low 12 27 ns
tf(C) CLKOUT1, CLKOUT2, STRB fall time 4 ns
tr(C) CLKOUT1, CLKOUT2, STRB rise time 4 ns
tw(CL) CLKOUT1, CLKOUT2, STRB low pulse duration 2Q – 7 2Q + 3 ns
tw(CH) CLKOUT1, CLKOUT2, STRB high pulse duration 2Q – 3 2Q + 7 ns
CLKOUT1 high to CLKOUT2 low,
td(C1-C2) Q–6 Q+2 ns
CLKOUT2 high to CLKOUT1 high, etc.

NOTE 3: Q = 1/4 tc(C)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 35

 TMS320C25-50

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

+5 V
TMS320C25 fcrystal

10 kΩ
74HC04
F11 4.7 kΩ
CLKIN

C = 20 pF 0.1 µF
47 pF 74AS04
10 kΩ

fcrystal, (MHz) L, (µH)

TMS320C25 40.96 1.8

TMS320C25-50 51.20 1.0
ADVANCE INFORMATION

TMS320E25 40.96 1.8

Figure 7. External Clock Option

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
19.5
tc(CI) CLKIN cycle time 150 ns
3
tf(CI) CLKIN fall time 5† ns
tr(CI) CLKIN rise time 5† ns
tw(CIL) CLKIN low pulse duration, tc(CI) = 50 ns (see Note 4) 20 ns
tw(CIH) CLKIN high pulse duration, tc(CI) = 50 ns (see Note 4) 20 ns
tsu(S) SYNC setup time before CLKIN low 4 Q–4 ns
th(S) SYNC hold time from CLKIN low 4 ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4 tc(C)
4. CLKIN duty cycle [tr(CI) + tw(CIH)]/tc(CI) must be within 40-60%.

36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320C25-50

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT
td(C1-S) STRB from CLKOUT (if STRB is present) Q–5 Q+3 ns
td(C2-S) CLKOUT2 to STRB (if STRB is present) –2 5 ns
tsu(A) Address setup time before STRB low (see Note 5) Q – 11 ns
tn(A) Address hold time after STRB high (see Note 5) Q–4 ns
tw(SL) STRB low pulse duration (no wait states, see Note 6) 2Q – 5 2Q + 2 ns
tw(SH) STRB high pulse duration (between consecutive cycles, see Note 6) 2Q – 2 2Q + 5† ns
tsu(D)W Data write setup time before STRB high (no wait) 2Q – 17 ns
th(D)W Data write hold time from STRB high Q–5 ns
ten(D) Data bus starts being driven after STRB low (write) 0† ns
tdis(D) Data bus high-impedance state after STRB high, (write) Q Q + 15† ns

ADVANCE INFORMATION
td(MSC) MSC valid from CLKOUT1 –1 9 ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4 tc(C)
5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.
6. Delay between CLKOUT1, CLKOUT2, and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait states.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
ta(A) Read data access time from address time (see Notes 5 and 7) 3Q – 30 ns
tsu(D)R Data read setup time before STRB high 19 ns
th(D)R Data read hold time from STRB high 0 ns
td(SL-R) READY valid after STRB low (no wait states) Q – 21 ns
td(C2H-R) READY valid after CLKOUT2 high Q – 21 ns
th(SL-R) READY hold time after STRB low (no wait states) Q–1 ns
th(C2H-R) READY valid after CLKOUT2 high Q–1 ns
td(M-R) READY valid after MSC valid 2Q – 24 ns
th(M-R) READY hold time after MSC valid 0 ns

NOTES: 3. Q = 1/4 tc(C)

5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.
7. Read data access time is defined as ta(A) = tsu(A) + tw(SL) – tsu(D)R.

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 TMS320C25-50

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

RS, INT, BIO, AND XF TIMING

switching characteristics over recommended operating conditions (see Notes 3 and 16)
PARAMETER MIN TYP MAX UNIT
td(RS) CLKOUT1 low to reset state entered 22† ns
td(IACK) CLKOUT1 to IACK valid –5 7 ns
td(XF) XF valid before falling edge of STRB Q–8 ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4 tc(C)
16. RS, INT, BIO are asynchronous inputs and can occur at any time during a clock cycle.

timing requirements over recommended operating conditions (see Notes 3 and 16)
MIN NOM MAX UNIT
tsu(IN) INT, BIO, RS setup before CLKOUT1 high 25 ns
th(IN) INT, BIO, RS hold after CLKOUT1 high 0 ns
ADVANCE INFORMATION

tf(IN) INT, BIO fall time 8† ns

tw(IN) INT, BIO low pulse duration tc(C) ns
tw(RS) RS low pulse duration 3tc(C) ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4 tc(C)
16. RS, INT, BIO are asynchronous inputs and can occur at any time during a clock cycle.

HOLD TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT
td(CIL-AL) HOLDA low after CLKOUT1 low 1† 11 ns
tdis(AL-A) HOLDA low to address high-impedance 0† ns
tdis(CIL-A) Address high-impedance after CLKOUT1 low (HOLD mode, see Note 17) 20 † ns
td(HH-AH) HOLD high to HOLDA high 19 ns
ten(A-CIL) Address driven before CLKOUT1 low (HOLD mode, see Note 17) 8† ns
† Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4 tc(C)
17. A15-A0, PS, DS, STRB, and R/W timings are all included in timings referenced as “address”.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
td(C2H-H) HOLD valid after CLKOUT2 high Q – 19 ns

NOTE 3: Q = 1/4 tc(C)

38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320C25-50

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

SERIAL PORT TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER MIN TYP MAX UNIT
td(CH-DX) DX valid after CLKX rising edge (see Note 18) 75 ns
td(FL-DX) DX valid after falling edge (TXM = 0, see Note 18) 40 ns
td(CH-FS) FSX valid after CLKX raising edge (TXM = 1) 40 ns

NOTES: 3. Q = 1/4 tc(C)

18. The last occurrence of FSX falling and CLKX rising.

timing requirements over recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
tc(SCK) Serial port clock (CLKX/CLKR) cycle time † 160 ns
tf(SCK) Serial port clock (CLKX/CLKR) fall time 25 ‡ ns
tr(SCK) Serial port clock (CLKX/CLKR) rise time 25 ‡ ns

ADVANCE INFORMATION
tw(SCK) Serial port clock (CLKX/CLKR) low or high pulse duration (see Note 19) 64 ns
tsu(FS) FSX or FSR setup time before CLKX, CLKR falling edge (TXM = 0) 5 ns
th(FS) FSX or FSR hold time before CLKX, CLKR falling edge (TXM = 0) 10 ns
tsu(DR) DR setup time before CLKR falling edge 5 ns
th(DR) DR hold time after CLKR falling edge 10 ns
† The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down to
fsx = 0 Hz.
‡ Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4 tc(C)
19. The cycle of the serial port must be within 40%-60%.

CONTRAST SUMMARY OF ELECTRICAL SPECIFICATIONS

The following table presents electrical parameters which differ between TMS320C25 (40 MHz, 100 ns) and
TMS320C25-50 (50 MHz, 80 ns).

clock characteristics and timing

TMS320C25 TMS320C25-50
PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
tc(SCK) 97.7 597 78.13 597 ns
td(CIH-C) 5 30 12 27 ns
tf(C) 5 4 ns
tr(C) 5 4 ns
tw(CL) 2Q – 8 2Q 2Q + 8 2Q – 7 2Q + 3 ns
tw(CH) 2Q – 8 2Q 2Q + 8 2Q – 3 2Q + 7 ns
td(C1-C2) Q–5 Q Q+5 Q–6 Q+2 ns
tsu(S) 5 Q–5 4 Q–4 ns
th(S) 8 4 ns

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 TMS320C25-50

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

memory and peripheral interface timing

TMS320C25 TMS320C25-50
PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
td(C1-S) Q –6 Q Q+6 Q–5 Q+3 ns
td(C2-S) –6 0 6 –2 5 ns
tsu(A) Q – 12 Q – 11 ns
th(A) Q–8 Q–4 ns
tw(SL) 2Q 2Q – 5 2Q + 2 ns
tw(SH) 2Q 2Q – 2 2Q + 5 ns
tsu(D)W 2Q – 20 2Q – 17 ns
th(D)W Q – 10 Q Q–5 ns
td(MSC) – 12 0 12 –1 9 ns
ta(A) 3Q – 35 3Q – 30 ns
tsu(D)R 23 19 ns
th(D)R 0 0 ns
ADVANCE INFORMATION

td(SL-R) Q – 20 Q – 21 ns
td(C2H-R) Q – 20 Q – 21 ns
th(SL-R) Q+3 Q–1 ns
th(C2H-R) Q+3 Q–1 ns
td(M-R) 2Q – 25 2Q – 24 ns
th(M-R) 0 0 ns

RS, INT, BIO, and XF timing

TMS320C25 TMS320C25-50
PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
td(IACK) –6 0 12 –5 7 ns
td(XF) Q – 15 Q–8 ns
tsu(IN) 32 25 ns
th(IN) 0 0 ns

HOLD timing
TMS320C25 TMS320C25-50
PARAMETER MIN TYP MAX MIN TYP MAX UNIT

td(C1L-AL) 0 10 1 11 ns
td(HH-AH) 25 19 ns
td(C2H-H) Q – 24 Q – 19 ns

serial port timing

TMS320C25 TMS320C25-50
PARAMETER MIN TYP MAX MIN TYP MAX UNIT

td(CH-DX) 75 70 ns
td(FL-DX) 40 40 ns
td(CH-FS) 40 40 ns
tsu(FS) 18 5 ns
th(FS) 20 10 ns
tsu(DR) 10 5 ns
th(DR) 20 10 ns

40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

TIMING DIAGRAMS

This section contains all the timing diagrams for the TMS320 second-generation devices. Refer to the top corner
of page for the specific device.
Timing measurements are referenced to and from a low voltage of 0.8 voltage and a high voltage of 2 volts,
unless otherwise noted.

clock timing
tc(CI)
tf(CI)
tr(CI)

X/2CLKIN

tw(CIH)
th(S)
tw(CIL)
tsu(S) tsu(S)

ADVANCE INFORMATION
SYNC
tc(C)
td(CIH-C) tw(CL)
td(CIH-C)

CLKOUT1

tw(CH)

td(CIH-C) tr(C) tf(C)

STRB

td(CIH-C)
tc(C)
tw(CL)

CLKOUT2

td(C1-C2) td(C1-C2) tf(C) tr(C)

td(C1-C2) tw(CH)
td(C1-C2)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 41

 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

memory read timing

td(C1-S)

CLKOUT1

td(C1-S)

CLKOUT2

td(C2-S) td(C2-S)

STRB

tw(SH)

tsu(A) th(A)
tw(SL)
ADVANCE INFORMATION

A15-A0,
BR, PS, DS Valid
or IS

ta(A)

R/W

td(SL-R)
tsu(D)R

READY

th(SL-R) th(D)R

D15-D0 Data In

42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

memory write timing

CLKOUT1

CLKOUT2

STRB

th(A)
tsu(A)

A15-A0,
BR, PS, DS Valid
or IS

ADVANCE INFORMATION
R/W

READY

tsu(D)W
th(D)W

D15-D0 Data Out

ten(D) tdis(D)

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 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

one wait-state memory access timing

CLKOUT1

CLKOUT2

STRB

th(C2H-R)
A15-A0, BR,
PS, DS, R/W or Valid
IS
th(C2H-R) td(C2H-R)
td(C2H-R)
ADVANCE INFORMATION

READY

td(M-R) th(M-R)
th(M-R) td(M-R)
D15-D0
(For Read Data In
Operation)

D15-D0
(For Write Data Out
Operation)
td(MSC)
td(MSC)

MSC

44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

reset timing

CLKOUT1

tsu(IN) td(RS) tsu(IN)

th(IN)

RS

tw(RS)

A15-A0 Valid

Fetch
Location 0
D15-D0

Valid Begin
Program
PS Execution

ADVANCE INFORMATION
STRB

Control
Signals†

IACK

Serial Port
Control‡

† Control signals are DS, IS, R/W, and XF.

‡ Serial port controls are DX and FSX.

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 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

interrupt timing (TMS32020)

CLKOUT1

STRB

tsu(IN) th(IN)
tw(IN)

INT2-INT0

tf(IN) td(IACK)

A15-A0 FETCH N FETCH N + 1 FETCH I FETCH I + 1

ADVANCE INFORMATION

td(IACK)

IACK

interrupt timing (TMS320C25)

CLKOUT1

tsu(IN)

STRB

th(IN)
tw(IN)

INT2-INT0

tf(IN) td(IACK)

A15-A0 FETCH N FETCH N + 1 FETCH N + 2 N+3 FETCH I

td(IACK)

IACK

46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

serial port receive timing

tc(SCK)
tr(SCK)
tw(SCK)

CLKR

th(DR) tf(SCK)
th(FS) tw(SCK)

FSR

tsu(FS)
tsu(DR)

ADVANCE INFORMATION
DR

serial port transmit timing

tc(SCK)

tw(SCK) tr(SCK)

CLKX

td(CH-DX)
tf(SCK)
tw(SCK)
th(FS)
FSX
(Input,
TXM = 0)
tsu(FS) td(CH-DX)
td(FL-DX)

DX N=1 N = 8,16

td(CH-FS)
td(CH-FS)
FSX
(Output,
TXM = 1)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 47

 TMS32020

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

BIO timing

CLKOUT1

STRB

FETCH Branch Address FETCH Next Instruction

FETCH
A15-A0
BIOZ

PC = N PC = N + 1 PC = N + 2 PC = N + 3
or Branch Address
tsu(IN)

th(IN)
ADVANCE INFORMATION

BIO Valid

external flag timing

CLKOUT1

STRB

td(XF)

A15-A0 FETCH
Valid SXF/RXF Valid Valid

PC = N – 1 PC = N PC = N + 1 PC = N + 2

XF Valid

48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320C25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

BIO timing

CLKOUT1

STRB

FETCH Branch Address FETCH Next Instruction

FETCH
A15-A0
BIOZ

PC = N PC = N + 1 PC = N + 2
or Branch Address
tsu(IN)

th(IN)

ADVANCE INFORMATION
BIO Valid

external flag timing

CLKOUT1

STRB

td(XF)

A15-A0 FETCH
SXF/RXF Valid Valid Valid

PC = N PC = N + 1 PC = N + 2 PC = N + 3

XF Valid

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 TMS32020

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

HOLD timing (part A)

CLKOUT1

CLKOUT2

STRB

td(C2H-H)†

HOLD
ADVANCE INFORMATION

A15-A0 N N+1 N+2

PS, DS,
Valid Valid
or IS

R/W

tdis(C1L-A)

D15-D0 In In

tdis(AL-A)

HOLDA

td(C1L-AL)

N N+1 N/A N/A

FETCH
N–1 N Dummy Dead
EXECUTE

† HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur;
otherwise, a delay of one CLKOUT2 cycle will occur.

50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS32020

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

HOLD timing (part B)

CLKOUT1

CLKOUT2

ten(A-C1L)

STRB

td(C2H-H)†

HOLD

ADVANCE INFORMATION
A15-A0 Valid Valid

PS, DS,
or IS

R/W In In

td(HH-AH)

D15-D0

HOLDA N+2 N+3

N/A N /A N+2 N+3

FETCH
Dead Dead N+1 N+2
EXECUTE

† HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur;
otherwise, a delay of one CLKOUT2 cycle will occur.

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 TMS320C25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

HOLD timing (part A)

CLKOUT1

CLKOUT2

STRB

td(C2H-H)†

HOLD
ADVANCE INFORMATION

A15-A0 N N+1 N+2

PS, DS,
Valid Valid
or IS

R/W

tdis(C1L-A)

D15-D0 In In

tdis(AL-A)

HOLDA

td(C1L-AL)

N N+1 – –
FETCH
N–2 N –1 N –
EXECUTE

† HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur;
otherwise, a delay of one CLKOUT2 cycle will occur.

52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320C25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

HOLD timing (part B)

CLKOUT1

CLKOUT2

ten(A-C1L)

STRB

td(C2H-H)†

HOLD

ADVANCE INFORMATION
PS, DS, Valid
or IS

R/W

D15-D0 In

td(HH-AH)

HOLDA

A15-A0 N+2 N+2

– – – N+2
FETCH
– – – N+1
EXECUTE

† HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur;
otherwise, a delay of one CLKOUT2 cycle will occur.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 53

 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25

ICC vs f(CLKIN) and VCC ICC vs f(CLKIN) and VCC
Normal Operating Mode Powerdown Mode
170 80
160 TA = 25°C VCC = 5.50 V
VCC = 5.50 V
150 VCC = 5.25 V 70
140 VCC = 5.00 V VCC = 5.25 V
130 VCC = 4.75 V 60 VCC = 5.00 V
120 VCC = 4.50 V VCC = 4.75 V
ICC, mA

ICC, mA
110 50 VCC = 4.50 V
100
90 40
80
70 30
60
50 20
40
30 10
20
10 0
4 8 12 16 20 24 28 32 36 40 44 48 52 4 8 12 16 20 24 28 32 36 40 44 48 52
f(CLKIN), MHz f(CLKIN), MHz

TMS320C25FNL (PLCC) reflow soldering precautions

ADVANCE INFORMATION

Recent tests have identified an industry-wide problem experienced by surface mounted devices exposed to
reflow soldering temperatures. This problem involves a package cracking phenomenon sometimes
experienced by large (e.g., 68-lead) plastic leaded chip carrier (PLCC) packages during surface mount
manufacturing. This phenomenon occur if the TMS320C25FNL is exposed to uncontrolled levels of humidity
prior to reflow solder. This moisture can flash to steam during solder reflow, causing sufficient stress to crack
the package and compromise device integrity. If the TMS320C25FNL is being socketed, no special handling
precautions are required. In addition, once the device is soldered into the board, no special handling precautions
are required.
In order to minimize moisture absorption, TI ships the TMS320C25FNL in “dry pack” shipping bags with a RH
indicator card and moisture-absorbing desiccant. These moisture-barrier shipping bags will adequately block
moisture transmission to allow shelf storage for 12 months from date of seal when stored at less than 60%
relative humidity (RH) and less than 30°C. Devices may be stored outside the sealed bags indefinitely if stored
at less than 25% RH and 30°C.
Once the bag seal is broken, the devices should be stored at less than 60% RH and 30°C as well as reflow
soldered within two days of removal. In the event that either of the above conditions is not met, TI recommends
these devices be baked in a clean oven at 125°C and 10% maximum RH for 24 hours. This restores the devices
to their “dry packed” moisture level.

NOTE
Shipping tubes will not withstand the 125°C baking process. Devices should be transferred to a metal tray or tube be-
fore baking. Standard ESD precautions should be followed.

In addition, TI recommends that the reflow process not exceed two solder cycles and the temperature not
exceed 220°C.
If you have any additional questions or concerns, please contact your local TI representative.

54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320 SECOND-GENERATION
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

MECHANICAL DATA

68-pin GB grid array ceramic package (TMS32020, TMS320C25)

28,448 (1.120)
27,432 (1.080)

Thermal Resistance Characteristics 17,02 (0.670)

Nom
PARAMETER MAX UNIT

Junction-to-free-air
RθJA 36 °C/W
thermal resistance
28,448 (1.120)
Junction-to-case 27,432 (1.080)
RθJC 6 °C/W
thermal resistance
17,02
(0.670)
Nom

ADVANCE INFORMATION
4,953 (0.195)
2,032 (0.080)
1,397 (0.055)
Max

3,302 (0.130) 1,575 (0.062)

Dia
2,794 (0.110) 0,508 (0.020) 1,473 (0.058)
0,406 (0.016)

2,54
(0.100)
T.P. 2,54
L
(0.100)
K
T.P.
J
H
G
F
E
D
C 1,524 (0.060)
Nom
B 4 Places
A
1 2 3 4 5 6 7 8 9 10 11
1,27
(0.050)
Nom
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 55

 TMS320C25
TMS320C25-50
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50)

Seating
Plane
1,27 (0.050) T.P.
0,25 (0.010) R Max (see Note B)
3 Places

24,33 (0.956)
24,13 (0.950) 23,62 (0.930)
(see Note A) 23,11 (0.910)
(At Seating Plane)

25,27 (0.995)
25,02 (0.985)
ADVANCE INFORMATION

0,94 (0.037)
0,69 (0.027) R
1,22 (0.048)
× 45°
1,07 (0.042) 1,35 (0.053)
× 45°
24,33 (0.956) 1,19 (0.047)
24,13 (0.950) 2,79 (0.110)
(see Note A) 2,41 (0.095)
25,27 (0.995)
4,50 (0.177)
25,02 (0.985)
4,24 (0.167)

0,81 (0.032) 1,52 (0.060)

Thermal Resistance Characteristics
0,66 (0.026) Min

PARAMETER MAX UNIT

Junction-to-free-air
RθJA 46 °C/W 0,64 (0.025)
thermal resistance
Min
Junction-to-case
RθJC 11 °C/W
thermal resistance
0,51 (0.020)
0,36 (0.014)

Lead Detail
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTES: A. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by this dimension.
B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.

WARNING
When reflow soldering is required, refer to page 54 for special handling instructions.

56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

MECHANICAL DATA

68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only)

This hermetically-sealed chip carrier package consists of a ceramic base, ceramic cap, and a 68-lead frame.
Hermetic sealing is accomplished with glass. The FZ package is intended for both socket- or surface- mounting.
Having a Sn/Pb ratio of 60/40, the tin/lead-coated leads do not require special cleaning or processing
when being surface-mounted.

A 4,57 (0.180)
(see Note 2) 3,94 (0.155)
B 3,55 (0.140)
3,05 (0.120)
1,02 (0.040) × 45° 1,27 (0.050) Typ
(see Note 3)

ADVANCE INFORMATION
C
A
B (At Seating
(see Note 2)
0,81 (0.032) Plane)
0,66 (0.026)

0,51 (0.020)
0,64 (0.025) 0,36 (0.014)
(see Note 1) R
Max 1,016 (0.040) Min
3 Places Ref
Thermal Resistance Characteristics
3,05 (0.120)
PARAMETER MAX UNIT 2,29 (0.090)

Junction-to-free-air
RθJA 49 °C/W Seating Plane
thermal resistance
(see Note 4)
Junction-to-case
RθJC 8 °C/W
thermal resistance

JEDEC NO. OF A B C
OUTLINE TERMINALS MIN MAX MIN MAX MIN MAX
12,32 12,57 10,92 11,56 10,41 10,92
MO-087AA 28
(0.485) (0.465) (0.430) (0.455) (0.410) (0.430)
17,40 17,65 16,00 16,64 15,49 16,00
MO-087AB 44
(0.685) (0.695) (0.630) (0.655) (0.610) (0.630)
25,02 25,27 23,62 24,26 23,11 23,62
––– 68
(0.985) (0.995) (0.930) (0.955) (0.910) (0.930)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTES: 1. Glass is optional, and the diameter is dependent on device application.

2. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by dimension B.
3. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.
4. The lead contact points are within 0,15 (0.006) of being planar.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 57

 TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

programming the TMS320E25 EPROM cell

The TMS320E25 includes a 4K × 16-bit EPROM, implemented from an industry-standard EPROM cell, to
perform prototyping and early field testing and to achieve low-volume production. When used with a 4K-word
masked-ROM TMS320C25, the TMS320E25 yields a high-volume, low-cost production as a result of more
migration paths for data. An EPROM adapter socket (part # TMDX3270120), shown in Figure 8, is available to
provide 68-pin to 28-pin conversion for programming the TMS320E25.
ADVANCE INFORMATION

Figure 8. EPROM Adapter Socket

Key features of the EPROM cell include standard programming and verification. For security against copyright
violations, the EPROM cell features an internal protection mechanism to prevent proprietary code from being
read. The protection feature can be used to protect reading the EPROM contents. This section describes
erasure, fast programming and verification, and EPROM protection and verification.
fast programming and verification
The TMS320E25 EPROM cell is programmed using the same family and device codes as the TMS27C64
8K × 8-bit EPROM. The TMS27C64 EPROM series are ultraviolet-light erasable, electrically programmable
read-only memories, fabricated using HVCMOS technology. The TMS27C64 is pin-compatible with existing
28-pin ROMs and EPROMs. The TMS320E25, like the TMS27C64, operates from a single 5-V supply in the
read mode; however, a 12.5-V supply is needed for programming. All programming signals are TTL level. For
programming outside the system, existing EPROM programmers can be used. Locations may be programmed
singly, in blocks, or at random. When programmed in blocks, the data is loaded into the EPROM cell one byte
at a time, the high byte first and the low byte second.

58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

Figure 9 shows the wiring conversion to program the TMS320E25 using the 28-pin pinout of the TMS27C64.
The pin nomenclature table provides a description of the TMS27C64 pins. The code to be programmed into the
device should be serial mode. The TMS320E25 uses 13 address lines to address the 4K-word memory in byte
format.

RS
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
TMS27C64 10 60
D7 11 59
VCC
28 D6 12 58
27 PGM
D5 13 57
26 EPT
D4 14 56
25 A8
D3 15 55
24 A9
D2 16 54
23 A11
D1 17 53
22 G TMS320E25
D0 18 52 CLKIN

ADVANCE INFORMATION
A10 68-Pin (FZ)
21
19 51
20 E
20 50
19 Q8
21 49
18 Q7
E 22 48
17 Q6
23 47
16 Q5 EPT
24 46
15 Q4 VPP
25 45
A0
26 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
V SS

A10

A12

G
A1
A2
A3
A4
A5
A6
A7

A8
3.9 K A9

A11

PGM
V CC

GND
V PP
A12

Q1
Q2
Q3
A7
A6
A5
A4
A3
A2
A1
A0
TMS27C64

10

12
13
14
11
1
2
3
4
5
6
7
8
9

Pin Nomenclature (TMS320E25)

SIGNALS I/O DEFINITION
A12 (MSB) - A0 (LSB) I On-chip EPROM programming address lines
CLIN I Clock oscillator input
E I EPROM chip select
EPT I EPROM test mode select
G I EPROM read/verify select
GND I Ground
PGM I EPROM write/program select
Q8 (MSB) - Q1 (LSB) I/O Data lines for byte-wide programming of on-chip 8K bytes of EPROM
RS I Reset for initializing the device
VCC I 5-V power supply
VPP I 12.5-V power supply

Figure 9. TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 59

 TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

Table 5 shows the programming levels required for programming, verifying and reading the EPROM cell. The
paragraphs following the table describe the function of each programming level.

Table 5. TMS320E25 Programming Mode Levels

SIGNAL TMS320E25 TMS27C64 PROGRAM PROGRAM OUTPUT
PROGRAM READ
NAME † PIN PIN VERIFY INHIBIT DISABLE
E 22 20 VIL VIL VIH VIL VIL
G 42 22 VIH PULSE X PULSE VIH
PGM 41 27 PULSE VIH X VIH VIH
VPP 25 1 VPP VPP VPP VCC VCC
VCC 61,35 28 VCC + 1 VCC + 1 VCC + 1 VCC VCC
VSS 27,44,10 14 VSS VSS VSS VSS VSS
CLKIN 52 14 VSS VSS VSS VSS VSS
RS 65 14 VSS VSS VSS VSS VSS
EPT 24 26 VSS VSS VSS VSS VSS
Q1-Q8 18-11 11-13,15-19 DIN QOUT HI-Z QOUT HI-Z
ADVANCE INFORMATION

A12-A10 40-38 2,23,21, ADDR ADDR X ADDR X

A9-A7 37,36,34 24,25,3 ADDR ADDR X ADDR X
A6 33 4 ADDR ADDR X ADDR X
A5 32 5 ADDR ADDR X ADDR X
A4 31 3 ADDR ADDR X ADDR X
A3-A0 30-28,26 7-10 ADDR ADDR X ADDR X
† In accordance with TMS27C64.
LEGEND;
VIH = TTL high level; VIL = TTL low level; ADDR = byte address bit
VPP = 12.5 V ± 0.5 V; VCC = 5 ± 0.25 V; X = don’t care
PULSE = low-going TTL level pulse; DIN = byte to be programmed at ADDR
QOUT = byte stored at ADDR; RBIT = ROM protect bit.
erasure
Before programming, the device is erased by exposing the chip through the transparent lid to high-intensity
ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV-intensity ×
exposure-time) is 15 W•s/cm2. A typical 12 mW/cm2, filterless UV lamp will erase the device in 21 minutes. The
lamp should be located approximately 2.5 cm above the chip during erasure. After erasure, all bits are in the
high state. Note that normal ambient light contains the correct wavelength for erasure. Therefore, when using
the TMS320E25, the window should be covered with an opaque label.
fast programming
After erasure (all memory bits in the cell are logic one), logic zeroes are programmed into the desired locations.
The fast programming algorithm, shown in Figure 10, is normally used to program the entire EPROM contents,
although individual locations may be programmed separately. A programmed logic zero can be erased only by
ultraviolet light. Data is presented in parallel (eight bits) on pins Q8-Q1. Once addresses and data are stable,
PGM is pulsed. The programming mode is achieved when VPP = 12.5 V, PGM = VIL, VCC = 6 V, G = VIH, and
E = VIL More than one TMS320E25 can be programmed when the devices are connected in parallel. Locations
can be programmed in any order.
Programming uses two types of programming pulses: prime and final. The length of the prime pulse is 1 ms.
After each prime pulse, the byte being programmed is verified. If correct data is read, the final programming
pulse is applied; if correct data is not read, an additional 1-ms prime pulse is applied up to a maximum of 15
times. The final programming pulse is 4 ms times the number of prime programming pulses applied. This
sequence of programming and verification is performed at VCC = 6 V, and VPP = 12.5 V. When the full fast
programming routine is complete, all bits are verified with VCC = VPP = 5 V.

60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

program verify
Programmed bits may be verified with VPP = 12.5 V when G = VIL, E = VIL, and PGM = VIH. Figure 11 shows
the timing for the program and verify operation.
Start

Address = First
Location

VCC = 6 ± 0.25 V
VPP = 12.5 V ± 0.25
V

X=0

Program One

ADVANCE INFORMATION
1-ms Pulse

Increment X

No

Yes Fail
Verify
X = 25?
One
Byte
Pass

Program One
Device Pulse of
Failed 3X-ms Duration

No
Last Increment
Address? Address

Yes

VCC = VPP = 5 V ± 0.25 V

Fail Compare All

Bytes to Original
Data

Pass

Device
Passed

Figure 10. Fast Programming Flowchart

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 61

 TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

Program
Verify

VIH
A12-A0 Address Stable Address N + 1
VIL

VIH/VOH
Q8-Q1 Data In Stable HI-Z Data Out Valid
VIL/VOL

VPP
VPP
VCC

VCC + 1
VCC
VCC
ADVANCE INFORMATION

VIH
E
VIL

VIH
PGM
VIL

VIH
G
VIL

Figure 11. Fast Programming Timing

program inhibit
Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.
read
The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect
bit) has not been programmed. The read is accomplished by setting E to zero and pulsing G low. The contents
of the EPROM location selected by the value on the address inputs appear on Q8-Q1.
output disable
During the EPROM programming process, the EPROM data outputs may be disabled, if desired, by establishing
the output disable state. This state is selected by setting the G and PGM pins high. While output disable is
selected, Q8-Q1 are placed in the high-impedance state.
ROM protection and verification
This section describes the code protection feature included in the EPROM cell, which protects code against
copyright violations. Table 6 shows the programming levels required for protecting and verifying the EPROM.
The paragraphs following the table describe the protect and verify functions.

62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

Table 6. TMS320E25 Protect and Verify EPROM Mode Levels

SIGNAL † TMS320E25 PIN TMS27C64 PIN ROM PROTECT PROTECT VERIFY
E 22 20 VIH VIL
G 42 22 VIH VIL
PGM 41 27 VIH VIH
VPP 25 1 VPP VCC
VCC 61,35 28 VCC + 1 VCC
VSS 10, 27, 44 14 VSS VSS
CLKIN 52 14 VSS VSS
RS 65 14 VSS VSS
EPT 24 26 VPP VPP
Q8-Q1 18-11 11-13, 15-19 Q8 = PULSE Q8 = RBIT
A12-A10 40-38 2, 23, 21, X X
A9-A7 37, 36, 34 24, 25, 3 X X
A6 33 4 X VIL

ADVANCE INFORMATION
A5 32 5 X X
A4 31 6 VIH X
A3-A0 30-28, 26 7-10 X X
† In accordance with TMS27C64.
LEGEND;
VIH = TTL high level; VIL = TTL low level; VCC = 5 V ± 0.25 V
VPP = 12.5 V ± 0.5 V; X = don’t care
PULSE = low-going TTL level pulse; RBIT = ROM protect bit.

EPROM protect
The EPROM protect facility is used to completely disable reading of the EPROM contents to guarantee security
of propietary algorithms. This facility is implemented through a unique EPROM cell called the RBIT (EPROM
protect bit) cell. Once the contents to be protected are programmed into the EPROM, the RBIT is programmed,
disabling access to the EPROM contents and disabling the microprocessor mode on the device. Once
programmed, the RBIT can be cleared only by erasing the entire EPROM array with ultraviolet light, thereby
maintaining security of the propietary algorithm. Programming the RBIT is accomplished using the EPROM
protect cycle, which consists of setting the E, G, PGM, and A4 pins high, VPP and EPT to 2.5 V ± 0.5 V, and
pulsing Q8 low. The complete sequence of operations involved in programming the RBIT is shown in the
flowchart of Figure 12. The required setups in the figure are detailed in Table 6.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 63

 TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

Start

Program One
X=0 Pulse of 3X-ms
Duration

EPROM
Protect Protect
Setup Verify
Setup

Program One
1-ms Pulse
Device Verify Device
Failed RBIT Passed
X=X+1

Yes
X = 25?
ADVANCE INFORMATION

No

Protect
Verify
Setup

Fail
Verify
RBIT

Pass

EPROM
Protect
Setup

Figure 12. EPROM Protect Flowchart

protect verify
Protect verify is used following the EPROM protect to verify correct programming of the RBIT (see Figure 12).
When using protect verify, Q8 outputs the state of the RBIT. When RBIT = 1, the EPROM is unprotected; when
RBIT = 0, the EPROM is protected. The EPROM protect and verify timings are shown in Figure 13.

64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

Protect
Verify
VIH
A4
VIL

VPP
VPP
VCC

VCC + 1
VCC
VCC

VIH
E

ADVANCE INFORMATION
VIL

VIH
PGM
VIL

VIH
G
VIL

VIH/VOH
Q8 HI-Z HI-Z HI-Z
VIL/VOL

VPP
EPT
VSS

VIH
A6
VIL

Figure 13. EPROM Protect Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 65

 TMS320 SECOND-GENERATION INDEX
DEVICES
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990
ADVANCE INFORMATION

66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

 NIL
NIL
NIL
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 microcomputer/microprocessor mode

adapter socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . 10 multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 operation conditions
TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 21
BIT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TMS320C25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TMS320C25-50 . . . . . . . . . . . . . . . . . . . . . . . . . 34
Bulletin board Service . . . . . . . . . . . . . . . . . . . . . . 18 TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . 27, 33
overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
clock
TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 overview
TMS320C25/E25 . . . . . . . . . . . . . . . . . . . . . 28, 29 TMS320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
TMS320C25-50 . . . . . . . . . . . . . . . . . . . . . . 35, 36 specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
development support . . . . . . . . . . . . . . . . . . . . 18, 19
direct addressing . . . . . . . . . . . . . . . . . . . . . . . 10, 17 pin nomenclature
DMA documentation support . . . . . . . . . . . . . . . . 20 TMS32020/C25/C25-50 . . . . . . . . . . . . . . . . . . . 2
TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
EPROM protection/verification . . . . . . . . . . . . 58-65
external interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pinouts
TMS32020/C25/C25-50 . . . . . . . . . . . . . . . . . . . 1
flowcharts TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
EPROM protect . . . . . . . . . . . . . . . . . . . . . . . . . 63 programming levels for EPROM . . . . . . . . . . 58-65
fast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60, 61
repeat feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
hotline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 reflow soldering precaution . . . . . . . . . . . . . . . . . . 54
immediate addressing . . . . . . . . . . . . . . . . . . . . . . 10
serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 9
indirect addressing . . . . . . . . . . . . . . . . . . . . . . 10, 17
instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 specification overview . . . . . . . . . . . . . . . . . . . . . . 20
introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
supply current characteristics . . . . . . . . . . . . . . . . 54
key features switching characteristics
TMS320 family . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TMS32020 . . . . . . . . . . . . . . . . . . . . . . . 21, 23-26
TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TMS320C25/E25 . . . . . . . . . . . . . . . . . . 27, 28-33
TMS320C25/C25-50/E25 . . . . . . . . . . . . . . . . . . 4 TMS320C25-50 . . . . . . . . . . . . . . . . . . . 34, 35-40

mechanical data timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 timing diagrams . . . . . . . . . . . . . . . . . . 41-53, 62, 65
TMS320C25 . . . . . . . . . . . . . . . . . . . . . . . . . 55, 56 TMS320 Second-Generation . . . . . . . . . . . 41-47
TMS320C25-50 . . . . . . . . . . . . . . . . . . . . . . . . . 56 TMS32020 . . . . . . . . . . . . . . . . . . . 46, 48, 50, 51
TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 TMS320C25/E25 . . . . . . . . . . . . . . 46, 49, 52, 53
memory TMS3220 product notification . . . . . . . . . . . . . 17
addressing modes . . . . . . . . . . . . . . . . . . . . 10, 17
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 67

 PACKAGE OPTION ADDENDUM
www.ti.com 19-May-2005

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TMS320C25FNA NRND PLCC FN 68 18 TBD CU SNPB Level-3-220C-168HR
TMS320C25FNAR NRND PLCC FN 68 250 TBD CU SNPB Level-3-220C-168HR
TMS320C25FNL NRND PLCC FN 68 18 TBD CU SNPB Level-3-220C-168HR
TMS320C25FNLR NRND PLCC FN 68 250 TBD CU SNPB Level-3-220C-168HR
TMS320C25FNLW OBSOLETE PLCC FN 68 TBD CU SNPB Level-3-220C-168HR
TMS320C25GBA NRND CPGA GB 68 21 TBD AU Level-NC-NC-NC
TMS320C25GBL NRND CPGA GB 68 21 TBD AU Level-NC-NC-NC
TMS320C25PHL NRND QFP PH 80 66 TBD A42 SNPB Level-4-220C-72HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1
 IMPORTANT NOTICE

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