Microprocessor

Architecture
The Pentium family of processors, which has its roots in the
Intel486(TM) processor, uses the Intel486 instruction set
(with a few additional instructions). The term ''Pentium
processor'' refers to a family of microprocessors that share a
common architecture and instruction set. The first Pentium
processors (the P5 variety) were introduced in 1993. This
5.0-V processor was fabricated in 0.8-micron bipolar
complementary metal oxide semiconductor (BiCMOS)
technology. The P5 processor runs at a clock frequency of
either 60 or 66 MHz and has 3.1 million transistors.

The next version of the Pentium processor family, the P54C

processor, was introduced in 1994. The P54C processors are
fabricated in 3.3-V, 0.6-micron BiCMOS technology. The P54C
processor also has System Management Mode (SMM) for
advanced power management

The Intel Pentium processor, like its predecessor the Intel486 microprocessor, is fully software compatible with the installed base of
over 100 million compatible Intel architecture systems. In addition, the Intel Pentium processor provides new levels of performance to
new and existing software through a reimplementation of the Intel 32-bit instruction set architecture using the latest, most advanced,
design techniques. Optimized, dual execution units provide one-clock execution for "core" instructions, while advanced technology,
such as superscalar architecture, branch prediction, and execution pipelining, enables multiple instructions to execute in parallel with
high efficiency. Separate code and data caches combined with wide 128-bit and 256-bit internal data paths and a 64-bit, burstable,
external bus allow these performance levels to be sustained in cost-effective systems. The application of this advanced technology in
the Intel Pentium processor brings "state of the art" performance and capability to existing Intel architecture software as well as new
and advanced applications.

The Pentium processor has two primary operating modes and a "system management mode."

The operating mode determines which instructions and architectural features are accessible.

These modes are:

 Protected Mode

This is the native state of the microprocessor. In this mode all instructions and architectural features are available, providing
the highest performance and capability. This is the recommended mode that all new applications and operating systems should
target. Among the capabilities of protected mode is the ability
 to directly execute "real-address mode" 8086 software in a protected, multi-tasking
environment. This feature is known as Virtual-8086 "mode" (or "V86 mode"). Virtual-8086
"mode" however, is not actually a processor "mode," it is in fact an attribute which can
be enabled for any task (with appropriate software) while in protected mode.

 Real-Address Mode (also called "real mode")

This mode provides the programming environment of the Intel 8086 processor, with
a few extensions (such as the ability to break out of this mode). Reset initialization
places the processor in real mode where, with a single instruction, it can switch to
protected mode.

 System Management Mode

The Pentium microprocessor also provides support for System Management Mode (SMM). SMM is a standard architectural
feature unique to all new Intel microprocessors, beginning with the Intel386 SL processor, which provides an operating-system
and application independent and transparent mechanism to implement system power management and OEM differentiation
features. SMM is entered through activation of an external interrupt pin (SMI#), which switches the CPU to a separate address
space while saving the entire context of the CPU. SMM-specific code may then be executed transparently. The operation is
reversed upon returning.

Advanced Features

The Pentium P54C processor is the product of a marriage between the Pentium processor's architecture and Intel's 0.6-micron, 3.3-V
BiCMOS process The Pentium processor achieves higher performance than the fastest Intel486 processor by making use of the following
advanced technologies.

 Superscalar Execution: The Intel486 processor can execute only one instruction at a time. With superscalar execution, the
Pentium processor can sometimes execute two instructions simultaneously.

 Pipeline Architecture: Like the Intel486 processor, the Pentium processor executes instructions in five stages. This staging, or
pipelining, allows the processor to overlap multiple instructions so that it takes less time to execute two instructions in a row.
Because of its superscalar architecture, the Pentium processor has two independent processor pipelines.

 Branch Target Buffer: The Pentium processor fetches the branch target instruction before it executes the branch instruction.

 Dual 8-KB On-Chip Caches: The Pentium processor has two separate 8-kilobyte (KB) caches on chip--one for instructions and
one for data--which allows the Pentium processor to fetch data and instructions from the cache simultaneously.

 Write-Back Cache: When data is modified; only the data in the cache is changed. Memory data is changed only when the
Pentium processor replaces the modified data in the cache with a different set of data

 64-Bit Bus: With its 64-bit-wide external data bus (in contrast to the Intel486 processor's 32-bit- wide external bus) the
Pentium processor can handle up to twice the data load of the Intel486 processor at the same clock frequency.

 Instruction Optimization: The Pentium processor has been optimized to run critical instructions in fewer clock cycles than the
Intel486 processor.

 Floating-Point Optimization: The Pentium processor executes individual instructions faster through execution pipelining, which
allows multiple floating-point instructions to be executed at the same time.

 Pentium Extensions: The Pentium processor has fewer instruction set extensions than the Intel486 processors. The Pentium
processor also has a set of extensions for multiprocessor (MP) operation. This makes a computer with multiple Pentium
processors possible.
A Pentium system, with its wide, fast buses, advanced write-back cache/memory subsystem, and powerful processor, will deliver more
power for today's software applications, and also optimize the performance of advanced 32-bit operating systems (such as Windows 95)
and 32-bit software applications.

Figure 1 shows a block diagram of the Pentium design.

The most important enhancements over the 486 are the separate instruction and data caches, the dual integer pipelines (the U-pipeline
and the V-pipeline, as Intel calls them), branch prediction using the branch target buffer (BTB), the pipelined floating-point unit, and
the 64-bit external data bus. Even-parity checking is implemented for the data bus and the internal RAM arrays (caches and TLBs).

As for new functions, there are only a few; nearly all the enhancements in Pentium are included to improve performance, and there are
only a handful of new instructions. Pentium is the first high-performance micro-processor to include a system management mode like
those found on power-miserly processors for notebooks and other battery-based applications; Intel is holding to its promise to include
SMM on all new CPUs. Pentium uses about 3 million transistors on a huge 294 mm 2 (456k mils 2 ). The caches plus TLBs use only about
30% of the die. At about 17 mm on a side, Pentium is one of the largest microprocessors ever fabricated and probably pushes Intel’s
production equipment to its limits. The integer data path is in the middle, while the floating-point data path is on the side opposite the
data cache. In contrast to other superscalar designs, such as SuperSPARC, Pentium’s integer data path is actually bigger than its FP data
path. This is an indication of the extra logic associated with complex instruction support. Intel estimates about 30% of the transistors
were devoted to compatibility with the x86 architecture. Much of this overhead is probably in the microcode ROM, instruction decode
and control unit, and the adders in the two address generators, but there are other effects of the complex instruction set. For example,
the higher frequency of memory references in x86 programs compared to RISC code led to the implementation of the dual-ac.

Register set

The purpose of the Register is to hold temporary results, and control the execution of the program. General-purpose registers in
Pentium are EAX, ECX, EDX, EBX, ESP, EBP,ESI, or EDI.

The 32-bit registers are named with prefix E, EAX, etc, and the least 16 bits 0-15 of these registers can be accessed with names such as
AX, SI Similarly the lower eight bits (0-7) can be accessed with names such as AL & BL. The higher eight bits (8-15) with names such as
AH & BH. The instruction pointer EAP known as program counter(PC) in 8-bit microprocessor, is a 32-bit register to handle 32-bit
memory addresses, and the lower 16 bit segment IP is used for 16-bi memory address.

The flag register is a 32-bit register , however 14-bits are being used at present for 13 different tasks; these flags are upward
compatible with those of the 8086 and 80286. The comparison of the available flags in 16-bit and 32-bit microprocessor is may provide
some clues related to capabilities of these processors. The 8086 has 9 flags, the 80286 has 11 flags, and the 80286 has 13 flags. All of
these flag registers include 6 flags related to data conditions (sign, zero, carry, auxiliary, carry , overflow, and parity) and three flags
related to machine operations.(interrupts, Single-step and Strings). The 80286 has two additional : I/O Privilege and Nested Task. The
I/O Privilege uses two bits in protected mode to determine which I/O instructions can be used, and the nested task is used to show a
link between two tasks.

The processor also includes control registers and system address registers , debug and test registers for system and debugging
operations.

Addressing mode & Types of instructions

Instruction set is divided into 9 categories of operations and has 11 addressing modes. In addition to commonly available instructions in
a 8 bit microprocessor and this set includes operations such as bit manipulation and string operations, high level language support and
operating system support. An instruction may have 0-3 operands and the operand can be 8, 16, or 32- bits long. The 80386 handles
various types of data such as Single bit , string of bits , signed and unsigned 8-, 16-, 32- and 64- bit data, ASCII character and BCD
numbers.

High level language support group includes instructions such as ENTER and LEAVE. The ENTER instruction is used to ENTER from a high
level language and it assigns memory location on the stack for the routine being entered and manages the stack. On the other hand the
LEAVE generates a return procedure for a high level language. The operating system support group includes several instructions , such
as APRL.( Adjust Requested Privilege Level) and the VERR/W (Verify Segment for Reading or Writing). The APRL is designed to prevent
the operating system from gaining access to routines with a higher priority level and the instructions VERR/W verify whether the
specified memory address can be reached from the current privilege level.

Refference:

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