DIGITAL CIRCUITS AND STYSTEMS

LAB FILE

SUBMITTED BY:

ROLL NO.

LAB SUPERVISOR:MR. PRATEEK SHUKLA

BINARY TO GRAY CODE CONVERTER

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bintogray11 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : out STD_LOGIC_VECTOR (3 downto 0));
end bintogray11;

architecture Behavioral of bintogray11 is

begin
b(3)<=a(3);
b(2)<= a(3) xor a(2);
b(1)<=a(2) xor a(1);
b(0)<=a(1) xor a(0);
end Behavioral;
FSM TO CHECK DIVISIBILITTY BY 5

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fsm is
Port ( clk,reset,w : in STD_LOGIC;
z : out STD_LOGIC);
end fsm;
architecture Behavioral of fsm is
type state_type is (a,b,c,d,e,f);
signal y : state_type;
begin
process(clk,reset)
begin
if (reset ='0') then
y <= f;
elsif(clk'event and clk='1') then
case y is
when f=>
if w='0' then
y<=a;
 else y<=b;
end if;
when a=>
if w='0' then
y<=a;
else y<=b;
end if;
when b=>
if w='0' then
y<=c;
else y<=d;
end if;
when c=>
if w='0' then
y<=e;
else y<=a;
end if;
when d=>
if w='0' then
y<=b;
else y<=c;
end if;
when e=>
if w='0' then
y<=d;
else y<=e;
end if;
end case;
end if;
end process;
z<='1' when y=a else '0';
end Behavioral;
TRAFFIC LIGHT CONTROLLER

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity traffic is
Port ( clk : in STD_LOGIC;
sa : in STD_LOGIC;
sb : in STD_LOGIC;
ra : out STD_LOGIC;
rb : out STD_LOGIC;
ya : out STD_LOGIC;
yb : out STD_LOGIC;
ga : out STD_LOGIC;
gb : out STD_LOGIC);
end traffic;

architecture Behavioral of traffic is

signal state, nextstate: integer range 0 to 12;
begin
process(state, Sa, Sb)
begin
Ra<='0'; Rb<='0'; Ga<='0'; Gb<='0'; Ya<='0'; Yb<='0';
case state is
when 0 to 4 => Ga<='1'; Rb<='1'; Ra<='0'; Ya<='0'; Yb<='0'; Gb<='0';
nextstate<=state+1;
when 5=> Ga<='1'; Rb<='1';Ra<='0'; Ya<='0'; Yb<='0'; Gb<='0';
if Sb='1' then nextstate<=6; end if;
when 6=> Ya<='1'; Rb<='1'; Ga<='0'; Ra<='0'; Yb<='0'; Gb<='0'; nextstate<=7;
when 7 to 10 =>Ra<='1'; Gb<='1'; Rb<='0'; Yb<='0'; Ya<='0'; Ga<='0';
nextstate<=state+1;
when 11 => Ra<='1'; Gb<='1'; Rb<='0'; Yb<='0'; Ya<='0'; Ga<='0';
if (Sa='1' or Sb='0') then nextstate<=12; end if;
when 12 => Ra<='1'; Yb<='1'; Ga<='0'; Rb<='0'; Gb<='0'; Ya<='0'; nextstate<=0;
end case;
end process;

process(clk)
begin
if (clk='1' and clk' event) then
state<=nextstate;
end if;
end process;
end Behavioral;
SERIAL SHIFT REGISTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity registerser1 is
Port ( inp : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
outt : out STD_LOGIC);
end registerser1;

architecture Behavioral of registerser1 is

component ffsync
Port ( clk,d,resetn : in STD_LOGIC;
q : out STD_LOGIC;
q1 : out STD_LOGIC);
end component;
signal c: std_logic_vector(4 downto 0);
begin
st1: ffsync port map (clk,inp,reset,c(0));
st2: ffsync port map (clk,c(0),reset,c(1));
st3: ffsync port map (clk,c(1),reset,c(2));
st4: ffsync port map (clk,c(2),reset,c(3));
st5: ffsync port map (clk,c(3),reset,outt);
end Behavioral;

D FLIP FLOP WITH SYNCHRONOUS RESET

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ffsync is
Port ( clk : in STD_LOGIC;
d : in STD_LOGIC;
resetn : in STD_LOGIC;
q : out STD_LOGIC;
q1 : out STD_LOGIC);
end ffsync;

architecture Behavioral of ffsync is

begin
process(clk)
begin
if (clk'event and clk='1') then
if (resetn='0') then
q<='0';
q1<='1';
else
q<=d;
q1<= not d;
end if;
end if;
end process;
end Behavioral;
D FLIP FLOP WITH ASYNCHRONOUS RESET

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ff1 is
Port ( clk : in STD_LOGIC;
reset: in std_logic;
d : in STD_LOGIC;
q : out STD_LOGIC;
q1 : out STD_LOGIC);
end ff1;

architecture Behavioral of ff1 is

begin
process(clk,reset)
begin
if(reset='0')
then q<='0';q1<='1';
elsif(clk'event and clk='1')then
q<=d;
q1<= not d;
end if;
end process;
end Behavioral;
BINARY COUNTER

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
Port ( reset : in STD_LOGIC;
e : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_vector(3 downto 0));
end counter;

architecture Behavioral of counter is

signal count : std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if reset='0' then
count<="0000";
elsif(clk'event and clk='1') then
if e ='1' then
count <= count+1;
end if;
end if;
end process;
q <= count;
end Behavioral;
BCD COUNTER

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
Port ( reset : in STD_LOGIC;
e : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_vector(3 downto 0));
end counter;

architecture Behavioral of counter is

signal count : std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if reset='0' then
count<="0000";
elsif(clk'event and clk='1') then
if e ='1' then
count <= count+1;
if count="1010" then
count<="0000";
end if;
end if;
end if;
end process;
q <= count;
end Behavioral;
2 TO 4 DECODER

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;entity decoder_en is
entity decoder is
Port ( en : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
q0 : out STD_LOGIC;
q1 : out STD_LOGIC;
q2 : out STD_LOGIC;
q3 : out STD_LOGIC);
end decoder;

architecture Behavioral of decoder is

begin
q0<=(not a) and (not b) and (not en);
q1<=(a)and (not b) and (not en);
q2<=(not a)and (b) and (not en);
q3<=(a)and (b) and (not en);

end Behavioral;