Lab 1 - ALU (Arithmetic/Logical Unit)

• Task: design an ALU for a P37X CPU

CSE372 • Ten operations:

Digital Systems Organization and Design •
•
Addition, subtraction
Multiplication
Lab • And, or, not, xor
• Shift left, logical shift right, arithmetic shift right

Prof. Milo Martin • The different adder implementations

• Ripple-carry
Unit 1: Synthesizable Verilog • Two carry-select adders

• Pay close attention in CSE371 lectures on this!

CSE 372 (Martin): Synthesizable Verilog 1 CSE 372 (Martin): Synthesizable Verilog 2

Hardware Description Languages (HDLs) Hardware Description Languages (HDLs)

• Textural representation of a digital logic design • Write “code” to describe hardware
• Specify wires, gates, modules
• Easier to edit and revise than schematics
• Also hierarchical
• However, you still need to think in terms of schematics (pictures)
• Pro: easier to edit and create; Con: more abstract
• HDLs are not “programming languages” module mux2to1(S, A, B, O);
• No, really. Even if they look like it, they are not. input S, A, B;
• One of the most difficult conceptual leaps of this course output O; S
wire S_, AnS_, BnS;
A
O
• Similar development chain
not (S_, S); B
• Compiler: source code ! assembly code ! binary machine code
and (AnS_, A, S_);
• Synthesis tool: HDL source ! gate-level specification ! hardware
and (BnS, B, S);
or (O, AnS_, BnS);
endmodule
CSE 372 (Martin): Synthesizable Verilog 3 CSE 372 (Martin): Synthesizable Verilog 4
Verilog HDL HDL History
• Verilog • 1970s: First HDLs
• One of two commonly-used HDLs • Late 1970s: VHDL
• Verilog is a (surprisingly) big language • VHDL = VHSIC HDL = Very High Speed Integrated Circuit HDL
• Lots of features for synthesis and simulation of hardware • VHDL inspired by programming languages of the day (Ada)
• 1980s:
• We’re going to learn a focused subset of Verilog • Verilog first introduced
• Verilog inspired by the C programming language
• Focus on synthesizable constructs
• VHDL standardized
• Focus on avoiding subtle synthesis errors
• 1990s:
• Use as an educational tool
• Verilog standardized (Verilog-1995 standard)
• Initially restrict some features to “build up” primitives
• Rule: if you haven’t seen it in lecture, you can’t use it
• 2000s:
• Continued evolution (Verilog-2001 standard)
• Ask me if you have any questions
• Both VHDL and Verilog evolving, still in use today

CSE 372 (Martin): Synthesizable Verilog 5 CSE 372 (Martin): Synthesizable Verilog 6

Two Roles of HDL and Related Tools Synthesis vs Simulation

• #1: Specifying digital logic • HDLs have features for both synthesis and simulation
• Specify the logic that appears in final design • E.g., simulation-only operations for error messages, reading files
• Either • Obviously, these can be simulated, but not synthesized into circuits
• Translated automatically (called synthesis) or • Also has constructs such as for-loops, while-loops, etc.
• Optimized manually (automatically checked for equivalence) • These are either un-synthesizable or (worse) synthesize poorly

• #2: Simulating and testing a design • Trends: a moving target

• High-speed simulation is crucial for large designs • Good: better synthesis tools for higher-level constructs
• Many HDL interpreters optimized for speed • Bad: harder than ever to know what is synthesizable or not
• Testbench: code to test design, but not part of final design

CSE 372 (Martin): Synthesizable Verilog 7 CSE 372 (Martin): Synthesizable Verilog 8
Structural vs Behavioral HDL Constructs Verilog Structural Example
Structural
• Structural constructs specify actual hardware structures module mux2to1(S, A, B, Out);
• Low-level, direct correspondence to hardware S
input S, A, B;
• Primitive gates (e.g., and, or, not) output Out; A
• Hierarchical structures via modules wire S_, AnS_, BnS; Out
• Analogous to programming software in assembly not (S_, S); B

• “Behavioral” constructs specify an operation on bits and (AnS_, A, S_);

and (BnS, B, S);
• High-level, more abstract
or (Out, AnS_, BnS);
• Specified via equations, e.g., out = (a & b) | c
endmodule
• Statements, e.g., if-then-else
• Analogous to programming software in C
• Not all behavioral constructs are synthesizable
• Even higher-level, synthesize poorly or not at all (e.g., loops)
• Perhaps analogous to programming in Perl, Python, Matlab, SQL

CSE 372 (Martin): Synthesizable Verilog 9 CSE 372 (Martin): Synthesizable Verilog 10

Verilog Structural Primitives Verilog “Behavioral” Example

“Behavioral” (Synthesizable)
• Gate-level module mux2to1(S, A, B, Out);
• One-output boolean operators: and, or, xor, nand, nor, xnor S
input S, A, B;
• E.g., C = A+B
output Out; A
or (C, A, B); Out
wire S_, AnS_, BnS;
• E.g., C= A+B+D B
assign S_ = ~S;
or (C, A, B, D);
assign AnS_ = A & S_;
• One-input operators: not, buf
assign BnS =B & S;
• E.g., A = not Z
assign Out = AnS_ | BnS;
not (A, Z);
endmodule
• E.g., A = not Z, B = not Z
not (A, B, Z);
• Buf just replicates signals (can increase drive strength)
• Transistor-level primitives too
• Will not use

CSE 372 (Martin): Synthesizable Verilog 11 CSE 372 (Martin): Synthesizable Verilog 12
Wire Assignment Verilog “Behavioral” Example
“Behavioral” (Synthesizable)
• Wire assignment: “continuous assignment” module mux2to1(S, A, B, Out);
• Connect combinational logic block or other wire to wire input S
input S, A, B;
• Order of statements not important, executed totally in parallel output Out; A
• When right-hand-side changes, it is re-evaluated and re-assigned wire S_, AnS_, BnS; Out
• Designated by the keyword assign assign S_ = ~S; B
wire c; assign AnS_ = A & S_;
assign c = a | b; assign BnS =B & S;
assign Out = AnS_ | BnS;
endmodule
• Can be combined with declaration
wire c = a | b; // same thing module mux2to1(S, A, B, Out);
• Basic operators input S, A, B;
• Not: ~ Or: | And: & Xor: ^ output Out;
assign Out = (~S & A) | (S & B);
• Can be combined: (a & b) | (c ^ d)
endmodule

CSE 372 (Martin): Synthesizable Verilog 13 CSE 372 (Martin): Synthesizable Verilog 14

Wires are not C-like Variables Aside: Non-binary Hardware Values

• Order of assignment doesn’t matter • A hardware signal can have any of four values
0, 1
X: don’t know, don’t care
Z: high-impedance (no current flowing)
• Can’t reuse a wire • Uses for “x”
assign temp = a & b; • Tells synthesis tool you don’t care
assign c = temp; • Synthesis tool makes the most convenient circuit (fast, small)
assign temp = a | b; • Use with care, leads to synthesis dependent operation
assign d = temp; • Uses for “z”
• Tri-state devices drive a zero, one, or “off” (z)
• Many tri-states drive the same wire, all but one must be “z”
• Can’t assign a wire multiple values • Makes some circuits very fast
• Actually, you can; but don’t do it. • Example: multiplexer
• This is why Verilog allows multiple assignments to same wire

CSE 372 (Martin): Synthesizable Verilog 15 CSE 372 (Martin): Synthesizable Verilog 16
Vectors of Wires Vector Constants
• Wire vectors:
wire [7:0] W1; // 8 bits, w1[7] is MSB • Constants:
wire [0:7] W2; // 8 bits, w2[0] is MSB • assign x = 3’b011
• Also called “arrays” or “busses” • The “3” is the number of bits
• The “b” means “binary” - “h” for hex, “d” for decimal
• Operations • The “011” are the digits (in binary in this case)
• Bit select: W1[3]
• Range select: W1[3:2]
• Concatenate: {<expr>[,<expr>]*}
vec = {x, y, z};
{carry, sum} = vec[0:1];
• e.g., swap high and low-order bytes of 16-bit vector
wire [15:0] w1, w2;
assign w2 = {w1[7:0], w1[15:8]}

CSE 372 (Martin): Synthesizable Verilog 17 CSE 372 (Martin): Synthesizable Verilog 18

Repeated Signals Operator List

• Concatenation • Operators similar to C or Java
assign vec = {x, y, z}; • On wires:
• & (and), | (or), ~ (not), ^ (xor)
• Can also repeat a signal n times
• On vectors:
assign vec = {16{x}}; // 16 copies of x
• &, |, ~, ^ (bit-wise operation on all wires in vector)
• Example uses (what does this do?): • E.g., assign vec1 = vec2 & vec3;
wire [7:0] out; • &, |, ^ (reduction on the vector)
• E.g., assign wire1 = | vec1;
wire [3:0] A;
• Even ==, != (comparisons) +, -, * (arithmetic), <<, >> (shifts)
assign out = {{4{0}}, A[3:0]}; • But you can’t use these, yet. Can you guess why?
• What about this? • Note: use with care, assume unsigned numbers
assign out = {{4{A[3]}}, A[3:0]}; • Verilog 2001: signed vs unsigned vectors, >>> operator
• Can be arbitrarily nested: (a & ~b) | c

CSE 372 (Martin): Synthesizable Verilog 19 CSE 372 (Martin): Synthesizable Verilog 20
Conditional Operator Hierarchical Design using Modules
• Verilog supports the ?: conditional operator • Interface specification
• Almost never useful in C (in my opinion) module mux2to1(S, A, B, O);
• Much more useful (and common) in Verilog input S, A, B;
output O;
• Examples: • Can also have inout: bidirectional wire (we will not need)
assign out = S ? B : A; • Alternative: Verilog 2001 interface specification
module mux2to1(input S, A, B, output O);
assign out = (sel == 2'b00) ? a : • Declarations
(sel == 2'b01) ? b :
• Internal wires, i.e., “local” variables
(sel == 2'b10) ? c :
(sel == 2'b11) ? d : 1'b0; • Wires also known as “nets” or “signals”
wire S_, AnS_, BnS;
• What do these do? • Implementation: primitive and module instantiations
and (AnS_, A, S_);

CSE 372 (Martin): Synthesizable Verilog 21 CSE 372 (Martin): Synthesizable Verilog 22

Verilog Module Example Hierarchical Verilog Example

module mux2to1(S, A, B, O);
• Build up more complex modules using simpler modules
input S, A, B;
output O;
• Example: 4-bit wide mux from four 1-bit muxes
S
• Again, just “drawing” boxes and wires
wire S_, AnS_, BnS;
A
O module mux2to1_4(Sel, A, B, O);
not (S_, S); B input [3:0] A;
and (AnS_, A, S_); input [3:0] B;
and (BnS, B, S); input Sel;
or (O, AnS_, BnS); output [3:0] O;
endmodule
mux2to1 mux0 (Sel, A[0], B[0], O[0]);
• Instantiation: mux2to1 mux0 (cond, in1, in2, out); mux2to1 mux1 (Sel, A[1], B[1], O[1]);
mux2to1 mux2 (Sel, A[2], B[2], O[2]);
• Operators and expressions can be used with modules mux2to1 mux3 (Sel, A[3], B[3], O[3]);
• !mux2to1 mux0 (cond1 & cond2, in1, in2, out); endmodule
CSE 372 (Martin): Synthesizable Verilog 23 CSE 372 (Martin): Synthesizable Verilog 24
Connections by Name Arrays of Modules
• Can (should?) specify module connections by name • Verilog also supports arrays of module instances
• Helps keep the bugs away • Well, at least some Verilog tools
• Example • Support for this feature varies (may not work well in Xilinx)
mux2to1 mux0 (.S(Sel), .A(A[0]), .B(B[0]), .O(O[0]));
• Also, then order doesn’t matter module mux2to1_4(Sel, A, B, O);
mux2to1 mux1 (.A(A[1]), .B(B[1]), .O(O[1]), .S(Sel)); input [3:0] A;
input [3:0] B;
input Sel;
output [3:0] O;

mux2to1 mux0[3:0] (Sel, A, B, O);

endmodule

CSE 372 (Martin): Synthesizable Verilog 25 CSE 372 (Martin): Synthesizable Verilog 26

Parameters Last Multiplexer Example

• Allow per-instantiation module parameters • Using conditional operator
• Use “parameter” statement
• modname #(10, 20, 30) instname (in1, out1); module mux2to1_N(Sel, A, B, Out);
• Example: parameter N = 1
input [N-1:0] A;
module mux2to1_N(Sel, A, B, O); input [N-1:0] B;
parameter N = 1 input Sel;
input [N-1:0] A; output [N-1:0] Out;
input [N-1:0] B; assign Out = Sel ? B : A
input Sel; endmodule
output [N-1:0] O;
mux2to1 mux0[N-1:0] (Sel, A, B, O); mux2to1_N #(4) mux1 (S, in1, in2, out)
endmodule
…
mux2to1_N #(4) mux1 (S, in1, in2, out)
CSE 372 (Martin): Synthesizable Verilog 27 CSE 372 (Martin): Synthesizable Verilog 28
Comments Verilog Pre-Processor
• Like the C pre-processor
• C/Java style comments • But uses ` (back-tick) instead of #
• // comment until end of line • Constants: `define
• /* comment between markers */ • No parameterized macros
• Use ` before expanding constant macro
• Note: all variable names are case sensitive `define letter_A 8’h41
wire w = `letter_A;
• Conditional compilation: `ifdef, `endif
• File inclusion: `include

• Parameter vs `define
• Parameter only for “per instance” constants
• `define for “global” constants

CSE 372 (Martin): Synthesizable Verilog 29 CSE 372 (Martin): Synthesizable Verilog 30

Recall: Two Types of Digital Circuits Designing Sequential Logic

• Combinational Logic • CSE372 design rule: separate comb. logic from sequential
• Logic without state variables state elements
• Examples: adders, multiplexers, decoders, encoders • Not enforced by Verilog, but a very good idea
• No clock involved • Possible exceptions: counters, shift registers
• We’ll give you a flip-flop module (see next slide)
• Sequential Logic
• Edge-triggered, not a transparent latch
• Logic with state variables
• State variables: latches, flip-flops, registers, memories • Parameterized to create a n-bit register
• Clocked • Example use: state machine
• State machines, multi-cycle arithmetic, processors
Clock
State Combinational Output
• Sequential Logic in Verilog Current
Register Logic
• Special idioms using behavioral constructs that synthesize into State
latches, memories Next State

CSE 372 (Martin): Synthesizable Verilog 31 CSE 372 (Martin): Synthesizable Verilog 32
Sequential Logic in Verilog Sequential Logic in Verilog
• How do we specify state-holding constructs in Verilog? • How do we specify state-holding constructs in Verilog?
module dff (out, in, wen, rst, clk); module register (out, in, wen, rst, clk);
wen = write enable parameter n = 1; wen = write enable
output out; rst = reset output [n-1:0] out; rst = reset
input in; clk = clock input [n-1:0] in; clk = clock
input wen, rst, clk; input wen, rst, clk;

reg out; reg [n-1:0] out;

always @(posedge clk) always @(posedge clk)
begin begin
if (rst) if (rst)
out = 0; out = 0;
else if (wen) else if (wen)
out = in; out = in;
Larger memories done similarly
end end
(we will also give these to you)
endmodule endmodule
CSE 372 (Martin): Synthesizable Verilog 33 CSE 372 (Martin): Synthesizable Verilog 34

Clocks Signals Simulation

• Clocks & reset signals are not normal signals • Used to test and debug our designs
• Travel on dedicated “clock” wires • Graphical output via waveforms
• Reach all parts of the chip
• Special “low-skew” routing

• Ramifications:
• Never do logic operations on the clocks
• If you want to add a “write enable” to a flip-flop:
• Use a mux to route the old value back into it
• (or use the flip-flop with write enable we give you!)
• Do not just “and” the write-enable signal with the clock!

• Messing with the clock can cause a errors

• Often can only be found using timing simulation

CSE 372 (Martin): Synthesizable Verilog 35 CSE 372 (Martin): Synthesizable Verilog 36
Levels of Simulation Testbenches
• Functional (or Behavioral) Simulation • How does one test code?
• Simulates Verilog abstractly
• No timing information, can’t detect “timing bugs” • In C/Java?
• Post-synthesis Timing Simulation • Write test code in C/Java to test C/Java
• Simulating devices generated via synthesis • “Test harness”, “unit testing”
• Gates, transistors, FPGA logical units (LUTs or lookup tables)
• No interconnect delay • For Verilog/VHDL?
• Not all internal signals may still exist • Write test code in Verilog to test Verilog
• Synthesis might have optimized or changed the design
• Verilog has advanced “behavioral” commands to facilitate this:
• Slower
• Delay for n units of time
• Layout Timing Simulation • Full high-level constructs: if, while, sequential assignment, ints
• After synthesis, the tool “places and routes” the logic blocks
• Input/output: file I/O, output to display, etc.
• Includes all sources of delay
• Even slower
• Example as part of Lab 1
CSE 372 (Martin): Synthesizable Verilog 37 CSE 372 (Martin): Synthesizable Verilog 38

Common Errors Additional Verilog Resources

• Tools are from a less gentle time • Elements of Logic Design Style by Shing Kong, 2001
• More like C, less like Java • Dos, do-nots, tips
• Assume that you mean what you say • http://www.cis.upenn.edu/~milom/elements-of-logic-design-style/
• Common errors:
• Not assigning a wire a value • Verilog HDL Synthesis: A Practical Primer
• Assigning a wire a value more than once • By J. Bhasker, 1998
• Implicit wire declarations (default to type “wire” 1-bit wide) • To the point (<200 pages)
• Disable by adding the following to the file:
• `default_nettype none • Advanced Digital Design with the Verilog HDL
• Does not work with ModelSim • By Michael D. Ciletti, 2003
• !Avoid names such as: • Verilog plus lots of digital logic design (~1000 pages)
• clock, clk, power, pwr, ground, gnd, vdd, vcc, init, reset, rst
• Some of these are “special” and will silently cause errors • Verilog tutorial on CD from “Computer Org. and Design”
CSE 372 (Martin): Synthesizable Verilog 39 CSE 372 (Martin): Synthesizable Verilog 40