Deep learning 4 layers

DESIGN SPECIFICATION
Version 1.0
December 2018

TEAM 1
Vu Hoang Giang
Nguyen Ha Thu
Nguyen Tien Thanh

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Table of content
1. Overview ....................................................................................................................................................... 5
2. Port Description ......................................................................................................................................... 5
3. Common Function Implementation ................................................................................................... 5
3.1. Bias and Weight module................................................................................................................. 5
3.2. Net calculator...................................................................................................................................... 6
3.3. Relu module ........................................................................................................................................ 7
3.4. PISO register ....................................................................................................................................... 8
3.5. Delta1_j module ................................................................................................................................. 9
3.6. Delta0_j module ............................................................................................................................... 10
3.7. Dw_ij module .................................................................................................................................... 10

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List of Figure

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List of Tables

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1. Overview
2. Port Description
Bảng 2.1. UART Port Description

Port Name Width I/O Description

Global Signals
pclk 1 I Clock
presetn 1 I Asynchronous reset, active low
Register Access Signals
psel 1 I Slave select
penable 1 I
paddr 3 I Register address
pwrite 1 I Register write/read indicator
pwdata 8 I Write data
prdata 8 O Read data
pslverr 1 O Slave error
pready 1 O Slave ready
UART Interface
Utx 1 O UART transmission line
Urx 1 I UART reception line
Interrupt Interface
txc_irq 1 O TX completed interrupt request
rxc_irq 1 O RX completed interrupt request

3. Common Function Implementation

Cá c common function được sử dụ ng là :

 Bias module, Weight module.

 Net calculator, relu_function, sigmoid function
 Delta1_j module, Delta2_j module, Delta0_j module, dw_ij module

3.1. Bias and Weight module

3.1.1. Functional Description

Được sử dụng để lưu giá trị của các phần tử bias, đồng thời có thể cập nhập và khởi tạo
được giá trị bias.

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3.1.2. Port Description

Table 3.1 Bias module port description

Port Name Width I/O Description

clk 1 I Synchronous clock
rst_n 1 I Asynchronous reset, active low
update 1 I Update new value of bias
init 1 I Initial signal
delta D_WIDTH I Delta value
value D_WIDTH O Value of bias (Weight)
D_WIDTH is the parameter indicate data size

3.1.3. Block diagram

Block digram of Bias (weight) module is shown in Figure 4.1.

Figure 3.1 Block diagram of bias (weight) module

3.2. Net calculator

3.2.1. Functional Description

Used to calcalate net value of each neuron

3.2.2. Port Description

Table 3.2 Net calculator port description

Port Name Width I/O Description

clk 1 I Synchronous clock
rst_n 1 I Asynchronous reset, active low

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enable 1 I Write request from hardware
load 1 I Write data from hardware
w D_WIDTH I Weight value
pre_out D_WIDTH I Output of neuron in previos layer
net D_WIDTH O Net value
D_WIDTH is the parameter indicate data size

3.2.3. Block diagram

Block digram of Net calculator is shown in Figure 4.2

Figure 3.2 Block diagram of net calculator

3.3. Relu module

3.3.1. Functional Description

Relu module is disigned to implement relu function

3.3.2. Port Description

Table 3.3 Relu module port desciption

Port Name Width I/O Description

x D_WIDTH I input
y D_WIDTH I Value of relu function (x)
D_WIDTH is the parameter indicate data size

3.3.3. Block diagram

Block digram of Relu module is shown in Figure 4.3

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 Figure 3.3 Block diagram of relu module

3.4. PISO register

3.4.1. Functional Description

Used to convert paralel data to serial data

3.4.2. Port Description

Table 3.4 PISO register port description

Port Name Width I/O Description

clk 1 I Synchronous clock
rst_n 1 I Asynchronous reset, active low
shift 1 I Shift signl
load 1 I Load new data
Data_in D_WIDTH * N_PRE I Paralel Data in
Data_out D_WIDTH O Serial data out
D_WIDTH is the parameter indicate data size
N_PRE is the parameter indicate number neuron of previous layer

3.4.3. Working

Figure 4.5 describe working of PISO register

Bảng 3.1. RC Register output behavior

rst_n clk load shift reg

0 x x x 0
1 ↑ 1 x Data_in
1 ↑ 0 0 Unchanged
1 ↑ 0 1 Shift left, D_WIDTH MSB
bits will be replace by 0
Reg is register that stored data in. Data_out is always equal Reg [D_WIDTH -1:0]
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3.5. Delta1_j module

3.5.1. Functional description

Used to calcalate delta value of each neuron in hidden1 layer.

3.5.2. Port description

Table 3.5 Delta1_j module port description

Port Name Width I/O Description

clk 1 I Synchronous clock
rst_n 1 I Asynchronous reset, active low
h1j_in D_WIDTH I Net value of neuron j in hidden 1 layer
w2_jj D_WIDTH I Weight2[j][j]
Delta2_j D_WIDTH I Delta value of neuron j in hidden 2 layer
Delta1_j D_WIDTH O Delta value of neuron j in hidden 1 layer
D_WIDTH is the parameter indicate data size

3.5.3. Block Diagram

Block digram of Delta1_j module is shown in Figure 4.4

Figure 3.4 Block diagram of Delta1_j module

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3.6. Delta0_j module

3.6.1. Functional Description

Used to calculate delta value of neuron j in Output layer

3.6.2. Port Description

Table 3.6 Delta0_j module port description

Port Name Width I/O Description

clk 1 I Synchronous clock
rst_n 1 I Asynchronous reset, active low
Desired_j D_WIDTH I Derised output of neuron j in output layer
Oj_out D_WIDTH I Actual output of neuron j in output layer
Delta0_j D_WIDTH O Delta value of neuron j in output layer
D_WIDTH is the parameter indicate data size

3.6.3. Block diagram

Block digram of Delta0_j module is shown in Figure 4.5

Figure 3.5 Block diagram of Delta0_j module

3.7. Dw_ij module

3.7.1. Functional Description

Used to calculate delta value of weight[i][j] and multiple it with learning rate u = 16’b1
(0.001).

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3.7.2. Port description

Table 3.7 dw_ij module port desription

Port Name Width I/O Description

clk 1 I Synchronous clock
rst_n 1 I Asynchronous reset, active low
Delta_j D_WIDTH I Delta value of neuron j in current layer
Pre_out_i D_WIDTH I Ouput of neuron i in previous layer
Dw_ij D_WIDTH O Detal value of weight[i][j]
D_WIDTH is the parameter indicate data size

3.7.3. Block diagram

Block digram of Delta0_j module is shown in Figure 4.5

Figure 3.6 Block diagram of dw_ij module

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