GATE LEVEL DESIGN OF A DIGITAL CLOCK

WITH ASYNCHRONOUS –SYNCHRONOUS

LOGIC
 ABSTRACT

A digital clock has been designed at gate level and is being presented in this paper. The clock
architecture consists of three major blocks SECOND, MINUTE and HOUR. The architecture is the amalgam
both of synchronous and asynchronous logic. All the flip-flops at each block run synchronously. The triggering
operation of a block is asynchronous in nature. It serves the design requiring lower power consumption,
provides lesser noise and electromagnetic interference, lower delay and greater throughput. The clock is
designed at Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST).
 INTRODUCTION TO VLSI

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands

of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and

communication technologies were being developed. The microprocessor is a VLSI device. The term is no

longer as common as it once was, as chips have increased in complexity into the hundreds of millions of

transistors.

Overview

The first semiconductor chips held one transistor each. Subsequent advances added more and more

transistors, and, as a consequence, more individual functions or systems were integrated over time. The first

integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors,

making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as

"small-scale integration" (SSI), improvements in technique led to devices with hundreds of logic gates, known

as large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has

moved far past this mark and today's microprocessors have many millions of gates and hundreds of millions of

individual transistors.

At one time, there was an effort to name and calibrate various levels of large-scale integration

above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But the huge number of gates and

transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater

than VLSI levels of integration are no longer in widespread use. Even VLSI is now somewhat quaint, given

the common assumption that all microprocessors are VLSI or better.

As of early 2008, billion-transistor processors are commercially available, an example of which

is Intel's Montecito Itanium chip. This is expected to become more commonplace as semiconductor fabrication

moves from the current generation of 65 nm processes to the next 45 nm generations (while experiencing new

challenges such as increased variation across process corners). Another notable example is NVIDIA’s 280

series GPU.
 This microprocessor is unique in the fact that its 1.4 Billion transistor count, capable of a

teraflop of performance, is almost entirely dedicated to logic (Itanium's transistor count is largely due to the

24MB L3 cache). Current designs, as opposed to the earliest devices, use extensive design automation and

automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic

functionality. Certain high-performance logic blocks like the SRAM cell, however, are still designed by hand

to ensure the highest efficiency (sometimes by bending or breaking established design rules to obtain the last

bit of performance by trading stability).

What is VLSI?

VLSI stands for "Very Large Scale Integration". This is the field which involves packing more and

more logic devices into smaller and smaller areas.

VLSI

1. Simply we say Integrated circuit is many transistors on one chip.

2. Design/manufacturing of extremely small, complex circuitry using modified semiconductor

material

3. Integrated circuit (IC) may contain millions of transistors, each a few mm in size

4. Applications wide ranging: most electronic logic devices

History of Scale Integration

 late 40s Transistor invented at Bell Labs

 late 50s First IC (JK-FF by Jack Kilby at TI)

 early 60s Small Scale Integration (SSI)

 10s of transistors on a chip

 late 60s Medium Scale Integration (MSI)

 100s of transistors on a chip

 early 70s Large Scale Integration (LSI)

 1000s of transistor on a chip

 early 80s VLSI 10,000s of transistors on a

 chip (later 100,000s & now 1,000,000s)

  Ultra LSI is sometimes used for 1,000,000s

 SSI - Small-Scale Integration (0-102)

 MSI - Medium-Scale Integration (102-103)

 LSI - Large-Scale Integration (103-105)

 VLSI - Very Large-Scale Integration (105-107)

 ULSI - Ultra Large-Scale Integration (>=107)

Advantages of ICs over discrete components

While we will concentrate on integrated circuits , the properties of integrated circuits-

what we can and cannot efficiently put in an integrated circuit-largely determine the architecture of the entire

system. Integrated circuits improve system characteristics in several critical ways. ICs have three key

advantages over digital circuits built from discrete components:

 Size. Integrated circuits are much smaller-both transistors and wires are shrunk to micrometer sizes,

compared to the millimeter or centimeter scales of discrete components. Small size leads to advantages

in speed and power consumption, since smaller components have smaller parasitic resistances,

capacitances, and inductances.

 Speed. Signals can be switched between logic 0 and logic 1 much quicker within a chip than they can

between chips. Communication within a chip can occur hundreds of times faster than communication

between chips on a printed circuit board. The high speed of circuits on-chip is due to their small size-

smaller components and wires have smaller parasitic capacitances to slow down the signal.
 Power consumption. Logic operations within a chip also take much less power. Once again, lower

power consumption is largely due to the small size of circuits on the chip-smaller parasitic capacitances

and resistances require less power to drive them.

VLSI and systems

These advantages of integrated circuits translate into advantages at the system level:

 Smaller physical size. Smallness is often an advantage in itself-consider portable televisions or

handheld cellular telephones.

 Lower power consumption. Replacing a handful of standard parts with a single chip reduces total

power consumption. Reducing power consumption has a ripple effect on the rest of the system: a
 smaller, cheaper power supply can be used; since less power consumption means less heat, a fan may

no longer be necessary; a simpler cabinet with less shielding for electromagnetic shielding may be

feasible, too.
 Reduced cost. Reducing the number of components, the power supply requirements, cabinet costs, and

so on, will inevitably reduce system cost. The ripple effect of integration is such that the cost of a

system built from custom ICs can be less, even though the individual ICs cost more than the standard

parts they replace.

Understanding why integrated circuit technology has such profound influence on the design of digital

systems requires understanding both the technology of IC manufacturing and the economics of ICs and digital

systems.

Applications

 Electronic system in cars.

 Digital electronics control VCRs

 Transaction processing system, ATM

 Personal computers and Workstations

 Medical electronic systems.

 Etc….

Applications of VLSI

Electronic systems now perform a wide variety of tasks in daily life. Electronic systems in

some cases have replaced mechanisms that operated mechanically, hydraulically, or by other means;

electronics are usually smaller, more flexible, and easier to service. In other cases electronic systems have

created totally new applications. Electronic systems perform a variety of tasks, some of them visible, some

more hidden:

 Personal entertainment systems such as portable MP3 players and DVD players perform

sophisticated algorithms with remarkably little energy.

 Electronic systems in cars operate stereo systems and displays; they also control fuel

injection systems, adjust suspensions to varying terrain, and perform the control functions

required for anti-lock braking (ABS) systems.

  Digital electronics compress and decompress video, even at high-definition data rates, on-

the-fly in consumer electronics.

 Low-cost terminals for Web browsing still require sophisticated electronics, despite their

dedicated function.
 Personal computers and workstations provide word-processing, financial analysis, and

games. Computers include both central processing units (CPUs) and special-purpose

hardware for disk access, faster screen display, etc.

 Medical electronic systems measure bodily functions and perform complex processing

algorithms to warn about unusual conditions. The availability of these complex systems, far

from overwhelming consumers, only creates demand for even more complex systems.

The growing sophistication of applications continually pushes the design and manufacturing of

integrated circuits and electronic systems to new levels of complexity. And perhaps the most amazing

characteristic of this collection of systems is its variety-as systems become more complex, we build not a few

general-purpose computers but an ever wider range of special-purpose systems. Our ability to do so is a

testament to our growing mastery of both integrated circuit manufacturing and design, but the increasing

demands of customers continue to test the limits of design and manufacturing

ASIC

An Application-Specific Integrated Circuit (ASIC) is an integrated circuit (IC) customized for a

particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell

phone is an ASIC. Intermediate between ASICs and industry standard integrated circuits, like the 7400 or the

4000 series, are application specific standard products (ASSPs).

As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and

hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million. Modern ASICs often

include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large

building blocks. Such an ASIC is often termed a SoC (system-on-a-chip). Designers of digital ASICs use a

hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.

Field-programmable gate arrays (FPGA) are the modern-day technology for building a breadboard or

prototype from standard parts; programmable logic blocks and programmable interconnects allow the same
FPGA to be used in many different applications. For smaller designs and/or lower production volumes, FPGAs

may be more cost effective than an ASIC design even in production.

1. An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a

particular use, rather than intended for general-purpose use.

2. A Structured ASIC falls between an FPGA and a Standard Cell-based ASIC

3. Structured ASIC’s are used mainly for mid-volume level designs

4. The design task for structured ASIC’s is to map the circuit into a fixed arrangement of known

cells.

1. INTRODUCTION

A digital clock is a type of clock that displays the time digitally. Instead of the rotary mechanism of
electromechanical clock, it uses digital counters that count second, minute and hours. Each sixty seconds make
a minute and each sixty minutes an hour. After twenty four hours the clock resets and starts from initial
condition. The functional unit of a digital clock is a counter that represents a second, minute or hour block. A
counter [7] may be defined as a register i.e. a group of flip-flops that goes through a predetermined sequence
of states upon the application of input pulses.The logic gates in a counter are connected in such a way as to
produce a prescribed sequence of binary states in the register.

There are two types of input/output (I/O) synchronization technique to design a counter
[10]:synchronous and asynchronous technique. In an asynchronous counter, the flip-flop output transition
serves as a source for triggering other flip-flops. In otherwords, the CP inputs of all flip-flops (except the first)
are triggered not only by the incoming pulses but rather by the transitions that occur in other flip-flops. The
asynchronous counter is also referred to as overlapped counter. A problem in designing an asynchronous logic
is that it cannot be described by Boolean equations developed for describing clocked sequential circuits. Again
as output of one flip-flop acts as the input of another one, the system designed at asynchronous logic faces
considerable delay.

On the other hand, a synchronous circuit is a digital circuit in which the parts are synchronized
by a single clock signal. In an ideal synchronous circuit, every change in the logical levels of its storage
components is simultaneous. These transitions follow the level change of a special clock signal. Ideally, the
input to each storage element has reached its final value before the next clock occurs, so the behavior of the
whole circuit can be predicted exactly. Practically, some delay is required for each logical operation, resulting
in a maximum speed at which each synchronous system can run .Thus in a synchronous counter all the flip-
flops are clocked simultaneously. The decision whether a flip-flop is to be complemented or not is determined
from the values of the T inputs at the time of pulse. If T=0, the flip-flop remains unchanged. If T=1, the flip
flop complements.

Thus the states of the counters get changed. Synchronous logic suffers from some
disadvantages: As the clock is usually a high-frequency signal, this distribution consumes a relatively large
amount of power and dissipates much heat. Even the flip-flops that are doing nothing consume a small amount
of power, thereby generating waste heat in the chip . Again the maximum possible clock rate is determined by
the slowest logic path in the circuit, otherwise known as the critical path. This means that every logical
calculation, from the simplest to the most complex, must complete in one clock cycle. In spite of these
drawbacks synchronous counters are more suited for some reasons.

At an asynchronous counter the output of any flip-flop (except the first) depends solely upon the
output of the previous T flip-flop. Due to the RC time delay at each transistor there occurs a large aggregation
of delay time after several flip-flops [8]. So to design asynchronous counter is impractical. For this reason
synchronous logic has been adopted to construct counter blocks. In addition to this the synchronous technique
serves greater throughput and much lower overhead for its design simplicity .
 . In the way to integrated circuit implementation process way can notice two
major steps: Design stage and fabrication stage. Design stage includes system design,
logic design and mask layout preparation. At the system level design the architecture
is checked against the system specification to ensure that all required hardware
features and data paths have been included. At the next level of hierarchy, the
architectural blocks are expanded into logic diagrams

In this stage the whole system is transferred into aggregation of registers [ 9]. Here
each item represents a particular logic function. If that particular logic functions are represented by
logic gates such as AND, OR or XOR, then it is called Gate level design [6]. Gate level design
realizes intensive aggregation of elements at much l o w e r area. To solve the problems
associated both with synchronous and asynchronous logic the author adopted a recently
emerged logic structure GALS . Globally Asynchronous Locally Synchronous logic is the
amalgam of the two logics. It not only removes the drawbacks but also provides more advantages .
The advantages include lower power consumption and electromagnetic interferences
.

2. OVERVIEW OF THE ARCHITECTURE

The digital clock designed as shown in Fig.1 assumes three functional blocks: second, minute and
hour. The second and minute block count from 0 to 59. So six T flip-flops are required to construct either
second or minute block (2^6=64). The hour block counts from 0 to 23. So it requires five T flip-flops
(2^5=32).
 Fig.1 : simplified architecture of the design clock.

The flip-flops inside a block (second, minute or hour) run simultaneously as they are triggered by same
clock pulse. But the clock pulse of minute block is a function of the outputs of the second block. Again the
clock pulse of the hour block is also a function of the outputs of the minute block. So the block to block
logical relation is asynchronous in nature. Thus the design architecture is a combination both of asynchronous
and synchronous logic.

Fig.2 : Logic diagram of SECOND and MINUTE block

3. MODEL DEVELOPMENT

There are three asynchronously operating blocks at the architectural design of the digital clock. But
flip-flops at each block are energised synchronously. The SECOND and MINUTE block have six T flip-flops
each. When they operate synchronously they are projected to have 64 distinct states. But we want them to go
to their primary state after counting 60 states. So we need to modify the input and output relationships of flip-
flops. Representing the input as Ta, Tb, Tc etc and A, B, C etc for flip-flops a, b, c respectively as shown in
Fig.2, the relations for SECOND and MINUTE blocks are:

Ta=BCEF (A’D+AD’)
Tb= ABCD’EF+CDEF (A’+B')
Tc =ABEFCD’+ DEF (A’+B’+C’)
Td=EF (A’+C’+B’)
Te= F (A’+B’+C’+D’)
Tf =1

Similarly we want to make the flip-flops of HOUR block to go to its primary state after counting
24 states instead of 32 states. For this case the input output relationships of the flip-flops are simplified as
follows:

Ta= CDE (A’B+AB’)

Tb=A’CDE
Tc=DE (A’+B’)
Td=E (A’+B’)
Te=1

Thus in the designed architecture sixty seconds make a minute and sixty minute an hour. After
twenty four hour the clock resets and starts counting from initial states at another day. It is customary to keep a
RESET button so that the user can reset the clock at any time.

4 .OPERATION

The individual block of the design is an aggregate of several synchronous binary counters. Therefore,
the flip-flop in the lowest order position is complemented with every pulse. This means that its T input must be
maintained at logic 1. A flip flop in any other position is complemented with a pulse provided all the bits in the
lower order positions are equal to 1. As the input functions T’s of the flip flops are configured, after the desired
sequence (111011 for second and minute block) comes, all the outputs of the flip flops will be 0.

When the second block reaches to 59 (111011 in binary), all the flip flops of this second block resets.
Then clock signal of minute block becomes 1. As Tfm =1 now logically, minute block state is increased by one
at the next clock pulse. Thus each time second block faces state 111011, minute increases by one. The same
thing occurs from minute to hour interaction. Aftercounting 23 hour (10111), 59 minute and 59 seconds all the
flip-flops resets. As shown in Fig.3. Flow chart explaining the operation of digital clock.

Fig.3 : Flowchart explaining the operation of digital clock.

IMPLEMENTATION

FPGA DESIGN FLOW

 In this part of tutorial we are going to have a short intro on FPGA design flow. A simplified version of
design flow is given in the flowing diagram.

Figure 5.3 FPGA Design Flow

5.2.1 Design Entry

There are different techniques for design entry. Schematic based, Hardware Description Language and
combination of both etc. . Selection of a method depends on the design and designer. If the designer wants to
deal more with Hardware, then Schematic entry is the better choice. When the design is complex or the
designer thinks the design in an algorithmic way then HDL is the better choice. Language based entry is faster
but lag in performance and density.

HDLs represent a level of abstraction that can isolate the designers from the details of the hardware
implementation. Schematic based entry gives designers much more visibility into the hardware. It is the better
choice for those who are hardware oriented. Another method but rarely used is state-machines. It is the better
choice for the designers who think the design as a series of states. But the tools for state machine entry are
limited. In this documentation we are going to deal with the HDL based design entry.

5.2.2 Synthesis
 Figure 5.4 FPGA Synthesis

The process that translates VHDL/ Verilog code into a device netlist format i.e. a complete circuit with
logical elements (gates flip flop, etc…) for the design. If the design contains more than one sub designs, ex. to
implement a processor, we need a CPU as one design element and RAM as another and so on, then the
synthesis process generates netlist for each design element Synthesis process will check code syntax and
analyze the hierarchy of the design which ensures that the design is optimized for the design architecture, the
designer has selected. The resulting netlist(s) is saved to an NGC (Native Generic Circuit) file (for Xilinx®
Synthesis Technology (XST)).

5.2.3 Implementation

This process consists of a sequence of three steps

 Translate
 Map
 Place and Route

Translate:

Process combines all the input netlists and constraints to a logic design file. This information is saved
as a NGD (Native Generic Database) file. This can be done using NGD Build program. Here, defining
constraints is nothing but, assigning the ports in the design to the physical elements (ex. pins, switches, buttons
etc) of the targeted device and specifying time requirements of the design. This information is stored in a file
named UCF (User Constraints File). Tools used to create or modify the UCF are PACE, Constraint Editor Etc.
 Figure 5.5 FPGA Translate

Map:

Process divides the whole circuit with logical elements into sub blocks such that they can be fit into
the FPGA logic blocks. That means map process fits the logic defined by the NGD file into the targeted FPGA
elements (Combinational Logic Blocks (CLB), Input Output Blocks (IOB)) and generates an NCD (Native
Circuit Description) file which physically represents the design mapped to the components of FPGA. MAP
program is used for this purpose.

Figure 5.6 FPGA map

Place and Route:

PAR program is used for this process. The place and route process places the sub blocks from the map
process into logic blocks according to the constraints and connects the logic blocks. Ex. if a sub block is
placed in a logic block which is very near to IO pin, then it may save the time but it may affect some other
constraint. So tradeoff between all the constraints is taken account by the place and route process.

The PAR tool takes the mapped NCD file as input and produces a completely routed NCD file as
output. The output NCD file consists of the routing information.

Figure 5.7 FPGA Place and route

5. SIMULATION RESULTS
The result was the exact replica of our expectation. From the timing diagram at Fig.7 we can
notice that initially all the flip-flops are at initial state (zero state) when RESET is at state 0. The rest part of
the circuitry remains inactive until RESET is at state 1. When RESET is at state 1 the flip-flops are allowed to
follow counting. The state of SECOND block changes as 000000, 000001, 000010, 000011 and so on. When it
reaches state 111011 (i.e. 59 in decimal), a clock pulse goes to MINUTE block and its state changes from
000000 to 000001 and the SECOND block starts counting again from 000000 state. Thus after 60 minutes
when state 111011 appears at MINUTE block it resets and the state of HOUR block changes from 00000 to
00001. After counting 23 hour 59 minutes and 59 seconds, all the flip flops of the system get reseted (i.e. zero
state) when the next clock pulse appears at the SECOND block.

Simulation of Top module

 6. SYNTHESIS REPORT
The model is designed at Xilinx System Generator. Then it is synthesized with Xilinx Synthesis Tool (XST) as
shown in Fig.4. The outcomes include a IC package with two input ports: RESET and CLOCK PULSE and
seventeen output ports. The RTL(Register Transfer Level) schematic of the design is provided as in Fig.6(a),
(b),(c)&(d).It assembles logic gates which meet the systems requirements [6].

Fig.4 : Block diagram

Fig :RTL Schematic

 Figure: Routed Design of Digital Clock on FPGA

SYNTHESIS REPORT

Device utilization summary:

---------------------------
Selected Device : 3s500efg320-5

Number of Slices: 16 out of 4656 0%

Number of Slice Flip Flops: 12 out of 9312 0%
Number of 4 input LUTs: 32 out of 9312 0%
Number of IOs: 19
Number of bonded IOBs: 19 out of 232 8%
Number of GCLKs: 1 out of 24 4%
Timing Summary:
---------------
Speed Grade: -5

Minimum period: 4.011ns (Maximum Frequency: 249.286MHz)

Minimum input arrival time before clock: No path found
Maximum output required time after clock: 4.326ns
Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

CONCLUSION

Logic gate level design of a digital clock has been presented. The design comprises the amalgam of
synchronous and asynchronous techniques to attain its purpose. The Gate level design realizes intensive
aggregation of components at smaller size of the chip. Again the combinational structure assumes lower power
requirement, electromagnetic interference and greater throughput. The designed structure was synthesized
using XST and simulated at verilogger pro 6.5. The design was successfully loaded at Xilinx FPGA device,
MDA-ASIC2 (XC25150). In spite of having some limitations the design has been found to be useful enough
 FUTURESCOPE
The digital clock that is designed can count seconds, minutes and hours only. But at the real
world people are not satisfied at this. They are interested in having notified other information
such as date, month, year etc. It is also expected that the clock will serve some other facilities
such as alarm, reminder etc. These features can be added just extending the design a little bit
further. Again the design includes lesser number of gates. So it will be cost-inefficient to design
on an entire chip. The author wishes to design a complete package of digital clock at the near
future that will overcome the remaining drawbacks.

RÉFÉRENCES

1. A. Hemaini, T. Meincke, S. Kumar, A. Postula, T. Olsson, P. Nilson, J. Oberrg, P. Ellervee,

Lowering Power Consumpsion in Clock by using Globally Asynchronous Locally Synchronous
Design Style”. DAC 99, New Orleans, Louisiana (c) 1999 ACM 1- 58113-109-7/99/06.
2. Jonas Carlson, Kent Palmnvist, Lars Wanhammar, “Synchronous Design Flow for Globally
Asynchronous Locally Synchronous Systems”. www.es.isy.liu.se/publications/papers
3.F.E. Barber, T. J. Bartoli, R. L. Freyman, J.A. Grand, J. Kane and Kershaw, “An Overview of
the Silicon Very-Large-Scale-Integration Implementation”. ©1981 American Telephone and
elegraph Company, The Bell System Technical Journal, vol. 60, No.7, September 1981, printed
in USA.
4. Gordon M. Jacobs, Robert W. Brodersen, “A fully Asynchronous Digital Signal Processor
using Selftimed Circuit” Solid-State ircuits Conference, 1990. Digest of Technical Papers. 37th
ISSCC., 1990 IEEE International Issue Date: 14-16 Feb. 1990 . August 2002 .
5. Mark E. Dean, David L.Dill and Mark Horowitz, “Self Timed Logic using Current-Sensing
Completion Detection CSCD)”, Journal of VLSI Signal Processing, 7, 7-16 (1994) ©
1994Kluwer Academic Publisher, Boston, Manufactured in Netherland.