Data Converters

• Signals are of two types: Analog & Digital

• Digital Signal Processing (DSP) is much
easier, since we have to keep track of only
1s and 0s
• Analog signal processing is pretty tedious
(Remember BJT Amplifiers?)
• Particularly, in communication systems,
digital data transmission produces almost
error-free and noise-free operation

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* There is very little chance that digital signals would
get corrupted by noise (Remember Noise Margins?)
* Also, much less chance of signal interference in
digital transmissions
* However, after the digital signal is processed , we
may still need the o/p in analog form, e.g., speech
* Thus, the basic signal processing architecture:

Analog Analog
Signal i/p Digital Signal Signal o/p
Data Data
Processing Core
Converter Converter
(DSP Core)

Analog-to-Digital Digital-to-Analog
Converter (ADC) Converter (DAC)

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Sampling of Analog Signals:
VC
* Known as Sample-and-Hold Circuit Vi V0
* VC : Switch Control Signal: Storage
Capacitor
 Makes the switch close periodically (C)

* Produces pulses of width Δt and period T

* t: Sampling Interval
* f sampling = Sampling Frequency = 1/T
*  T  t  : Hold Interval
 During this time, V0 is fed to an ADC, and
converted to corresponding digital signal
* O /p is in N -bit binary form
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Vi, V0
Vi
Sampling of
Analog Signal

V0

VC

t

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Signal Quantization:
* Let an analog signal range from 0 to 10 V , which
needs to be converted to a 4-bit digital signal
* Recall: A 4-bit digital signal can represent 16
equispaced values (from 0 to 15 )
* Thus, each value is spaced apart by 10 V  15
= 0.67 V, which corresponds to 1 LSB
* This is known as Resolution of Conversion
* Chart: 0000  0.00 V; 0001  0.67 V; 0010  1.34 V;
0100  2.68 V; 1000  5.36 V; 1010  6.7 V;
1100  8.04 V; 1110  9.38 V; 1111  10 V
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* Note: For each bit increment , analog i/p range
is 0.67 V
* What happens if the analog signal lies within a
range, e.g., let's say 7 V?
* Now, 1010 is 6.7 V and 1011 is 7.37 V
 The o/p can be either of 1010 or 1011
 Either way, there is an error , known as
Quantization Error (QE )
* QE = (Analog Full Scale) / (2N  1),
where N = Number of bits
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* Obviously, this error can be reduced by increasing N
* Example:
 For N = 16, QE = 10 V   216  1 = 0.15 mV
 For N = 32, QE = 10 V   232  1 = 2.33 nV
(vanishingly small )
* Another way to express QE: ± LSB 2
* Example: N = 4, QE = ± 0.335 V
N = 16, QE = ± 0.075 mV
N = 32, QE = ± 1.165 nV

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DAC:
* Two types:
 Binary Weighted
 R -2R Ladder

Binary Weighted DAC :

R RF R2
A0
(LSB)
R/2
X
A1 R1
V0
R/4 V1
A2
(MSB)

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* A 2 A1 A 0 are digital i /p bits, which can be
either 0 or 1 (logically ), equivalent to 0 V
or some VREF (Reference Voltage )
* KCL at node X :
VREF  A 0 VREF  A1 VREF  A 2 V1
  
R R 2 R 4 RF
RF
 V1     4A 2  2A1  A 0   VREF
R
* Thus, the output voltage:
R2 R 2R F
V0    V1    4A 2  2A1  A 0   VREF
R1 R 1R
 Binary Weighting
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* Note: Maximum weight is assigned to A 2 ,
which has the least resistance (R / 4 ) attached
to it, so that it draws the maximum current
from the reference voltage  MSB
* Similarly, minimum weight is assigned to A 0 ,
which has the highest resistance (R) attached
to it, so that it draws the minimum current
from the reference voltage  LSB
* Note: If R1 = R F and R 2 = R, then
V0 =  4A 2  2A1  A 0   VREF

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Design Example:
* Let V0 (max) = 5 V
 A 2 A1A 0 = 111 should correspond to 5 V
 VREF   5 V   4  2  1  0.714 V
* For A 2 A1A 0 = 000, V0 = 0, while for A 2 A1A 0
= 001, V0 = 0.714 V =  5 V   23  1
 For each bit increment, V0 jumps by 0.714 V
 Resolution of the DAC = 0.714 V
* Note: For A 2 A1A 0 = 100, V0 = 2.856 V  V0  max  2

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R-2R Ladder DAC :
* For additional i/p bits, the resistors scale as
R / 8, R / 16 , R / 32, and so on
 Becomes a very clumsy design
* Remedy: R -2R Ladder DAC
R R V1
V0

2R 2R 2R 2R 2R

A0 A1 A2 R2
(LSB) (MSB) R1

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* Uses resistors of values R and 2R only, and a
single op-amp (OA)
* MSB (A 2 ) is closest to the OA, while LSB (A 0 )
is furthest from it
* A 0 A1 A 2 connected to either 0 or VREF (logic 0
or 1)
* Show that:
 V1 A =  A 2 3  VREF
2 1 and A1  A 0  0

 V1 A 1 and A =  A1 6   VREF
1 2  A0 0

 V1 A =  A 0 12   VREF
0 1 and A 2  A1  0

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* Thus, by superposition:
 V1 = 1 12  4A 2  2A1  A 0   VREF
* The OA is non-inverting, with gain:
V0 V1  1  R 2 R1
* Choose R 2 R1  11
 V0   4A 2  2A1  A 0   VREF
* The result is exactly same as that obtained in the
previous case, but using resistors of only 2 values
(R and 2R )
* Extremely popular DAC and heavily used

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ADC :
* Various options available, out of which, we will
be discussing two of them:
 Counting Type
 Flash (or Parallel Comparator )

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Counting Type:

Analog CLK
I/p
N-Bit Binary
Counter
BN–1
BN–2
Digital
Comparator
O/p
B1
B0

DAC

* Note: It employs a DAC within it

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Operating Principle:
* Initially, the Binary Counter is reset (all o /ps zero)
* Thus, DAC o /p = 0, fed back to the comparator
* Comparator o /p high  CLK is allowed to pass
to the counter through the AND gate
* The counter starts counting and increments by 1 at
each CLK pulse
* DAC converts this digital o/p to its analog equivalent
and feeds it back to the comparator, which compares
it with the analog i/p signal

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* So long as the analog i/p signal is greater than
the DAC o/p, the o/p of the comparator remains
high, and the counter keeps on counting
* As soon as the DAC o/p becomes greater than the
analog i/p signal, the comparator o/p goes low , and
the CLK signal is prevented from reaching the i/p
of the counter  the count stops
* At that instant of time, the binary o /p is taken out ,
and immediately thereafter the counter is reset ,
which starts the counting process again

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* Note: During the entire conversion period, the
analog i/p should not change, i.e., it must be
held constant
* Implemented using a Sample-and-Hold (S /H)
circuit, with its hold time at least equal to or
greater than the conversion time of the ADC
* Note: The conversion time itself is a function of
the analog i/p (smaller value leads to quicker
conversion and vice-versa)

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* As soon as the count stops, the Hold of the S/H
circuit is released , and it samples and holds the
next analog data for conversion
* Needs a maximum of  2 N  1  CLK cycles for
N -bit data
* Quite slow , if the analog i/p voltage is large, since
the count has to always start from zero
* Advantage: Very simple design and needs very
limited hardware  costs less

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Flash (Parallel Comparator):
Analog
VREF
I/p Vi

R C3

3VREF/4
B1
(MSB)
R
4-to-2 Line
C2
Encoder
B0 Digital O/p
(Line C0
VREF/2 (LSB)
not used)

R
C1

VREF/4

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* Fastest ADC availabe to date
* Note:
 For 0 < Vi < VREF /4:
C1 = C2 = C3 = 0
 For VREF /4 < Vi < VREF /2:
C1 = 1, C2 = C3 = 0
 For VREF /2 < Vi < 3VREF /4:
C1 = C2 = 1, C3 = 0
 For Vi > 3VREF /4:
C1 = C2 = C3 = 1

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* The 4 -to-2 Line Encoder takes these as i/ps and
produces 2-bit binary output
* Encoding Scheme:
MSB LSB
C3 C2 C1 B1 B0
0 0 0 0 0
0 0 1 0 1
0 1 1 1 0
1 1 1 1 1
* The entire operation is done parallely (in a flash)
 Known as a Parallel Comparator (or Flash) ADC
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* Note: QE (or Resolution) =  VREF 8
* Number of comparators needed =  2N  1 for
N -bit digital o /p
 For 8-bit digital o/p, need 255 comparators!!!
 One of the major drawbacks of flash ADC, i.e.,
hardware requirement (and thus, the cost ) is
huge
 Use limited to 8-bit o /p
* Note: Needs only one clock cycle for data conversion
 Extremely fast

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