Scribd
Upload
74 views1 page

GVP College of Engineering For Women Madhurawada::Visakhapatnam

This document is a midterm exam for a Digital Logic Design course covering three main topics: 1) Binary and octal number conversions. Students must convert between binary, octal, and decimal number systems. 2) Boolean algebra and logic gate implementations. Problems involve finding dual/complements of Boolean functions and implementing functions with NOR gates. 3) Karnaugh map minimization. Students must use K-maps to minimize Boolean functions in Sum of Products and Product of Sums form and define essential prime implicants. The exam has three questions worth a total of 30 marks and covers common number systems and logic design techniques taught in a basic Digital Logic Design course.

Uploaded by

prasanthi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
74 views1 page

GVP College of Engineering For Women Madhurawada::Visakhapatnam

This document is a midterm exam for a Digital Logic Design course covering three main topics: 1) Binary and octal number conversions. Students must convert between binary, octal, and decimal number systems. 2) Boolean algebra and logic gate implementations. Problems involve finding dual/complements of Boolean functions and implementing functions with NOR gates. 3) Karnaugh map minimization. Students must use K-maps to minimize Boolean functions in Sum of Products and Product of Sums form and define essential prime implicants. The exam has three questions worth a total of 30 marks and covers common number systems and logic design techniques taught in a basic Digital Logic Design course.

Uploaded by

prasanthi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 1

GVP COLLEGE OF ENGINEERING FOR WOMEN

MADHURAWADA::VISAKHAPATNAM
Department of CSE: Digital Logic Design
II B. Tech. (I Semester) Mid Examinations-I, August 2018
Descriptive Type Examination (R-16 Regulations)
Subject: Digital Logic Design Date: 25-08-2018
Sections: CSE-1 & CSE -2 Duration: 90 min.
Name of the Instructor/Faculty: Mrs. G Prashanthi / Mrs. B Vijaya Lakshmi
Answer all the Questions
All Questions carry equal marks
Paper is for a Maximum of 30 Marks

1. a) Convert the following number to Octal: (i) (1011.1010)2 [CO 1] (2 M)

b) Convert the following number to Binary: (i) (59.425)10 [CO 1] (2 M)

c) Perform the binary subtraction using 1’s and 2’s complement methods. (6 M)
(110011)2-(1110011)2 [CO 1]

2. a) Find the dual and complement of the following function: A'BD'+B'(AC'+D') +A'BC'.
[CO2] (4M)

b) Implement the following Boolean function with only two input NOR gates:
F=(AB'+D')E+C(A'+B'D). [CO2] (6M)

3. a) Simplify the following Boolean function


F(A, B, C, D)= Σ(0, 6, 8, 13, 14); d(A, B, C, d)=Σ(2, 4,10)
using K-Map method in (a)SOP form (b) POS form. [CO3] (8M)

b) Define the essential prime implicants in a K-map method. [CO3] (2M)

************

You might also like