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Aim: Sofware Used: Theory

The document describes the design of a dataflow Verilog module for a full adder/full subtractor circuit. It includes the theory of addition and subtraction using a common binary adder. The module uses a single input "ar" to determine whether to perform addition or subtraction. The design code and test bench are provided, along with simulation results verifying the logic functions of addition and subtraction.

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27 views2 pages

Aim: Sofware Used: Theory

The document describes the design of a dataflow Verilog module for a full adder/full subtractor circuit. It includes the theory of addition and subtraction using a common binary adder. The module uses a single input "ar" to determine whether to perform addition or subtraction. The design code and test bench are provided, along with simulation results verifying the logic functions of addition and subtraction.

Uploaded by

Tiger
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as RTF, PDF, TXT or read online on Scribd
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Aim : To develop dataflow verilog module for Full Adder/Full subtractor

Sofware Used : Vivado 2015.4

Theory :
The operations of both addition and subtraction can be performed by a one common binary adder
Here in this design designed module adds when ‘ar’ is high and subtracts when ‘ar’ is low.

Truth Table of Adder/Subtractor


Input Output
ar a b c sd cout
1 0 0 0 0 0
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 0 1
1 1 0 0 1 0
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 1 1
0 0 0 0 0 0
0 0 0 1 1 1
0 0 1 0 1 1
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 0
0 1 1 0 0 0
0 1 1 1 1 1

Verilog Design Code :


`timescale 1ns / 1ps
module addsub(
input a,
input b,
input c,
input ar,
output sd,
output cout
);
assign sd=a^b^c;
assign cout=(ar & (a&b|c&(a^b)))|(~ar &(~a&b|b&c|~a&c));
endmodule

RTL Schematic :
Test bench of Full Adder/ Subtractor :
`timescale 1ns / 1ps
module adsub;
reg a; reg b; reg c; reg ar ;wire sd; wire cout;
addsub uut (a,b,c,ar,sd,cout);
initial
begin
#10 a=1'b0;b=1'b0;c=1'b0;ar=1'b0;
#10 a=1'b0;b=1'b0;c=1'b1;
#10 a=1'b0;b=1'b1;c=1'b0;
#10 a=1'b0;b=1'b1;c=1'b1;
#10 a=1'b1;b=1'b0;c=1'b0;
#10 a=1'b1;b=1'b0;c=1'b1;
#10 a=1'b1;b=1'b1;c=1'b0;
#10 a=1'b1;b=1'b1;c=1'b1;
#10 a=1'b0;b=1'b0;c=1'b0;ar=1'b1;
#10 a=1'b0;b=1'b0;c=1'b1;
#10 a=1'b0;b=1'b1;c=1'b0;
#10 a=1'b0;b=1'b1;c=1'b1;
#10 a=1'b1;b=1'b0;c=1'b0;
#10 a=1'b1;b=1'b0;c=1'b1;
#10 a=1'b1;b=1'b1;c=1'b0;
#10 a=1'b1;b=1'b1;c=1'b1;
#10
$stop; end
endmodule

Simulation results:

Results :
Dataflow verilog module of Full Adder/Full subtractor designed.

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