A Novel and Efficient Low Power 8-Bit Arithmetic

Logic Unit Using FS-GDI Technique

 K.Srinivasa Rao1,Tadiboina Pavan Kumar2,Pendem Sudheer3,Gudimetla Prasad4
1
Assistant Professor,Department of ECE,Andhra Loyola Institute of Engineering and Technology,Vijayawada,A.P.,India.
2,3,4
B.Tech,Student,Department of ECE,Andhra Loyola Institute of Engineering and Technology,Vijayawada,A.P.,India
1 2 3 4
(E-mail: [email protected] ,[email protected] ,[email protected] ,[email protected] )
 Abstract— Power dissipation and area of the circuit are
the main issues in the electronics industry.This paper provides
a design of 8-Bit Arithmetic Logic Unit (ALU) using Full- (a) (b)
Swing GDI and CMOS techniques.The proposed ALU design GDI cell; (a) originally proposed, (b) standard CMOS compatible
consists of 2x1 Multiplexer, 4x1 Multiplexer and low power
Full Adder circuits to realize the arithmetic and logic However, it was proposed for fabrication in twin-well
operations. The simulation carried out using Tanner EDA Tools CMOS or silicon on insulator (SOI) processes, it allowed
V13.0. The results show that the GDI design consume less improvement in power consumption, delay and area of
power using less number of transistors, while achieving full digital circuits compared to CMOS and PTL techniques. The
swing operation compared to CMOS design.
drawback in GDI cell was it suffered from reduced voltage
swing due to threshold drops, which leads to performance
Keywords— Arithmetic Logic Unit (ALU); Gate Diffusion degradation and increasing static power dissipation.
Input (GDI); Full-Swing GDI,CMOS. To improve the output of the GDI cells Swing
restoration circuits utilized. Morgenshtein et al. [2]
I. INTRODUCTION Proposed the Modified -GDI approach, shown in Fig. 1 (b)
where the substrate terminals of NMOS and PMOS
We use a lot of portable electronic devices in our daily life,; transistors connected permanently to GND and VDD,
which are basically low power high speed VLSI circuits. respectively. This modification enables fabrication of GDI
One of these circuits is the Arithmetic logic unit (ALU) cell in standard CMOS processes which is cost efficient
which considered as an essential component in many compared to twin-well and (SOI) processes.
applications such as Microprocessor, digital signal TABLE I. DIFFERENT LOGIC FUNCTIONS REALIZATION USING GDI CELL
processing, image processing, etc.
ALU is used to perform both the logical and arithmetic
operations.The power and area are the major problems in
ALU implementation,so that we preferred low power logic
design style i.e..,GDI.But in the GDI technology,output
voltage swing degradation,fabrication complexity & power
consumption are the disadvantages.Due to this reason
Modified GDI was proposed.The Modified gate diffusion
input (MOD-GDI) technology is more efficient in terms of
power consumption,fabrication complexity and low output III.CIRCUITS IN ARITHMETIC LOGIC UNIT
voltage swing degradation when compared to GDI
technology. In this section, the Full-Swing GDI technique is used to
In this paper, an 8-bit alu is designed using an realize the circuits required to design the ALU as follows:
adder,logic block and multiplexers which are realized by the A. 2x1 Multiplexer
Full-Swing GDI technique and compared to CMOS work in
terms of power dissipation and transistor count. A multiplexer is a digital switch which chooses the
Simulations are carried out using S-EDIT,T-SPICE output from several inputs based on a select signal[4]as
and W-EDIT in the Tanner EDA Tools V13.0. shown in Fig. 2 .A 2x1 multiplexer consists 2 inputs and 1
This paper is organized as follows: Section II overviews selection line and 1 output.It is realized using GDI technique
the GDI methodology and presents its benefits and with 6 transistors.
limitations. The circuits needed to design Arithmetic logic
unit are discussed in Section III. The design of the
arithmetic logic unit is discussed in Section IV.Section V
presents simulation results and comparison. Section VI
concludes the paper.

II. GATE DIFUSSION INPUT (GDI) TECHNIQUE

GDI Technique was first proposed by Arkadiy
Morgenshtein, IdanShwartz and Alexander Fish [1] this
technique allows implementation of various complex logic
functions using only two transistors as listed in Table I. The
original GDI was based on using a simple cell, as shown in Fig. 2. Full-Swing GDI 2x1 Multiplexer
Fig. 1(a)
B. 4x1 Multiplexer
Using the previously discussed 2x1 multiplexer a
4x1 multiplexer realized as shown in Fig. 3.It consists only
of 16 transistors.A count of 3 2x1 multiplexers are required
to realize a 4x1 multiplexer.
 Each 1-Bit ALU stage consists of two 2x1 multiplexers,
two 4x1 multiplexers and one full adder cell,one logic block
and one invertor as shown in fig 6..It has a number of
selection lines(S0-S2) used to determine the operation to be
performed.S2 selects between Arithmetic and Logic
operaton.If S2=0,Arithmetic operations are realized and If
S2=1, Logical operations are realized.S0 and S1 specify the
operation.

Fig. 3. Full-Swing GDI 4x1 Multiplexer

C. Full Adder
A full adder is a combinational circuit that
performs the arithmetic sum of three input bits. It consists of
three inputs and two outputs.
Adders are widely used in digtal VLSI systems.By
improving the performance of adder cell,we can increase the Fig. 6. Schematic of 1-Bit ALU Stage
performance of the ALU.Here Adder is the key component
in the ALU to perform arithmetic operations.By realizing The first 4x1 multiplexer is responsible for the B
the full adder in less transistors reduces the area of the
ALU.Full adder is realized using 18 transistors.

Fig. 4. Full-Swing Full Adder cell operand based on the values of S0 and S1 selection lines it
E.Logic Block selects from logic 1, B, B and logic 0 to generate the
decrement,addition,subtraction and the increment operations
Logic block is used to perform logical operations respectively.
in the ALU.We can take these operations in the full adder The output of first multiplexer is given to the operand
cell also but,the circuit becomes complex and delay B input of the full adder alongside with operand A and C
becomes high.So,we take a separate block in order to reduce output of the arithmetic operation is calculated form the next
the delay time .The Logic block can mainly perform 4
operations i.e..,AND,OR,XOR and XNOR. equation.
G = A + B + CIN
For decrement operation operand A is summed with logic
Fig. 5.Logic block 1 which represents -1 in 2's complement with C = 0, this
gives G = A – 1. In addition operation operand A is summed
with operand B with C = 0, this gives G = A + B.
Subtraction is achieved using 2's complement operand A is
IV. Arithmetic Logic Unit summed with the complement of operand B with C = 1, this
An ALU is a key component in the Central Processing gives G = A +B+1 which is equivalent to A – B. And for
Unit (CPU) of a computer.It is a combinational circuit which increment operation,operand A is summed with logic 0 with
C = 1, this gives G = A + 1.
performs arithmetic operations such as addition, subtraction,
increment, decrement and logic operations such as AND, The second 4x1 multiplexer used for selection of logic
OR, XOR and XNOR . operation according to S0 and S1, while the second 2x1
The proposed design of the 8-Bit ALU multiplexer used to selects between arithmetic and Logic
consists of 2 stages, each stage is an 4-Bit ALU tand 4-bit operation. Table II summarizes the truth table of the
consists 4 stages,each stage is an 1-Bit ALU realized using proposed 8-Bit ALU.
the previously discussed circuits as follows:
 The 4-bit ALU design consists of four stages of 1- TABLE II. TRUTH TABLE OF THE PROPOSED 8-BIT ALU
bit ALU and one 2x1 Multiplexer as shown in Fig. 7.

Fig. 7. Schematic of 4-Bit ALU Stage

The proposed 8-Bit ALU consists of 2 stages of 4-Bit

ALU.It can perform a total of 12 operations as shown in
TABLE II. Out of those,8 are Arithmetic and 4 are Logical.
In Arithmetic operations,CIN plays an important role but in
in logical operations,it does not needed because logical
operations only depend upon both A and B inputs only. IV. SIMULATION RESULTS
The proposed 8-Bit ALU designed using 250nm CMOS
process.The simulations were done using the S-EDIT,T-
SPICE and W-EDIT in Tanner EDA Tools V13.0 Using
A=01111111, B=01010101 as test inputs. The proposed
design compared to CMOS design in terms of power
consumption and transistor count. Simulation results for the
proposed 8-bit ALU are shown in Table III.

TABLE III .SIMULATION RESULTS OF THE 8-BIT ALU DESIGN

No. of
Design Technology Power(μW)
Transistors

CMOS design 250nm 1194 4800.05.μW

GDI design
250nm 464 2100.40 μW

Fig. 8. Proposed 8-Bit ALU block diagram

 Fig. 9.The waveform of the Proposed 8-Bit ALU

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The analysis and simulation indicate that the proposed ALU
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