Chapter 09

Chapter 9: Operational Amplifiers
9.1 General Considerations 9.7 Common Feedback

9.2 One-Stage Op Amps 9.8 Input Range Limitations
9.3 Two-Stage Op Amps 9.9 Slew Rate
9.4 Gain Boosting 9.10 High-Slew-Rate Op Amps
9.5 Comparison 9.11 Power Supply Rejection
9.6 Output Swing 9.12 Noise in Op Amps
Copyright © 2017 McGraw-Hill Education. All rights reserved. No reproduction or distribution without the prior written consent of McGraw-Hill Education.
Op Amp Definition
• We loosely define an op amp as a “high-gain

differential amplifier.”
• Usually employed in a feedback system when
precision is a requirement.
• Applications ranging from DC generation, high-
speed amplification or filtering.
Copyright © 2017 McGraw-Hill Education. All rights reserved. No reproduction or distribution without the prior written consent of McGraw-Hill Education. 2
Op Amp Design Challenge
Three decades ago

•General-purpose blocks as an “ideal” op amp
•Design effort is to satisfy an ideal op amp
- infinite gain
- infinite input impedance
- zero output impedance
Today
•Design effort is to make trade-offs for a specific
application, often sacrificing the unimportant
aspects to improve the critical ones.
•E.g., gain error vs speed, open loop gain vs VDD
Performance Parameter
• Gain(Precision), Bandwidth(Speed): 3-dB/fu

Output Swing, Power dissipation
• Noise, Linearity, Supply Rejection, offset
• Input CM Range, Input/Output Impedance
• Large-Signal behavior (e.g. slew rate)
Example 9.1
The circuit has a nominal gain of 10. i.e.,1+R1/R2=10.

Determine the minimal value of A1 for a gain error 1%:
Solution:
Thus, A1>1000. Open-loop gain

determines precision.
Example 9.2
Assume the op amp is a single-pole voltage amplifier.

For a small step input, calculate the time required for the
output to reach within 1% and its unity-gain bandwidth
if 1+R1/R2=10 and its settling time is less than 5ns.
Solution: Speed vs. Bandwidth
Example 9.3
Explain the circuit behavior if we swap the inverting and

non-inverting inputs of the op amp.
Solution: Positive feedback destabilizes the circuit.

Output grows exponentially to non-linearity range.
One-Stage Op Amps
• Low-frequency gain:
• Bandwidth: usually proportional to 1/(CL*Rout)
• Output Swing (single-side): VDD-3Overdrive
• Mirror pole in single-ended circuit
• Power and noise: good, with four devices -> input noise
Example 9.4
Calculate the input common-mode voltage range and the

closed-loop output impedance of the unity-gain buffer.
Solution:
<Vin<
Output impedance:
The closed-loop pole is independent of open-loop
output impedance.
Telescopic Cascode Op Amps
• Low-frequency gain:
• Speed: Additional poles
• Output Swing (single-side): VDD-5Overdrive
• Mirror pole in single-ended
• Difficult to short telescopic op amp output to input
• Power and noise: good, input noise mainly has four devices
contribution
Example 9.5
For this unity-gain buffer configuration, explain in which
region each transistor operates as Vin varies from
below to above
Solution: Remedy in switched-capacitor circuit

When , M4 is in triode, others are saturated;
M2, M4 are saturated;
M2, M1 in triode,M4 is in saturation.
Example 9.6
Assuming that the op amp has a high open-loop gain,
determine the maximum allowable output swing.
Solution: ±(one threshold-one overdrive)
Telescopic Cascode Op Amps Design
• Generally, power budget determines branch current
• Gain and Output voltage swing
• Deal with
Design Procedure (Example 9.7)
-Define drain current
-Distribute overdrive voltage
-Calculate the aspect ratio
-Calculate the gain with Lmin

-Iteration by increasing W,L until
achieving gain criterion PMOS>Cascode_N>Input_N
-Finally, DC bias voltage setup
and exam residual goals
- CMFB is necessary
Linear Scaling
• How to modify design if power budget is different while all
the other specifications are the same?
• Only scale the widths of all the transistors while keeping
the lengths constant.
Example 9.6
Explain what aspects of the performance degrade for a low-
power op amp design when we scale down the transistor
width.
Solution:
(1)The speed of the op amp in driving a capacitive load
(2)The input-referred noise voltage rises by a square root
factor of scale constant. (for input device)
Gate Bias Voltage Generation
• Ensure bias voltage to track the input CM level
• Choose Mb1 to be a narrow, long, “weak” device
Folded Cascode Op Amps
Recall Folded Cascode

•Not “stack” the cascode transistor on the input device
•Consume higher power
•Output Voltage Swing: VDD-4overdrive
•Output and input could short together
Folded Cascode Voltage Gain
•Since << , thus

•
•Two or three times lower than a telescopic topology
Effect capacitance on the nondominant
pole
• At “folding point”, a large capacitance due to a
large current device M5 would be added to the total
capacitance.
NMOS vs. PMOS input
• Greater mobility from NMOS input leads to higher gain

• Lowering the pole at folding point
• PMOS input is less sensitive to flicker noise(wider WL)
Folded Cascode Properties
• Slighter Higher Output Swing than telescopic

• Higher Power dissipation, lower voltage gain, lower pole
frequency and higher noise
• Input and output can be shorted: 2overdrive from bound
• A better input CM range
Example 9.9
Design a folded- cascode op amp with an NMOS pair.

Specifications: VDD = 3V, differential output swing = 3V,
Power dissipation = 10mW, voltage gain = 2000.
Solution:
(1)Current allocation
(2)Overdrive voltage allocation
(3)Aspect ratio calculation
(4)Small-signal gain with minimal length
(5)Iteration by increase M5/M1/M4 in turns
Note that the folding point capacitance may limit here.
Low Voltage Single-ended Output
• M7 is biased at the edge of triode
Could M5 always in saturation?
• Left implementation wastes one threshold voltage
• Still, single-ended output is unfavorable due to half
output swing and a mirror pole
• Note that almost all the differential output circuits need
a CMFB
Two-Stage Op Amps
• Voltage headroom in today’s design is constrained with

low supply voltage and large output swing
• Gain:
• Output Swing: Vdd-2Overdrive
Two-Stage Op Amps with cascode
devices
• Voltage headroom in today’s design is constrained with
low supply voltage and large output swing
• Gain:
• Can we have more stages? Feedback stability limits
Two-Stage Op Amps Design
Example
9.10 the two-stage op amp for VDD = 1V, P = 1mW, a
Design
differential output swing of 1 Vpp, and a gain of 100.
Solution:
(1)Current allocation
(2)Voltage allocation:
300mV to M7, 200mV to M5,
400mV to M3, 100mV to M1
(noise and gm consideration)
(3)Calculate aspect ratio
(4)Calculate gain > 2000
Gain Boosting
• Increase the output impedance without adding more

cascode devices. But how?
• A transistor preceded by an ideal voltage amplifier exhibits
a transconductance of gmA1 and a output resistance of ro.
Gain Boosting
• Increase the output impedance without adding more
cascade devices. But how?
• First Perspective:
A degenerated transistor preceded by an ideal voltage
amplifier
In fact, the output resistance is “boosted. The headroom

is similar to a simple degenerated transistor
Example 9.11
Determine the resistance seen at the source of M2 without

considering body effect.
Solution:
Basic gain-boosted stage
• Current-Voltage feedback increase the output
impedance by a factor of A1+1, while the real gm
raised by A1 is reduced by A1+1 when feedback is
applied.
- Rout:
- Gm: gm1A1/(A1+1)~gm1
- Rp:(look above P, see example 9.11)
(<<ro1, can be neglected)

-
Regulated Cascode
Second Perspective
•Loosely view the voltage change divided by Rs and
gmroRs.
•Drain current response can be suppressed as
- Vp is constant
- Current through Rs is constant
•Vp is “pinned” to Vb by feedback regulation.
Example 9.12
Determine the small-signal values of and .
Assume is large.
Solution: Current circulates M2
Gain boosting Key
• The amplifier boosts the gm of the cascode device
• The amplifier regulates the output current by monitoring

and pinning the source voltage
Gain Boosting Circuit
Implementation
• Simplest a common-source stage
• Avoid headroom limitation, PMOS common-source stage

is better, but M3 could go in triode
• Folded-cascode inserts one more stage
Example 9.13
Determine the allowable range for Vb.
Solution:
Gain Boosting with a Differential
Pair
• One threshold higher than a simple differential circuit
• Merge two gain boosting blocks to differential one
Differential Folded Cascode Gain
Boosting
• The minimal allowable Vx,Vy is VOD12+VISS1
• The output impedance of the circuit (Example 9.14)
Gain Boosting in Signal Path and Load
• Gain boosting can be utilized in the load current source
• To allow maximum swings, A2 employs NMOS-input.
Gain Boosting Frequency Response
• Zero:
• Dominant pole:
• Non-dominant pole: Above the original-3dB bandwidth
Frequency Response Bode Plot
• Gain boosting frequency response bode plot
• Two poles, non-dominant is below the original 3dB pole
Example 9.15
Is the dominant-pole approximation valid here.
Solution:
The second term is typically much greater than unity and the
approximation is valid.
Comparison
Output Swing Calculation
• Be careful about distortion and gain error

• The maximum output amplitude that yields an acceptable
distortion or gain error
• Apply a growing sinusoid wave, monitor the resulting output,
and calculate the maximum allowable gain
Common-Mode Feed Back
• Vcm(in) and Vcm(out):
Basic Concepts
• In fully-differential op amps, the output CM level is usually

not well defined.
- Case 1: , Vx,Vy decreases, Iss triode;
- Case 2: In reverse, Vx,Vy increases, M3,M4 triode.
Basic Concepts
• In high-gain amplifiers, CMFB balances the PMOS and

NMOS current mismatches, thus avoid driving one of them
into triode region.
• Differential feedback cannot define CM level
• In simulation, CM may be well-defined around half VDD, yet
in real world, random mismatches and device variations
would degrade CM easily without CMFB.
Example 9.16
Consider the telescopic op amp below. Suppose M9 suffers
from a 1% current mismatch with respect to M10, producing
Iss = 2.97 mA rather than 3 mA. Assuming perfect matching
for the others. Explain what happens in the circuit.
Solution:
Output voltage error: =3.99V
Vx, Vy must rise so much that
M5, M6, M7, M8 go to triode,
yielding ID7 = 1.485 mA.
Current mismatch is largely

depended on different drain-
source voltage.
Conceptual topology
• Measure output CM level;

• Compare with a reference;
• Apply the error to correct the level.
CM Sensing Techniques
• Resistive sensing
- large R1,R2 to avoid loading effect
- large chip area and parasitic capacitance
- reduce frequency performance
• Source follower sensing

- lose one Vth in swing
- large R1, I1 to avoid “starved”
• Capacitive sensing
- Switched-capacitor
• Deep triode sensing

- Rtot ~ vout1+vout2
- Rtot has no relationship
with differential voltage
- may go to saturation region
Example 9.17
A student simulates the step response of a closed-loop op
amp circuit and observes the output waveforms shown in
below. Explain why Vout1 and Vout2 do not change
symmetrically.
Solution:
As evident from waveforms, the output CM levels change
from t1 to t2, indicating CM sensing mechanism is
nonlinear. For example, if M7 or M8 in last slide does not in
deep triode at t2, the CM level would change because now it
is a function of differential output.
• Differential pair sensing

- by small signal analysis
- Under Large swings situation, sensing is not valid due to
large non-linearity.
CM Feedback Techniques
• Control cascade current source
• Control tail current source
• Deep triode sensing feedback
- Limited headroom
- Large C
- Device variation
• Deep triode folded-cascade sensing feedback
Example 9.18
Determine the sensitivity of Vout,CM to Vb, i.e, dVout,CM/dVb.
Solution:
CMFB small signal analysis
Maximize Vds7,8 for Sensitivity
• Modification of deep triode sensing feedback
• The output level is relatively independent of device

parameters and lowers sensitivity of Vb
• Modification of deep triode sensing feedback
• M17, M18 reproduces the drain of M15 a voltage equal to the

source voltage of M1 and M2
• Another type of CM feedback topology

• Diode-connected loads’ output CM level is well-defined
• Differential small signal gain
• Common-mode work as a diode-connected
• Low supply voltage design
Example 9.19
Determine the maximum allowable output swings.
Solution:
Each output can fall to two overdrive voltages above ground if
Vin,CM is chosen to place Iss at the edge of the triode region.
The highest level allowed at the output is equal to the output
CM level at P plus |Vth3,4| (by selecting suitable RF). Thus,
output swing is VDD-3Vov.
(RF is small, not like previous setup)
Example 9.20
Facing voltage headroom limitations, a student constructs the
circuits below. Determine the small-signal gain from the input
CM level to the output CM level.
Solution:
(A poor CMRR)
CMFB in Two-Stage Op Amps
• CMFB around second stage (not good)

- May establish a current beyond nominal value
• CMFB from second stage to first stage
- Global loop control of both stages
CMFB from Second to First Stage
• CMFB from second stage to first stage limitation

- 3 or 4 poles, which makes it difficult for the loop stable
CMFB at both Stages
• All the drain currents are copied from Iss
• The differential voltage gain is equal to
Example 9.21
For the below design explain why the output CM level is
inevitably well below VDD/2 and hence the output swings
are limited. Devise a solution.
Solution:
The output CM is equal to VG7,8, which is only slightly
greater than one threshold. The issue can be resolved by
drawing a small current from node Q. It can be upwards to
desired output and the device is still in saturation.
CMFB for Cascode First Stage
• First stage use deep triode feedback loop to avoid loading.

• Achieving high gain while not precise
Input Range Limitations
• Input common-mode level may need to vary over a wide
range, e.g. ADC input comparator.
• Input swing limits the total range sometimes.
• In the below single-end unity-gain buffer the input CM
minimal voltage is VGS1,2+VISS, which is one threshold
greater than 2Vov in the output CM.
Extension of Input Range
• Incorporate both NMOS and PMOS differential pair to keep a
necessary transconductance
• The transconductance variation should be concerned
• Gain, speed and noise may vary
Slew Rate
• In a linear circuit, the slope of the step depends on final
output value
• The observation applies to linear feedback system
Slew Rate
• In a realistic case, with large input steps, the output
displays a linear ramp having a constant slope. The slope of
ramp is the “slew rate”.
• It seems that the maximum current to charge the load
capacitance is limited.
• Nonlinear behavior. Reduce speed and increase distortion.
• Increase SR would consume power and wider device
Slew Rate Example
• A small step rises Vout by and hence adjusts through
R1, R2 negative feedback circuit.
• When M1 experiences a large step, M2 turns off. Thus, CL is
charged by a constant current ISS.
• Feedback is broken but after M2 turns on, the circuit returns
to a linear operation.
Example 9.22
(a)Determine the small-signal step response of the circuit.
(b)Calculate the positive and negative slew rates.
Solution:
Slew Rate of Telescopic Op Amp
• Each side appears a ramp with slope equal to
• The total slew rate for Vout1- Vout2 equal to
Slew Rate of Folded-cascode Op
Amp
• Yield a slew rate of if
• Otherwise, M3 turns off and tail current source enters the
triode region. The settling time increases.
Clamp transistor
• Limit Vx,Vy to produce large different voltage
• More aggressive design, Vx,Vy higher than VDD-VTHN
Example 9.23
As Vout rises, so does Vx, eventually turning M2 on. As ID2
increases from zero, the plot becomes linear. Considering M1
and M2 becomes linear if difference between their drain current
is less than
Calculate the time to linear.
Solution:
High-Slew-Rate Op Amp
• Slew rate is limited by power consumption
• The trade-off could be mitigated if the capacitor could
be charged to a desired value quickly. And the voltage
falls back to original value.
• Complementary topology jumps fast but suffer from
poor power supply rejection
Push-Pull Stages
• Use current-mirror. E.g. If Vin+ jumps down, and Vin- jumps
up then
- M5 draws less current, lowering ID4;
- M3, M6 draws more current;
- M7 draws more current, raising ID2;
- M1 draws less current, charging CL.
Push-Pull Stages
• Improve the input common-mode rejection by adding tail
current sources to build differential circuits
• The differential slew rate is
• SR increases with a around twofold power penalty
Example 9.24
Calculate the small-signal voltage gain of the class-AB op amp
shown below.
Solution:
Frequency Response and Mirror
Pole
• It is not possible to equate zero and pole
• Raise SR would decrease mirror pole frequency
Two-Stage Op Amp with High SR
• Voltage Gain:
• Slew Rate
- If P is low capacitance, it is “agile” enough to go upon
to VDD, thus providing a large SR.
Power Supply Rejection
• Power line contains noise
• PSRR(power supply rejection ration):
- Gain from input to output divided by the gain from
supply to the output
• At low frequency
Example 9.25
Calculate the low-frequency PSRR of the feedback circuit
shown below
Solution:
Feedback reduce the same and PSRR is

relatively constant.
Noise in Telescopic Op Amp
• At low frequency the cascode devices contribute

negligible noise
Noise in Folded-Cascode Op Amp
• At low frequency the cascode devices contribute

negligible noise
Noise in two-stage Op Amp
• The noise in the second stage contributes negligible

noise
Example 9.26
A simple amplifier is constructed below. Note that the first
stage incorporates diode-connected – rather than current-
source loads. Assuming all the transistors in saturation.
(W/L)1=50/0.6 (W/L)3=10/0.6 (W/L)5=20/0.6 (W/L)7=56/0.6
Solution:

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Chapter 9: Operational Amplifiers

9.1 General Considerations 9.7 Common Feedback

• We loosely define an op amp as a “high-gain

Three decades ago

• Gain(Precision), Bandwidth(Speed): 3-dB/fu

The circuit has a nominal gain of 10. i.e.,1+R1/R2=10.

Thus, A1>1000. Open-loop gain

Assume the op amp is a single-pole voltage amplifier.

Solution: Speed vs. Bandwidth

Explain the circuit behavior if we swap the inverting and

Solution: Positive feedback destabilizes the circuit.

Calculate the input common-mode voltage range and the

Solution: Remedy in switched-capacitor circuit

Solution: ±(one threshold-one overdrive)

-Calculate the gain with Lmin

Recall Folded Cascode

•Since << , thus

• Greater mobility from NMOS input leads to higher gain

• Slighter Higher Output Swing than telescopic

Design a folded- cascode op amp with an NMOS pair.

Note that the folding point capacitance may limit here.

• Voltage headroom in today’s design is constrained with

• Can we have more stages? Feedback stability limits

• Increase the output impedance without adding more

In fact, the output resistance is “boosted. The headroom

Determine the resistance seen at the source of M2 without

(<<ro1, can be neglected)

Solution: Current circulates M2

• The amplifier boosts the gm of the cascode device

• The amplifier regulates the output current by monitoring

• Avoid headroom limitation, PMOS common-source stage

• Non-dominant pole: Above the original-3dB bandwidth

• Be careful about distortion and gain error

• Vcm(in) and Vcm(out):

• In fully-differential op amps, the output CM level is usually

• In high-gain amplifiers, CMFB balances the PMOS and

Current mismatch is largely

• Measure output CM level;

• Source follower sensing

• Deep triode sensing

• Differential pair sensing

• Control tail current source

• Deep triode folded-cascade sensing feedback

Maximize Vds7,8 for Sensitivity

• Modification of deep triode sensing feedback

• The output level is relatively independent of device

• Modification of deep triode sensing feedback

• M17, M18 reproduces the drain of M15 a voltage equal to the

• Another type of CM feedback topology

• CMFB around second stage (not good)

• CMFB from second stage to first stage limitation

• First stage use deep triode feedback loop to avoid loading.

• The observation applies to linear feedback system

Feedback reduce the same and PSRR is

• At low frequency the cascode devices contribute

• At low frequency the cascode devices contribute

• The noise in the second stage contributes negligible

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