William Stallings - Operating Systems - Internals and Design Principles-Pearson Education Limited (2018)
William Stallings - Operating Systems - Internals and Design Principles-Pearson Education Limited (2018)
William Stallings - Operating Systems - Internals and Design Principles-Pearson Education Limited (2018)
Digital Systems
Lecture # 7
Summary of Properties of Minterms
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Sum of Products
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Sum of minterms vs. Sum of Products
Sum of minterms
F Y XYZ XY
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Sum of Products Implementation
Sum of products
F Y XYZ XY
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2-level vs 3-level implementation
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2-level vs 3-level implementation
AB + CD + CE can be
Also expressed as
AB + C(D+E)
What’s best?
• Hard to answer!!
• More gate delays?
• But maybe we only have 2-input gates
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Circuit Cost
For a circuit, we will define a COST. We will ignore NOT gates at the
inputs of a circuit; all other gates count as 1 and every gate input will count
as 1.
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Product of Maxterms
We can also express F as AND of all
rows that should evaluate to 0
F M1 M 3 M 4 M 6
F ( X , Y , Z ) M (1,3,4,6)
F ( X Y Z )( X Y Z )
( X Y Z )( X Y Z )
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Product of Sum (POS)
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Product of Sum (POS) implementation
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Circuit Optimization
Goal: To obtain the simplest
implementation for a given function
Optimization is a more formal approach
to simplification that is performed using
a specific procedure or algorithm
Optimization requires a cost criterion to
measure the simplicity of a circuit
Distinct cost criteria we will use:
• Literal cost (L)
• Gate input cost (G)
• Gate input cost including inverters (GN)
Circuit Optimization
Literal Cost
Literal – a variable or its complement
Literal cost – the number of literal
appearances in a Boolean expression
corresponding to the logic circuit diagram
Example: Boolean expressions for F
• F=BD+ABC+ACD L=8
• F=BD+ABC+ABD+ABC L = 11
• F = (A+B)(A+D)(B+C+D)(B+C+D) L = 10
• Which solution is best? First solution is best
Circuit Optimization
Gate Input Cost
Gate Input Cost: Count of total number of inputs to the
gates in the logic circuit implementation
Two gate input costs are defined:
G = Count of gate inputs without counting Inverters
GN = Count of gate inputs + count of Inverters
For SOP and POS equations, the gate input cost can be
found from the Boolean expression by finding the sum of:
• All literal appearances
• Number of terms excluding single literal terms (added to G)
• Number of distinct complemented single literals (added to GN)
Example:
L = 8 G = L+3 = 11
• F=BD+ABC+ACD
GN = G+3 = 14
Circuit Optimization
Cost Criteria (continued)
Example 1: GN = G + 2 = 9
L= 5
F=A +BC + BC
G=L+2= 7
B
C
A F
Circuit Optimization
Cost Criteria (continued)
Example 2: A
B
F = A B C + AB C C
L = 6 G = 8 GN = 11 F
F = (A + C)( B + C)( A + B)
L = 6 G = 9 GN = 12
Same function and same A
literal cost B
But first circuit has better C
gate input count and better F
gate input count with NOTs
Select first circuit!
Circuit Optimization
Cost Criteria Summary
Literal Count:
• Simple to evaluate by counting all literals
• However, does not represent circuit complexity
accurately in all cases
Gate Input Cost (or Count):
• Good measure of logic implementation
• Proportional to the number of transistors and
wires used in the implementation
• Important when measuring cost of circuits with
more than two levels
Circuit Optimization
Boolean Function Optimization
Minimizing the gate input (or literal) cost of a
Boolean equation reduces the circuit cost
We choose gate input cost
Boolean Algebra and graphical techniques are tools to
minimize cost criteria values
Some important questions:
• When do we stop trying to reduce the cost?
• Do we know when we have a minimum cost?
Treat optimum or near-optimum cost functions
for two-level (SOP and POS) circuits first
Introduce a graphical technique using Karnaugh maps
(K-maps for short)
Circuit Optimization
Karnaugh Map (K-map)
A K-map is a collection of squares
• Each square represents a minterm
• The collection of squares is a graphical representation of a
Boolean function
• Adjacent squares differ in the value of one variable
• Alternative algebraic expressions for the same function are
derived by recognizing patterns of squares
Circuit Optimization
Some Uses of K-Maps
Provide a means for:
• Finding optimum or near optimum
SOP and POS standard forms
Two-level AND/OR and OR/AND circuits
for functions with small numbers of variables
• Visualizing concepts related to manipulating
Boolean expressions, and
• Demonstrating concepts used by computer-aided
design programs to simplify large circuits
Circuit Optimization
Karnaugh Maps
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Examples
F XY XY XY X Y
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Simplification using Boolean
Algebra
F XY XY XY
XY X (Y Y )
XY X (1)
X Y
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Three-Variable Map
Eight minterms
Look at encoding of columns and rows
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Simplification
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How to obtain a simplified expression?
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Example
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0 F XY XY
1 1 1 0
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Another Example
On a 3-variable K-Map:
• One square represents a minterm with 3 variables
Circuit Optimization