Chapter 4: Interfacing Memory

4.1 Interfacing Memory

While executing a program, the microprocessor needs to access memory
frequently to read instruction codes and data stored in memory and the interfacing
circuit enables that access.
4.1.1Memory Structure and Its requirements
Read/Write Memory (R/WM) is a group of registers to store binary information. Fig 1
shows a typical R/W memory chip, it has 1024 registers, each of which can store 8 bits
indicated by 8 I/O lines.
1) An address should be placed on the address lines. The low-order address lines
are decoded by the internal decoder of the memory chip, and the addressed
register is identified.
2) The high-order address should be decoded to generate a Chip Select signal,
and the memory chip is selected by asserting the Chip Select CS low.
3) To read from the addressed register, the RD should be asserted low to
enable the output buffer, and then the data byte from the register will be placed
on the I/O lines.
4) To write into the addressed register, the WR should be asserted low to
enable the input buffer, and then data bits from the data lines are stored into the
register.

To read from memory, the Z80 performs the following steps:

 1. Places a 16 bit address on its address bus.
2. Asserts the MREQ to indicate that the address bus holds a valid address.
3. Asserts the RD signal low to indicate that it wants to read.
To write into memory, the Z80 performs the following steps:
1. Places a 16 bit address on the address bus.
2. Asserts MREQ and places data on the data bus.
3. Asserts WR signal.
4.1.2 Basic Concepts in Memory Interfacing
The primary function of memory interfacing is to allow the microprocessor to read
from and write into a given register of memory chip.
1. Be able to select the chip
2. Identify the register
3. Enable the appropriate buffer.

4.1.3 Address Decoding

 The process of address decoding should result in identifying a register with a
given address; we should be able to generate a unique pulse for that address.

4.2 Illustrative Example

4.2.1Interfacing the 2764 EPROM
This is a memory chip commonly used in industry to develop microprocessor-
based products. This is an 8k (8192  8) memory chip with 8 data lines and is housed
in a 28-pin package.
Address Range and Memory Map
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 0000H
MSEL 0   
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 = FFFFH

4.2.2 Interfacing CMOS 6116 Static R/W Memory

This is a 2k static memory chip, organized as 2048  8 format. It has 11 address
lines (A10-A0), 8 data lines and 3 control signals: CE , OE and WE (write
enable).
Memory Address Range
Assuming the “don’t care” address lines A12 and A11 are at logic 0.
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 X X 0 0 0 0 0 0 0 0 0 0 0 = 8000H
MSEL 4  
1 0 0 X X 1 1 1 1 1 1 1 1 1 1 1 = 87FFH
Designing Memory for the MCTS Project
MCTS is Microprocessor-Controlled Temperature System.

 Memory Design: Problem Statement

Given the components as listed;
1. 74LS 138 : 3 to 8 decoder
2. 2732 (4k  8) : EPROM
3. 6116 (2k  8) : CMOS R/W memory
 Circuit Analysis
1. When the logic levels of A15-A12 are all 0, and the processor asserts MREQ
to read from memory, the output O0 goes active and selects the chip. The
address range of the EPROM is as follows:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 0000H
MSEL 0  
1 1 1 1 1 1 1 1 1 1 1 1 = 0FFFH
2. The 6116 R/W memory is selected by the output signal of the decoder O 2
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = 2000H
MSEL 2  
0 1 1 1 1 1 1 1 1 1 1 1 = 27FFH

Chapter 4: Interfacing Memory

4.1 Interfacing Memory
4.1.1 Memory Structure and Its requirements
4.1.2 Basic Concepts in Memory Interfacing
4.1.3 Address Decoding
4.2 Illustrative Example
4.2.1 Interfacing the 2764 EPROM
4.2.2 Interfacing CMOS 6116 Static R/W Memory