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TDC1000, TDC1000-Q1
SNAS648B – OCTOBER 2014 – REVISED AUGUST 2015
TDC1000 Ultrasonic Sensing Analog Front End (AFE) for Level Sensing, Flow Sensing,
Concentration Sensing, and Proximity Sensing Applications
1 Features 3 Description
•
1 Automotive AEC-Q100 (TDC1000-Q1) The TDC1000 is a fully integrated analog front-end
(AFE) for ultrasonic sensing measurements of level,
• Measurement Range: Up to 8 ms fluid identification/concentration, flow, and proximity/
• Operating Current: 1.8 µA (2 SPS) distance applications common in automotive,
• Transmitter Channels TX1/TX2: industrial, medical, and consumer markets. When
paired with an MSP430/C2000 MCU, power, wireless,
– Supports Single or Dual-Transducer
and source code, TI provides the complete ultrasonic
Application sensing solution.
– Programmable Excitation: 31.25 kHz to 4 MHz,
Up to 31 Pulses TI's Ultrasonic AFE offers programmability and
flexibility to accommodate a wide-range of
• Receiver Channels RX1/RX2: applications and end equipment. The TDC1000 can
– STOP Cycle-to-Cycle Jitter: 50 psRMS be configured for multiple transmit pulses and
– Low-Noise and Programmable Gain Amplifiers frequencies, gain, and signal thresholds for use with
a wide-range of transducer frequencies (31.25kHz to
– Access to Signal Chain for External Filter 4MHz) and Q-factors. Similarly, the programmability
Design of the receive path allows ultrasonic waves to be
– Programmable Threshold Comparator for Echo detected over a wider range of distances/tank sizes
Qualification and through various mediums.
– Automatic Channel Swapping for Differential Selecting different modes of operation, the TDC1000
Time-of-Flight (TOF) Measurement can be optimized for low power consumption,
– Programmable Low Power Mode for Long TOF making it ideal for battery powered flow meters,
Measurements level instrumentation, and distance/proximity
measurements. The low noise amplifiers and
• Temperature Measurement comparators provide extremely low jitter, enabling
– Interface to Two PT1000/500 RTDs picosecond resolution and accuracy for zero and low
– RTD-to-RTD Matching Accuracy 0.02°CRMS flow measurements.
• Operating Temperature Range: -40°C to 125°C Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications
TDC1000 TSSOP (28) PW 9.70 mm × 4.40 mm
• Measurements through tanks of varying materials: TDC1000-Q1 TSSOP (28) PW 9.70 mm × 4.40 mm
– Fluid Level
(1) For all available packages, see the orderable addendum at
– Fluid Identification / Concentration the end of the data sheet.
• Flow Metering: Water, Gas, Heat
• Distance/Proximity Sensing
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TDC1000, TDC1000-Q1
SNAS648B – OCTOBER 2014 – REVISED AUGUST 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes........................................ 20
2 Applications ........................................................... 1 8.5 Programming .......................................................... 31
3 Description ............................................................. 1 8.6 Register Maps ......................................................... 32
4 Revision History..................................................... 2 9 Application and Implementation ........................ 41
9.1 Application Information............................................ 41
5 Pin Configuration and Functions ......................... 3
9.2 Typical Applications ................................................ 41
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 10 Power Supply Recommendations ..................... 51
6.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 52
6.3 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 52
6.4 Thermal Information .................................................. 5 11.2 Layout Example .................................................... 52
6.5 Electrical Characteristics........................................... 6 12 Device and Documentation Support ................. 53
6.6 Timing Requirements ................................................ 8 12.1 Device Support...................................................... 53
6.7 Switching Characteristics .......................................... 8 12.2 Documentation Support ........................................ 53
6.8 Typical Characteristics .............................................. 9 12.3 Related Links ........................................................ 53
7 Parameter Measurement Information ................ 11 12.4 Community Resources.......................................... 53
12.5 Trademarks ........................................................... 53
8 Detailed Description ............................................ 12
12.6 Electrostatic Discharge Caution ............................ 53
8.1 Overview ................................................................. 12
12.7 Glossary ................................................................ 53
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13 13 Mechanical, Packaging, and Orderable
Information ........................................................... 54
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2014) to Revision B Page
• Added PW package nomenclature throught document.......................................................................................................... 1

• Changed programmed threshold in Figure 35, Multiple Echo Receive Mode (Zoom-in) .................................................... 25
• Added trigger to START time description ............................................................................................................................ 26
• Changed notes on Figure 37, Short TOF Measurement ..................................................................................................... 27
• Changed note A on Figure 38, Standard TOF Measurement ............................................................................................. 28
• Changed note A on Figure 39, Standard TOF Measurement with Blanking Enabled ......................................................... 29
• Changed Equation 9, downstream TOF ............................................................................................................................... 48
Changes from Original (October 2014) to Revision A Page
• Added Pin Configuration and Functions section, Specifications section, Parameter Measurement Information
section, Detailed Description section, Application and Implementation section, Power Supply Recommendations
section and Layout section ..................................................................................................................................................... 1
• Changed Device and Documentation Support section .......................................................................................................... 1
2 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TDC1000 TDC1000-Q1

TDC1000, TDC1000-Q1
www.ti.com SNAS648B – OCTOBER 2014 – REVISED AUGUST 2015
5 Pin Configuration and Functions
TSSOP
28 Pin PW
Top View
RX1 1 28 TX1
RX2 2 27 TX2
VCOM 3 26 GND
LNAOUT 4 25 CLKIN
PGAIN 5 24 VDD
TDC1000
PGAOUT 6 23 VDD
COMPIN 7 22 VIO
RTD1 8 21 SDO
RTD2 9 20 SDI
RREF 10 19 CSB
CHSEL 11 18 SCLK
ERRB 12 17 RESET
START 13 16 TRIGGER
STOP 14 15 EN
Pin Functions
PIN
TYPE (1) DESCRIPTION
NAME NO.
RX1 1 I Receive input 1
RX2 2 I Receive input 2
VCOM 3 P Output common mode voltage bias
LNAOUT 4 O Low noise amplifier output (for ac decoupling capacitor)
PGAIN 5 I Programmable gain amplifier input
PGAOUT 6 O Programmable gain amplifier output
COMPIN 7 I Echo qualification and zero-crossing detector input
RTD1 8 O Resistance temperature detector channel 1
RTD2 9 O Resistance temperature detector channel 2
RREF 10 O Reference resistor for temperature measurement
CHSEL 11 I External channel selection
ERRB 12 O Error flag (open drain)
START 13 O Start pulse output
STOP 14 O Stop pulse output
EN 15 I Enable (active high; when low the TDC1000 is in SLEEP mode)
TRIGGER 16 I Trigger input
RESET 17 I Reset (active high)
SCLK 18 I Serial clock for the SPI interface
CSB 19 I Chip select for the SPI interface (active low)
SDI 20 I Serial data input for the SPI interface
SDO 21 O Serial data output for the SPI interface
VIO 22 P Positive I/O supply
VDD (2) 23, 24 P Positive supply; all VDD supply pins must be connected to the supply.
CLKIN 25 I Clock input
GND 26 G Negative supply
(1) G = Ground, I = Input, O = Output, P = Power

(2) Place a 100-nF bypass capacitor to ground in closest proximity of the pin
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 3
TDC1000, TDC1000-Q1
Pin Functions (continued)

PIN
TYPE (1) DESCRIPTION
NAME NO.
TX2 27 O Transmit output 2
TX1 28 O Transmit output 1
6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Analog supply voltage, VDD pins –0.3 6.0 V
VIO I/O supply voltage (VIO must always be lower than or equal to VDD supply) –0.3 6.0 V
(3)
VI Voltage on any analog input pin –0.3 VDD + 0.3 V
VI Voltage on any digital input pin (3) –0.3 VIO + 0.3 V
II Input current at any pin 5 mA
TJ Operating junction temperature –40 125 °C
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) When the input voltage at a pin exceeds the power supplies, the current at that pin must not exceed 5 mA and the voltage (VI) at that
pin must not exceed 6.0 V.
6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC A100-002 (1) ±2000
All pins ±500
V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC V
Q100-011 Corner pins (1, 14, 15
±750
and 28)
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Analog supply voltage, VDD pins 2.7 5.5 V
VIO Digital supply voltage, (VIO must always be lower than or equal to VDD supply) 1.8 VDD V
VI Voltage on any analog input pin GND VDD V
VI Voltage on any digital input pin GND VIO V
ƒCLKIN Operating frequency 0.06 16 MHz
TJ Operating junction temperature –40 125 °C

TDC1000, TDC1000-Q1
6.4 Thermal Information (1)

TDC1000
THERMAL METRIC TSSOP UNIT
(28 PINS) PW
RθJA Junction-to-ambient thermal resistance 83.5
RθJC(top) Junction-to-case (top) thermal resistance 29.9
RθJB Junction-to-board thermal resistance 40.8 °C/W
ψJT Junction-to-top characterization parameter 2.4
ψJB Junction-to-board characterization parameter 40.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TDC1000, TDC1000-Q1
6.5 Electrical Characteristics

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. TA = 25°C, VDD = VIO = 3.7 V, VCOM = VCM = VDD / 2, CVCOM = 10 nF (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TRANSMITTER SIGNAL PATH (TX)
HIGH VDD – 0.32 V
VOUT(TX) Output voltage swing ƒout = 1 MHz, RL = 75 Ω to VCM
LOW 0.32 V
IOUT(TX) Output drive current ƒout = 1 MHz, RL = 75 Ω to VCM 22 mARMS
ƒCLKIN = 8 MHz, divide-by-2 (programmable;
ƒOUT(TX) Output TX frequency 4 MHz
see Transmitter Signal Path)
RECEIVER SIGNAL PATH (RX)
LNA capacitive feedback, GPGA = 6 dB, ƒIN = 1
STOP cycle-to-cycle
ΔtSTOP MHz, VIN = 100 mVPP, CVCOM = 1 µF and 50 psRMS
jitter
Figure 14
LNA
Capacitive feedback, CIN = 300 pF, ƒIN = 1
GLNA LNA gain 20 dB
MHz, RL = 100 kΩ to VCM, CVCOM = 1 µF
LNA input referred Capacitive feedback, CIN = 300 pF, ƒ = 1 MHz,
enLNA 2 nV/√Hz
noise density VDD = 3.1 V, VIN = VCM, RL = ∞, CVCOM = 1 µF
Resistive feedback, RL = 1 kΩ to HIGH VCM + (VCM – 0.24) / (GLNA) V
VIN(LNA) Input voltage range
VCM, CVCOM = 1 µF LOW VCM – (VCM – 0.24) / (GLNA) V
Resistive feedback, RL = 1 kΩ to HIGH VDD – 0.24 V
VOUT(LNA) Output voltage range
VCM, CVCOM = 1 µF LOW GND + 0.24 V
Resistive feedback, RL = 1 kΩ to VCM, 100mV
SRLNA Slew rate (1) 9 V/μs
step, CVCOM = 1 µF
Capacitive feedback, ƒ = 1 MHz, RL = 100 kΩ
XTK MUX ch-to-ch crosstalk –57 dB
to VCM, CVCOM = 1 µF
Capacitive feedback, CIN = 300 pF, RL= 100 kΩ
BWLNA –3-dB bandwidth 5 MHz
to VCM, CVCOM = 1 µF
LNA input offset
VOS(LNA) Resistive mode, VIN = VCM, RL = ∞ ±320 µV
voltage
VCOM
VCOM VCOM output voltage VCM V
CVCOM = 1 µF
VCOM output error 0.5%
PGA
RL = 100 kΩ to VCM, CL = 10 pF HIGH VCM + (VCM – 0.06) / (GPGA) V
VIN(PGA) PGA input range
to GND LOW VCM – (VCM – 0.06) / (GPGA) V
GPGAMIN PGA min gain 0 dB
GPGAMAX PGA max gain DC, RL = ∞, CL = 10 pF 21 dB
ΔGPGA PGA gain step size 3 dB
GE(PGA) PGA gain error DC, GPGA = 0 dB, RL = ∞, CL = 10 pF 5%
PGA gain temperature
TCGPGA DC, GPGA = 0 dB, RL = ∞, CL = 10 pF 170 ppm/°C
coefficient
PGA input referred GPGA = 21 dB, ƒ = 1 MHz, VDD = 3.1V, VIN =
enPGA 3.1 nV/√Hz
noise density VCM, RL = ∞, CVCOM = 1 µF
RL = 100 kΩ to VCM, CL = 10 pF HIGH VDD – 0.06 V
VOUT(PGA) Output range
to GND LOW 60 mV
GPGA = 21 dB, RL = 100 kΩ to VCM, CL = 10
BWPGA –3-db bandwidth 5 MHz
pF, CVCOM = 1 µF
GPGA = 21 dB, RL = 100 kΩ to VCM, CL = 10
SRPGA Slew rate (1) 12.5 V/µs
pF, CVCOM = 1 µF
(1) The slew rate is measured from 10% to 90% and is represented by the average of the rising and falling slew rates.

TDC1000, TDC1000-Q1
Electrical Characteristics (continued)

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. TA = 25°C, VDD = VIO = 3.7 V, VCOM = VCM = VDD / 2, CVCOM = 10 nF (unless otherwise noted).
ZERO CROSS COMPARATOR
VOS(COMP) Input offset voltage (2) Referred to VCOM ±115 µV
Zero crossing
enCOMP comparator input 1 MHz 5 nV/√Hz
referred noise (2)
(2)
HYSTCOMP Hysteresis Referred to VCOM -10 mV
THRESHOLD DETECTOR
ECHO_QUAL_THLD = 0h, VCOM referred –35 mV
VTHDET Threshold level
ECHO_QUAL_THLD = 7h, VCOM referred –1.5 V
(3)
TEMPERATURE SENSOR INTERFACE
Temperature RREF = 1 kΩ, PT1000 range: –40 to 125°C (4) 1 °C
TERROR
measurement accuracy RREF = 1 kΩ, PT1000 range: –15°C to 85°C (4) 0.5 °C
Relative accuracy RREF = 1 kΩ, RRTD1 = RRTD2 = 1.1 kΩ 0.02 °CRMS
TGE Gain error 5.8 m°C/°C
POWER SUPPLY
Sleep (EN = CLKIN = TRIGGER = low) 0.61 µA
Continuous receive mode, LNA and PGA
2.8 3 mA
bypassed
IDD VDD supply current
Continuous receive mode, LNA and PGA active 6.2 7.5 mA
(5)
Temp. measurement only (PT1000 mode) 370 400 µA
Temp. measurement (PT500 mode) (6) 500 540 µA
VIO supply sleep
IIO Sleep (EN = CLKIN = TRIGGER = low) 2 nA
current (2)
DIGITAL INPUT/OUTPUT CHARACTERISTICS
Input logic low
VIL 0.2 × VIO V
threshold
Input logic high
VIH 0.8 × VIO V
threshold
SDO pin, 100-μA current 0.2 V
SDO pin, 1.85-mA current 0.4 V
Output logic low START and STOP pins, 100-μA current 0.5 V
VOL
threshold START and STOP pins, 1.85-mA current 0.6 V
ERRB pin, 100-μA current 0.2 V
ERRB pin, 1.85-mA current 0.4 V
SDO pin, 100-μA current VIO – 0.2 V
SDO pin, 1.85-mA current VIO – 0.6 V
Output logic high
VOH START and STOP pins, 100-μA current VIO – 0.5 V
threshold
START and STOP pins, 1.85-mA current VIO – 0.6 V
ERRB pin, 0-µA current VIO – 0.2 V
Maximum output
IOMAX current for SDO, 1.85 mA
START and STOP
(2) Specified by design.

(3) With ideal external components. For more detail see Temp Sensor Measurement section.
(4) PT1000 RTD approximate resistance: 800 Ω ≡ –52°C, 931 Ω ≡ –18°C, 1.10 kΩ ≡ 26°C, 1.33 kΩ ≡ 86°C and 1.48 kΩ ≡ 125°C.
(5) Specified currents include 120μA which flows through the RTD sensor in PT1000 mode (TEMP_RTD_SEL = 0).
(6) Specified currents include 240μA which flows through the RTD sensor in PT500 mode (TEMP_RTD_SEL = 1).

TDC1000, TDC1000-Q1
6.6 Timing Requirements

TA = 25°C, VDD = VIO = 3.7 V and ƒSCLK = 1 MHz (unless otherwise noted).
MIN TYP MAX UNIT
ƒSCLK Serial clock frequency 26 MHz
t1 High period, SCLK 16 ns
t2 Low period, SCLK 16 ns
t3 Set-up time, nCS to SCLK 10 ns
t4 Set-up time, SDI to SCLK 12 ns
t5 Hold time, SCLK to SDI 12 ns
t6 SCLK transition to SDO valid time 16 ns
Hold time, SCLK transition to nCS rising
t7 10 ns
edge
t8 nCS inactive 17 ns
Hold time, SCLK transition to nCS falling
t9 10 ns
edge
(1)
tr / tf Signal rise and fall times 1.8 ns
(1) The slew rate is measured from 10% to 90% and is represented by the average of the rising and falling slew rates.
SCLK
t9 t2 t1 t7
t3
CSB
t8
t4 t5
D15 D14 D0
t6
90% 90%
Prior D15 Prior D1 Prior D0
10% 10%
tr tf
Figure 1. SPI Timing Diagram
6.7 Switching Characteristics

TA = 25°C, VDD = VIO = 3.7 V, ƒCLKIN = 8 MHz.
START, STOP, ENABLE, CHSEL, RESET, CLOCKIN, TRIGGER, ERR
TX_FREQ_DIV = 2h, NUM_TX = 1 1 μs
PWSTART Pulse width for START signal TX_FREQ_DIV = 2h, NUM_TX = 2 2 μs
TX_FREQ_DIV = 2h, NUM_TX ≥ 3 3 μs
tr / tf Rise/fall time for START
20% to 80%, 20-pF load 0.25 ns
START signal
tr / tf STOP Rise/fall time for STOP signal 20% to 80%, 20-pF load 0.25 ns
Maximum CLKIN input
ƒCLKIN 16 MHz
frequency
tr / tf CLKIN CLKIN input rise/fall time (1) 20% to 80% 10 ns
TRIGGER input rise/fall
tr / tf TRIG 20% to 80% 10 ns
time (1)
(1)
tEN_TRIG Enable to trigger wait time 50 ns
TX_FREQ_DIV = 2h (see TX/RX Measurement
tRES_TRIG Reset to trigger wait time (1) 3.05 μs
Sequencing and Timing)
(1) Specified by design.

TDC1000, TDC1000-Q1
6.8 Typical Characteristics

At TA = 25°C, unless otherwise noted.
500 500
Output Impedance Magnitude (||)
Output Impedance Magnitude (|_

400 400
300 300
200 200
100 100
0 0
±100 ±100
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
Frequency (Hz) C001 Frequency (Hz) C002
VDD = VIO = 3.7V Capacitive RL = 1kΩ VDD = VIO = 3.7V Gain of 21dB RL = 1kΩ
Feedback Mode
Figure 2. LNA ZOUT vs Frequency Figure 3. PGA ZOUT vs Frequency

10 10
9 9
Input-referred Noise (nV/O,Ì
Input-referred Noise (nV/O,Ì
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
5k 50k 500k 2M 5k 50k 500k 2M
VDD = VIO = 3.1V Capacitive RL = ∞ VDD = VIO = 3.7V Gain of 21dB RL = ∞

Feedback Mode
Figure 4. LNA Input-referred Noise vs Frequency Figure 5. PGA Input-referred Noise vs Frequency
Output Voltage (250mV/DIV)
Output Voltage (250mV/DIV)
Time (1s/DIV) Time (1s/DIV)
C005 C006
VDD = VIO = 3.7V Resistive Feedback RL = 1kΩ VDD = VIO = 3.7V Gain of 21dB RL = 100kΩ
VIN = 100mV Mode fIN = 100kHz VIN = 100mV fIN = 100kHz
Figure 6. LNA Response Figure 7. PGA Response

TDC1000, TDC1000-Q1
Typical Characteristics (continued)

At TA = 25°C, unless otherwise noted.
30 30
20 20
10 10
Gain (dB)
Gain (dB)
0 0
±10 ±10
±20 ±20
±30 ±30
10k 100k 1M 10M 10k 100k 1M 10M
VDD = VIO = 3.7V Capacitive RL = 100kΩ VDD = VIO = 3.7V Gain of 21dB RL = 100kΩ
Feedback Mode
CIN = 300 pF
Figure 8. LNA Gain vs Frequency Figure 9. PGA Gain vs Frequency

20 20
18 18
16 16
14 14
Count (%)
Count (%)
12 12
10 10
8 8
6 6
4 4
2 2
0 0
100
200
300
100
200
300
0
0
-300
-200
-100
-300
-200
-100
Time (ps) C009

Time (ps) C010
VDD = VIO = 5V LNA Capacitive PGA Gain of 6dB VDD = VIO = 3.7V LNA Capacitive PGA Gain of 6dB
VIN = 100mV Feedback Mode fIN = 1MHz VIN = 100mV Feedback Mode fIN = 1MHz
(See Figure 14) Count >= 10000 TA = 25C° (See Figure 14) Count >= 10000
Figure 10. RX Jitter Histogram Figure 11. RX Jitter Histogram

20 20
18 18
16 16
14 14
Count (%)
Count (%)
12 12
10 10
8 8
6 6
4 4
2 2
0 0
100
200
300
100
200
300
0
0
-300
-200
-100
-300
-200
-100
Time (ps) C011

Time (ps) C012
VDD = VIO = 3.7V LNA Capacitive PGA Gain of 6dB VDD = VIO = 3.7V LNA Capacitive PGA Gain of 6dB
VIN = 100mV Feedback Mode fIN = 1MHz VIN = 100mV Feedback Mode fIN = 1MHz
TA = -40C° (See Figure 14) Count >= 10000 TA = 125C° (See Figure 14) Count >= 10000
Figure 12. RX Jitter Histrogam Figure 13. RX Jitter Histogram

TDC1000, TDC1000-Q1
7 Parameter Measurement Information
CIN = 300 pF
INPUT LNAIN
CF1 = 1 nF
LNAOUT PGAIN
RF1 = 1 N CF2 = 51 pF
PGAOUT COMPIN
CF3 = 51 pF RF2 = 5.1 N
GND VCOM
Figure 14. External Circuits for Jitter Measurement

TDC1000, TDC1000-Q1
8 Detailed Description
8.1 Overview
The main functional blocks of TDC1000 are the Transmit (TX) and the Receive (RX) Channels. The transmitter
supports flexible settings for driving various ultrasonic transducers, and the receiver provides configurable blocks
with a wide range of settings for signal conditioning in various applications. The receive signal chain consists of
an LNA (Low Noise Amplifier), a PGA (Programmable Gain Amplifier), and two auto-zeroed comparators for
echo qualification and STOP pulse generation.
The TDC1000 provides three modes of operation: Mode 0, Mode 1 and Mode 2. Each mode is intended for one
or more applications such as flow/concentration measurement, container level measurement, proximity detection,
distance measurement, and a range of other applications where a precision measurement of Time-of-Flight
(TOF) is required.
A measurement cycle is initiated with a trigger signal on the TRIGGER pin of the device. After a trigger signal is
asserted, an output pulse is generated on the START pin. This signal is used as the time reference to begin a
TOF measurement. The transmitter generates programmable TX pulses, synchronous to the rising edge of the
START pulse, to drive an ultrasonic transducer and generate an ultrasonic wave that is shot through an acoustic
medium. The receiver detects the ultrasound wave that traveled through the medium and generates STOP
signals. Whether the ultrasound wave is received directly or from a reflection will depend on the system
configuration. The STOP signals are used by an external Time-to-Digital Converter (TDC), which functions as a
very accurate stopwatch. The system must include a TDC to measure the TOF based on the interval between
the START and STOP pulses. In some applications with medium-range accuracy requirements (ns range), a
microcontroller can be used to measure the TOF duration. In applications with high-range accuracy requirements
(ps range), TI recommends using the TDC7200 time-to-digital converter to measure the TOF duration.
In each application, the TDC1000 has to be configured by a serial interface (SPI) for one of the three modes of
operation available. In addition, the device must be programmed to various application-specific parameters that
are explained in the following sections.
8.2 Functional Block Diagram

TRIGGER
RESET
CHSEL
CLKIN
ERRB
SCLK
VDD
VDD
SDO
CSB
VIO
SDI
EN
TX1
Tx Clock SM Control Serial
Generator Divider Unit Interface
TX2
MUX
Channel
START
Select enable
RX1 Event
DAC
MUX
MUX
± + Manager STOP
RX2 LNA PGA Threshold Detect
+ VCOM ±
20 dB 0 to 21 dB
VCOM
Analog Bias Temp. Sense
TDC1000
Zero-Cross Detect
GND
LNAOUT
PGAIN
PGAOUT
COMPIN
VCOM
RREF
RTD2
RTD1

TDC1000, TDC1000-Q1
8.3 Feature Description

8.3.1 Transmitter Signal Path
The Transmitter (TX) path consists of a Clock Divider block and a TX Generator block. The clock divider allows
the TDC1000 to divide the clock source that is connected to the CLKIN pin down to the resonant frequency (ƒR)
of the transducer used. The clock divider allows division factors in powers of 2. The division factor of the clock
divider can be programmed with the TX_FREQ_DIV field in the CONFIG_0 register.
The TX Generator block can drive a transducer with a programmable number of TX pulses. The frequency of
these pulses is defined as ƒCLKIN/(2TX_FREQ_DIV+1), and should match the ƒR of the transducer. The number of
pulses is configured by programming the NUM_TX field in the CONFIG_0 register.
For example, for ƒCLKIN = 8 MHz and TX_FREQ_DIV = 2h (divide by 8), the divided clock frequency is 1 MHz.
In addition to the programmable number of pulses, the TX Generator also provides options to introduce a 180⁰
pulse shift at pulse position n or damping the last TX pulse. In some situations, damping can reduce the ringing
of the transducer for very short TOF measurements. These features are further described in the TRANSMIT
Operation section of the datasheet.
8.3.2 Receiver Signal Path

The RX signal path consists of a channel selection multiplexer followed by an LNA. The output of the LNA can
then be sent to the PGA for additional amplification if needed. Finally, the signal is fed into a set of comparators
which generate pulses on the STOP pin based on the programmed threshold levels. The block diagram for the
receiver path can be seen in Figure 15.
If the 20-dB to 41-dB of gain provided by the TDC1000 is insufficient, additional gain can be added prior to the
COMPIN pin. Likewise, with a strong received signal, if the gain from the LNA or PGA is not be needed, they can
be bypassed and the transducer signal could be directly connected to the COMPIN pin.
A band-pass filter centered on the transducer’s response can be used between each stage of the receiver path
to reduce the noise; note that the inputs of the LNA, PGA and comparators should be biased to the VCOM pin’s
potential. The comparators connected to the COMPIN pin are used for echo qualification and generation of
STOP pulses that correspond to the zero-crossings of the echo signal. The STOP pulses are used with a START
pulse to calculate the TOF of the echo in the medium.
Channel
Select enable
DAC Event
MUX
MUX
± + Manager
Threshold Detect STOP
LNA PGA
+ VCOM ±
20dB 0 to 21 dB
VCOM
Analog Bias Temp. Sense
TDC1000
Zero-Cross Detect
GND
LNAOUT
PGAIN
PGAOUT
COMPIN
VCOM
RREF
RTD2
RTD1
Figure 15. TDC1000 Receiver Path

TDC1000, TDC1000-Q1
Feature Description (continued)

8.3.3 Low Noise Amplifier (LNA)
The LNA in the TDC1000’s front-end limits the input-referred noise and ensures timing accuracy for the
generated STOP pulses. The LNA is an inverting amplifier designed for a closed-loop gain of 20 dB with the aid
of an external input capacitor or resistor, and it can be programmed for two feedback configurations. The band-
pass configuration, referred to as capacitive feedback mode, must be combined with an input capacitor. The low-
pass configuration, referred to as resistive feedback mode, must be combined with an input resistor. The
recommended values for the input components are 300 pF and 900 Ω respectively.
The LNA can be configured in capacitive feedback mode for transducers with resonant frequencies in the order
of a couple of MHz. This is done by clearing the LNA_FB bit in the TOF_1 register to 0. As shown in Figure 16,
the external capacitor, CIN, should be placed between the transducer and the corresponding input pin. This
provides an in-band gain of CIN/CF, where CF is the on-chip 30-pF feedback capacitor. Provided that CIN = 300
pF, the in-band gain of the LNA circuit is:
CIN 300 pF
Gaininband 10
CF 30 pF (1)
CF 30 pF
RF 9 lQ
MUX
CIN
Transducer 300 pF RX1
t
LNA LNAOUT
RX2
+
300 pF VCOM
CIN
Figure 16. LNA Capacitive Feedback Configuration
The capacitive feedback configuration of the LNA has a band-pass frequency response. The high-pass corner
frequency is set by the internal feedback components RF (9 kΩ) and CF (30 pF), and is approximately 590 kHz.
The in-band gain is set by the capacitor ratio and the LNA’s 50-MHz gain-bandwidth product sets the low-pass
corner of the frequency response. For example, an in-band gain of 10 results in a bandpass response between
590 kHz and 5 MHz.
The LNA can be configured in resistive feedback mode for transducers with resonant frequencies in the order of
a couple of hundreds of kHz. This is done by setting the LNA_FB bit in the TOF_1 register to 1. In this
configuration, the internal feedback capacitor CF is disconnected (see Figure 17), and the DC gain of the LNA
circuit is determined by the ratio between the internal feedback resistor RF (9 kΩ) and an external resistor RIN.
For RIN = 900 Ω, the gain of the circuit is 10.
RF 9 lQ
MUX
RIN
Transducer 900 Q RX1
t
LNA LNAOUT
RX2
+
900 Q VCOM
RIN
Figure 17. LNA Resistive Feedback Configuration
The LNA can be bypassed and disabled by writing a 1 to the LNA_CTRL bit in the TOF_1 register.

TDC1000, TDC1000-Q1
Feature Description (continued)

8.3.4 Programmable Gain Amplifier (PGA)
The PGA, shown in Figure 18, is an inverting amplifier with an input resistance of RIN = 500 Ω and a
programmable feedback resistor RFB that can be programmed to set a 0-dB to 21-dB gain in 3-dB steps. This
can be done by programming the PGA_GAIN field in the TOF_1 register. The bandwidth of the PGA is scaled
based on its programmed gain. The typical bandwidth of the PGA with a 100-kΩ load to VCM and a 10-pF
capacitor to ground are listed in Table 1.
Table 1. Typical PGA Bandwidth

PGA_GAIN (Hex) Gain (dB) Bandwidth (MHz)
0h 0 19.0
1h 3 16.8
2h 6 14.4
3h 9 12.3
4h 12 10.0
5h 15 8.2
6h 18 6.6
7h 21 5.0
The PGA can be bypassed and disabled by writing a 1 to the PGA_CTRL bit in the TOF_1 register. The output of
the PGA should not be loaded directly with capacitances greater than 10 pF.
RFB
PGA_IN RIN 500 :

PGA_OUT
PGA
VCOM
Figure 18. TDC1000 Programmable Gain Amplifier
8.3.5 Receiver Filters

It is recommended to place two filters in the RX path to minimize the receive path noise and obtain maximum
timing accuracy. As shown in Figure 19, one filter is placed between the LNAOUT and the PGAIN pins, and
another filter is placed between the PGAOUT and the COMPIN pins.
With an in-band gain of 10, the LNA has a bandwidth of 5 MHz. For most applications, a low-pass filter between
the LNAOUT and PGAIN pins is sufficient.
As shown in Figure 19, the second filter stage can use a cascade of a low-pass filter (RF1 and CF3) followed by a
high-pass filter (CF2 and RF2) referenced to VCOM. Design of the filter is straightforward. The RF1 and CF2 can be
chosen first. A reasonable set of values for RF1 and CF2 could be: RF1 = 1 kΩ ± 10% and CF2 = 50pF ± 10%.
Given the center frequency of interest to be ƒC and the filter bandwidth to be ƒB, the value of CF3 can be
calculated as:
1
CF3
2 S R F1 fC fB (2)
RF2 and CF2 determine the high-pass corner of the filter. RF2 should be referenced to VCOM to maintain the DC
bias level at the comparator input during the echo receive time. For values of RF2 larger than RF1, there will be
limited loading effect from the high-pass filter to the low-pass filter resulting in more accurate corner frequencies.
The chosen values shown in the figure below result in a high-pass corner frequency of about 600 kHz and a low-
pass corner frequency of about 3 MHz.

TDC1000, TDC1000-Q1
More complex filters can be used; external gain is acceptable if the signal amplitude is too low. If the pass-band
of the filter is wider than an octave, it is recommended to use a filter design which has linear group delay.
CF1 = 1 nF RF1 = 1 N CF2 = 50 pF

LNAOUT PGAIN PGAOUT COMPIN
CF3 = 53 pF RF2 = 5 N
GND VCOM
Figure 19. Filter for a 1-MHz Operation
8.3.6 Comparators for STOP Pulse Generation

The STOP pulse generation block of the TDC1000 contains two auto-zeroed comparators (a zero-cross detect
and a threshold-detect comparator), a threshold setting DAC, and an event manager.
Comparator auto-zero periods occur at the beginning of every TOF receive cycle. During these periods, the
comparator’s input offset is stored in an internal 2.5-pF capacitor, and it is subtracted from the input signal during
the echo processing phase. The duration of auto-zero period is configured with the AUTOZERO_PERIOD field
located in the CLOCK_RATE register.
Zero Cross Detect

VCOM ±
COMPIN +
STOP
Threshold
Detect Event Manager
ECHO_QUAL_THLD ±
+
DAC VTHLD
± +
RECEIVE_MODE
NUM_RX
Figure 20. STOP Pulse Generation Circuit
8.3.6.1 Threshold Detector and DAC

The threshold detect comparator in Figure 20 compares the echo amplitude with a programmable threshold level
(VTHLD) controlled by a DAC. The DAC voltage is set by the ECHO_QUAL_THLD field in register CONFIG_3 and
provides 8 programmable threshold levels, VTHLD. The typical levels are summarized in Table 2:
Table 2. Echo Qualification Threshold Levels

ECHO_QUAL_THLD 0h 1h 2h 3h 4h 5h 6h 7h
Typical VTHLD (mV) –35 –50 –75 –125 –220 –410 –775 –1500
8.3.6.2 Zero-cross Detect Comparator

The zero-cross detect comparator compares the amplified echo signal at COMPIN with its reference voltage,
which is VCOM. As shown in Figure 21, the comparator produces a low-to-high transition when the amplitude of
the echo signal rises above VCOM. The comparator produces a high-to-low transition when the echo amplitude
falls below VCOM – VHYST. The built-in negative-sided hysteresis of 10 mV in reference to VCOM ensures accurate
zero-cross time instances associated with the rising edges of the echo signal and immunity of the comparator
output to noise.

TDC1000, TDC1000-Q1
Signal into
COMPIN
VCOM
VHYST = 10 mV
Zero Cross
Detect Output
Figure 21. Zero-Cross Detector Output Signal
The output of the zero-cross detect comparator is passed to the event manager, where depending on the
decision of the threshold-detect comparator.
8.3.6.3 Event Manager

The event manager is a digital state machine in the STOP pulse generation circuit of the TDC1000. The event
manager controls the maximum number of STOP pulses to generate on the STOP pin and the receive mode for
the STOP pulse generation. The number of STOP pulses is configured in the NUM_RX field in the CONFIG_1
register. The receive mode is selected in the RECEIVE_MODE bit of the CONFIG_4 register. See sections
Single Echo Receive Mode and Multiple Echo Receive Mode for details about the receiver modes of the
TDC1000.
An example for NUM_RX = 2h and RECEIVE_MODE = 0 is shown in Figure 22. When the echo signal amplitude
exceeds values smaller than VTHLD, the threshold detect comparator indicates to the event manager to qualify the
next zero-cross event as valid. When the qualified zero-cross is detected by the zero-cross detect comparator,
the event manager passes the pulse to the STOP pin until the number of receive events programmed in
NUM_RX is reached.
STOP
COMPIN
VCOM
VTHLD
GND
Passes VTHLD Passes VTHLD
Qualified for Qualified for

zero-cross zero-cross
Figure 22. Signal Qualification, Zero-cross Detection and STOP Pulse Generation

TDC1000, TDC1000-Q1
8.3.7 Common-mode Buffer (VCOM)

The output of the internal common-mode buffer is present at the VCOM pin. This pin should be bypassed to
ground with a low-leakage 10-nF capacitor and it should not be loaded with more than 20 µA. The common-
mode buffer can be disabled with the VCOM_SEL bit in the CONFIG_2 register. If disabled, an external
reference voltage must be applied to the VCOM pin.
During a time-of-flight measurement, the common-mode reference will take approximately 16 µs to settle if
starting from zero initial conditions. Using a larger capacitor will increase the settling time of the internal common-
mode reference. The implications of a larger VCOM capacitor are further explored in the Common-mode
Reference Settling Time section.
8.3.8 Temperature Sensor
TDC1011 MEAS_MODE
tof_start
MUX START
MEAS_MODE
tof_stop
MUX STOP
Temp
Sensor
RTD1
RREF
RTD1
(external)
RTD2
RTD2
(external)
Figure 23. Temperature Sensor Measurement
Accurate measurements of flow, level, and concentration require compensation for the temperature dependency
of the speed of sound in the medium. The TDC1000 provides two temperature sensor connections, allowing to
measure up to two locations with RTDs, as shown in Figure 23.
The temperature sensor block supports PT1000 or PT500 sensors. The type of RTD used must be selected in
the TEMP_RTD_SEL bit of the CONFIG_3 register. The system requires a temperature-stable external reference
resistor (RREF). If the RTD type is PT500, then RREF should be 500 Ω. If the RTD type is PT1000, then RREF
should be 1 kΩ. The reference resistor needs to have either a low temperature coefficient or be calibrated for
temperature shift.
The logic timing in a temperature measurement is controlled by the TEMP_CLK_DIV bit in the CONFIG_3
register. As shown in Figure 24, the external clock can be divided by 8 or by the value resulting from the
TX_FREQ_DIV field configuration in the CONFIG_0 register. It is recommended to operate the temperature
measurement block at frequencies of 1 MHz or less.

TDC1000, TDC1000-Q1
0x03[4] ± TEMP_CLK_DIV
y8
0 ¦TEMP 1
CLKIN ¦CLKIN TTEMP =
1 ¦TEMP
TX_FREQ_DIV+1
y2
0x00[7:5] ± TX_FREQ_DIV
Figure 24. Timing Source for the Temperature Measurement
8.3.8.1 Temperature Measurement with Multiple RTDs

The temperature measurement mode is selected by setting the MEAS_MODE bit in the CONFIG_2 register to 1.
A temperature measurement is started by sending a trigger pulse. After the temperature measurement is
complete, the TDC1000 returns to SLEEP mode. To return to TOF measurement mode, reset the MEAS_MODE
bit to 0.
The temperature sensor measurement can be performed without the need of an external ADC. The temperature
sensor block operates by converting the resistance of a reference, RREF, and up to two RTDs into a series of
START and STOP pulses. The interval between the pulses is proportional to the measured resistance, and
therefore, the temperature. As shown in Figure 25, the TDC1000 performs three measurements per trigger event
and generates the corresponding pulses on the START and STOP pins.
TRIGGER Reference RTD1 RTD2
START td1 td2
tREF tRTD1 tRTD2

STOP
Figure 25. Temperature Measurement Output Timing
The resistance of RTD1 and RTD2 can be calculated from the time intervals in Figure 25 as follows:
t
R RTDx R REF u REF
t RTDx (3)
With a 1-kΩ reference resistor, the tREF interval is approximately 200 μs. The following intervals, tRTD1 and tRTD2,
will depend on the resistance of the RTDs. The time delay between measurements, td1 and td2, can be
approximated as follows:
td1 = (51 × TTEMP) + ( tRTD1 × 0.55 ) (4)
td2 = (51 × TTEMP) + ( tRTD2 × 0.55 ) (5)
For example, two PT1000 sensors at 0°C will have an approximate resistance of 1 kΩ; the same as the
reference resistor in this example. Given an external 8-MHz clock and the default temperature clock divide-by-8
from the TEMP_CLK_DIV bit, the overall measurement time between the START pulse and the last STOP pulse
is approximately 922 µs.

TDC1000, TDC1000-Q1
8.3.8.2 Temperature Measurement with a Single RTD

The temperature sensing block can be configured to measure a single RTD by setting the TEMP_MODE bit in
register CONFIG_3 to 1. When the temperature measurement runs in PT1000 mode (TEMP_RTD_SEL = 0), the
first interval corresponds to RREF, the second interval is a redundant measurement on RREF and should be
neglected, and the third interval corresponds to RTD1. This operation is represented in Figure 26.
TRIGGER Reference Discard RTD1
START
td1 td2
tREF ½ t REF tRTD1

STOP
Figure 26. Temperature Measurement with a Single PT1000
The resistance of RTD1 can be calculated using Equation 3. The time delay between measurements can be
approximated using Equation 4 and Equation 5, with the exception that in this case, td1 is a function of ½ tREF and
td2 is a function of tRTD1.
If the temperature measurement runs in PT500 mode (TEMP_RTD_SEL = 1), the first interval is a redundant
measurement on RREF and should be neglected, the second interval corresponds to RREF, and the third interval
corresponds to RTD1. This operation is represented in Figure 27.
TRIGGER Discard Reference RTD1
START
td1 td2
2 u tREF tREF tRTD1

STOP
Figure 27. Temperature Measurement with a Single PT500
The resistance of RTD1 can be calculated using Equation 3. The time delay between measurements can be
approximated using Equation 4 and Equation 5, with the exception that in this case, td1 is a function of tREF and
td2 is a function of tRTD1.
8.4 Device Functional Modes

8.4.1 Time-of-Flight Measurement Mode
The TOF measurement mode is selected by setting the MEAS_MODE bit in the CONFIG_2 register to 0. The
type of TOF measurement mdoe can be selected with the TOF_MEAS_MODE field in the CONFIG_2 register.
Table 3 lists the available TOF measurement modes with their corresponding channel assignments.
Table 3. TOF Measurement Modes

TOF_MEAS_MODE CH_SEL EXT_CHSEL Active TX Channel Active RX Channel
Channel 1 0 0 TX1 RX2
Mode 0 00
Mode 1 01
Channel 1 0 0 Based on state machine and CH_SWP bit
Mode 2 10
Channel 2 1 0 Based on state machine and CH_SWP bit
Reserved 11 Reserved

TDC1000, TDC1000-Q1
8.4.1.1 Mode 0
Mode 0 is intended for Level and Fluid Identification Measurements applications. The TDC1000 associates each
transducer to complementary TX and RX channels. The transmit/receive pair “TX1/RX2” will act as both
transmitter and receiver for a measurement if CH_SEL = 0 in the CONFIG_2 register. The transmit/receive pair
“TX2/RX1” will act as both transmitter and receiver for the measurement if CH_SEL = 1.
The TDC1000 performs a single TOF measurement after receiving a trigger signal and returns to the SLEEP
mode when the measurement is complete.
8.4.1.2 Mode 1
In Mode 1 the TDC1000 associates each transducer to a single TX and RX channels. The transmit/receive pair
"TX1/RX1" will act as both transmitter and receiver for a measurement if CH_SEL = 0. The transmit/receive pair
"TX2/RX2" will act as both transmitter and receiver for the measurement if CH_SEL = 1.
The TDC1000 performs a single TOF measurement (one direction) and returns to the SLEEP mode when the
measurement is complete.
8.4.1.3 Mode 2
Mode 2 is intended for transit time water flow metering applications (see Water Flow Metering). In this mode, the
channel definitions are the same as for Mode 1: Channel 1 = "TX1/RX1" and Channel 2 = "TX2/RX2". The
TDC1000 will perform one TOF measurement and go into READY state waiting for the next trigger signal.
Mode 2 supports averaging cycles and automatic channel swap. The averaging mode is active if NUM_AVG > 0
and allows for the stopwatch or MCU to perform the average of multiple TOF measurement cycles. In this mode,
the device performs a TOF measurement on one channel (direction) for every trigger pulse until the averaging
count is reached, and if CH_SWP = 1, it will automatically swap channels and perform a TOF measurement on
the other channel (direction) for every trigger pulse until the averaging count is reached.
The number of averages is controlled with the NUM_AVG field found in the CONFIG_1 register. Channel
swapping is controlled with the CH_SWP bit in the CONFIG_2 register. The EXT_CHSEL bit in the CONFIG_2
register must be 0 for automatic channel swap to work. If EXT_CHSEL is 1, the active channel selection is
controlled manually with the CHSEL pin.
NOTE
If an echo measurement times out in averaging mode (indicated by the error flags or
ERRB pin), the state machine should be reset and the error flags should be cleared. The
state machine can be cleared by writing a 1 to bit [1] of the ERROR_FLAGS register and
the error flags can be cleared by writing a 1 to bit [0] of the ERROR_FLAGS register. After
completing these steps, the averaged measurement should be restarted.
8.4.2 State Machine

A state machine in the TDC1000 manages the operation of the various measurement modes (see Figure 28). At
power-on, the state machine is reset and most blocks are disabled. After the power-on sequence is complete, the
device goes into SLEEP mode if the EN pin is low or into READY mode if the EN pin is high. In the SLEEP or
READY state, the TDC1000 is able to receive SPI commands to set registers and configure the device for a
measurement mode.
NOTE
Although the SPI block is always active, it is not recommended to perform configuration
changes while the device is active. Configuration changes should be performed while the
device is in the SLEEP state or in the READY state.
If the EN pin is high and a trigger signal is received, the state machine will begin the execution of the configured
measurement. If the device is configured in Mode 0 or Mode 1, the state machine will return to the SLEEP state
after the measurement is completed. If the device is configured in Mode 2, the state machine returns to the
READY state and waits for the next trigger to continue with the next measurement.

TDC1000, TDC1000-Q1
The device can be forced to exit a measurement by applying a logic high on the RESET pin high or a logic low
on the EN pin.
SW Reset
EN=Low HW Reset
Timeout=1
SLEEP state ERROR_FLAGS register (0x07):

x Writing 1 to bit [1] of the ERROR_FLAGS
register cancels any active measurement
No and returns to sleep mode or ready mode
EN=High and sets Count to 0 and CH-flag to FALSE.
If averaging: Set Count = 0

If CH_SWP & NOT(EXT_CHSEL):
set CH-flag TRUE
Ready
Trigger
pulse?
TOF_MEAS_MODE = 0h (Mode 0)
= 1h (Mode 1) Yes
TX Burst
Output START
Pulse
RX Active
Output
STOP pulses
Mode?
TOF_MEAS_MODE = 2h (Mode 2)
Count <
Yes Increment Count
Average?
No
Toggle Channel
CH-flag TRUE? Yes Set Count = 0
Set Ch-flag FALSE
Figure 28. Simplified TDC1000 State Machine Diagram

TDC1000, TDC1000-Q1
8.4.3 TRANSMIT Operation
8.4.3.1 Transmission Pulse Count

The number of TX pulses generated by the TDC1000 to drive an ultrasonic transducer is programmable using
the NUM_TX field located in the CONFIG_0 register.
8.4.3.2 TX 180° Pulse Shift

As shown in Figure 29, the transmitter block can add a 180° shift at a position in the TX signal. The position of
the pulse shift is set by the TX_PH_SHIFT_POS field in the CONFIG_4 register and allows generating a specific
signal pattern.
Generation of 180° burst
for Tx Signature
Figure 29. Transmitter Pulse Signature, 180° Burst
As shown in Figure 30, enabling the TX 180° pulse shift has the effect of decreasing the number of transmitted
pulses by 1.
Normal Operation:
NUM_TX = 0x07
TX_PH_SHIFT_POS = 0x1F
180| Shift:
NUM_TX = 0x07
TX_PH_SHIFT_POS = 0x03
Pos. 0 Pos. 1 Pos. 2 Pos. 3 Pos. 4 Pos. 5 Pos. 6
Figure 30. Transmitter Pulse Signature
In some cases, the 180° pulse shift may help improving the turn-off time of a transducer, and thus suppress the
transmit ringing.
The 180° pulse shift is disabled by setting TX_PH_SHIFT_POS to position 31. Setting the 180° pulse shift to
positions 0 or 1 is not recommended.
8.4.3.3 Transmitter Damping

The transmitter damping feature allows for improved control over the transducer signal generation. Damping
extends the duration of the last TX pulse to help dissipate ringing and improve the transducer's turn-off time (see
Figure 31 and Figure 32). The accuracy of measurements can be improved by having a faster transducer turn-off
time. Damping is controlled with the DAMPING bit in the CONFIG_2 register.
Damping extends the duration of
the last pulse to dissipate ringing
Figure 31. Transmitter Damping (5 Tx Pulses With a Damping Pulse)

TDC1000, TDC1000-Q1
8.0
Damping disabled
6.0
Damping enabled
4.0
2.0
Amplitude
0.0
-2.0
-4.0
-6.0
-8.0
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0
7LPHV
Figure 32. Transmitter Damped Echo
There are two invalid use combinations of the damping feature that may result in unexpected behavior. First,
damping should not be combined with the 180° pulse shift described in the previous section. Second, damping
should not be enabled if the number of TX pulses is set to 31.
8.4.4 RECEIVE Operation
8.4.4.1 Single Echo Receive Mode

Single Echo mode is suitable for concentration measurements and flow metering applications. The device can be
configured for Single Echo mode by setting the RECEIVE_MODE bit to 0 in the CONFIG_4 register. In Single
Echo mode, the device will generate STOP pulses for every zero-cross qualified by the threshold comparator, up
to the number of expected STOP events configured in the NUM_RX field in the CONFIG_1 register.
The threshold comparator qualifies the next zero-cross after an RX amplitude smaller than the programmed
threshold voltage is detected. The zero-cross detector will provide output pulses corresponding to the rising edge
of the received signal crossing the VCOM level, as shown in Figure 33. The threshold voltage can be set in the
ECHO_QUAL_THDL field in the CONFIG_3 register.
Zero-crossing detected after
threshold exceeded
COMPIN
VCOM
ECHO_QUAL_THLD
Threshold
Signal exceeds threshold
Output on
STOP pin
Maximum number of requested events (5 in this figure)

returned; subsequent events not reported
Figure 33. Single Echo Receive Mode (5 STOP Events)

TDC1000, TDC1000-Q1
If the number of expected pulses programmed in NUM_RX is not received or the time-of-flight operation times
out, the TDC1000 will indicate an error condition in the ERROR_FLAGS register and will set the ERRB pin low.
8.4.4.2 Multiple Echo Receive Mode

The Multiple Echo mode is intended for use in level sensing applications and distance/displacement
measurements in which multiple echoes (burst) are received. In this condition, each received echo group will be
treated as a single pulse on the STOP pin. Up to 7 STOP pulses can be generated based on the value of the
NUM_RX field in the CONFIG_1 register. Multi echo mode can be enabled by setting the RECEIVE_MODE bit to
1 in the CONFIG_4 register. A representation of multiple echo STOP pulse generation is shown in Figure 34.
COMPIN
VCOM
Programmed
threshold
Output on
STOP pin
No pulse on STOP No pulse on STOP pin because
pin because signal did not maximum number of programmed events
exceed threshold (5 in this example) already produced.
Figure 34. Multiple Echo Receive Mode (5 STOP Events)
The rising edge of a STOP pulse is generated by a zero-crossing event. As in the Single Echo Receive Mode,
the threshold comparator qualifies the next zero-cross after an RX amplitude smaller than the programmed
threshold voltage is detected. The STOP pulse will extend until a zero-cross after the RX amplitude is no longer
smaller than the threshold voltage (see Figure 35).
Signal zero-crossing without
Zero-crossing detected exceeding threshold
after threshold exceeded
COMPIN
VCOM
Programmed
threshold
Signal exceeds
threshold
Output on
STOP pin
Figure 35. Multiple Echo Receive Mode (Zoom-in)
If the number of expected pulses programmed in NUM_RX is not received or the time-of-flight operation times
out, the TDC1000 will indicate an error condition in the ERROR_FLAGS register and will set the ERRB pin low.

TDC1000, TDC1000-Q1
8.4.5 Timing
8.4.5.1 Timing Control and Frequency Scaling (CLKIN)

0x09[2] ± CLOCKIN_DIV
1
y 2CLOCKIN_DIV ¦0 T0 =
¦0
CLKIN ¦CLKIN
1
y 2TX_FREQ_DIV+1 ¦1 T1 =
¦1
0x00[7:5] ± TX_FREQ_DIV
Figure 36. External Clock Division Tree
All transmit and receive function sequencing is synchronous to the external clock applied to the CLKIN pin. The
external clock is divided to generate two internal clocks with corresponding time periods denoted as T0 and T1 in
Figure 36. The division factor used to generate T0 is controlled with the CLOCKIN_DIV bit in the CLOCK_RATE
register. The division factor used to generate T1 is controlled with the TX_FREQ_DIV field located in the
CONFIG_0 register.
The SPI block is synchronous with the clock applied to the SCLK pin, and it is independent of the clock applied
to CLKIN. See the Serial Peripheral Interface (SPI) section for a complete description of the SPI block.
8.4.5.2 TX/RX Measurement Sequencing and Timing

The TDC1000 automatically sequences the TX and RX functionality. After receiving a pulse edge on the
TRIGGER pin, the TDC1000 resynchronizes to the CLKIN signal, and sends a TX burst. During the transmission
burst, the RX path is set to the alternate channel to minimize coupled noise.
During resynchronization, the trigger and START edges are aligned to the negative edge of the external clock.
The time between trigger and START is equal to 3 T0 periods plus 2 or 3 T1 periods, depending on the phase
between the received trigger pulse and the external clock. For example, if ƒCLKIN = 8 MHz and TX_FREQ_DIV =
0h2 (divide-by-8), the period T0 is 125 ns and the period T1 is 1 µs, resulting in a time of 2.375 µs or 3.375 µs
between the received trigger signal and the generated START pulse.
The trigger edge polarity is configured to rising edge by default, but it can be changed to falling edge by setting
the TRIG_EDGE_POLARITY bit in the CONFIG4 register to 1.
After a device reset, the system must wait a determined time before sending the next trigger signal. The typical
reset to trigger wait time is 3 × T1 + (50 ns).
8.4.6 Time-of-Flight (TOF) Control

The possible configurations of the TX/RX sequencing during a time-of-flight measurement can be divided into
three cases: Short TOF Measurement, Standard TOF Measurement and Standard TOF Measurement with
Power Blanking. Overall, the cases differ in the order of sequencing, power saving and echo listening windows.
The behavior of each case is described in the sections to follow.

TDC1000, TDC1000-Q1
8.4.6.1 Short TOF Measurement
Analog OFF
Analog ON
TRIG (see Note A)
Echo listen period
TX
START (see Note B)
(see Note C)
RX
STOP
READY COMMON-MODE AUTOZERO TRANSMIT MASK ECHO LISTEN END READY
128 x T0 2AUTOZERO_PERIOD x 64 x T0 NUM_TX x T1 2SHORT_TOF_BLANK_PERIOD x 8 x T0 2TOF_TIMEOUT_CTRL x 128 x T0 1 x T1
A. Clock alignment (see TX/RX Measurement Sequencing and Timing)

B. If NUM_TX < 3, the width of the START pulse is equal to NUM_TX × T1. If NUM_TX ≥ 3, the width of the START
pulse is equal to 3 × T1.
C. Common-mode settling time.
Figure 37. Short TOF Measurement
In a short time of flight measurement, the RX path is activated before the TX burst, as shown in Figure 37. The
input MUX is automatically swapped to the alternate receive channel before and during the TX burst. Swapping
the input prevents the TX burst from being amplified in the RX path. After the TX burst, the input MUX remains
switched to the alternate channel for a masking period determined by the SHORT_TOF_BLANK_PERIOD field in
the TIMEOUT register. Masking the RX path avoids the issue of amplifying the transducer's residual TX ringing in
the RX path.
The short TOF is the default measurement sequence selected at power-on. The short TOF measurement is
selected if the value of the TIMING_REG[9:0] field is less than 30, or if the FORCE_SHORT_TOF bit is set to 1.
The TIMING_REG[9:0] is a 10-bit wide field, with its 2 most significant bits located in the TOF_1 register, and the
8 least significant bits located in the TOF_0 register. The FORCE_SHORT_TOF bit is located in the TIMEOUT
register.
The comparator's input offset is stored in an internal capacitor during the auto-zero period. The length of the
auto-zero period is controlled by the AUTOZERO_PERIOD field in the CLOCK_RATE register.
The length of the window when the comparators are able to qualify and generate STOP pulses is configured by
the TOF_TIMEOUT_CTRL field. A timeout will occur if the number of expected pulses is not received during the
allocated time and an error condition is reported to the ERROR_FLAGS register and the ERRB pin. It is possible
to disable the echo timeout (see TOF Measurement Interval). The TOF_TIMEOUT_CTRL field is located in the
TIMEOUT register.
See the Timing Control and Frequency Scaling (CLKIN) section for the definition of the time periods T0 and T1.

TDC1000, TDC1000-Q1
8.4.6.2 Standard TOF Measurement
Analog OFF
Analog ON
TRIG
Echo listen period
TX
(see Note A)
START
(see Note B) (see Note C)
RX
STOP
READY TRANSMIT COMMON-MODE AUTOZERO WAIT / ECHO LISTEN ECHO LISTEN END READY
NUM_TX x T1 128 x T0 2AUTOZERO_PERIOD x 64 x T0 (TIMING_REG ± 30) x 8 x T0 2TOF_TIMEOUT_CTRL x 128 x T0 1 x T1

Figure 38. Standard TOF Measurement
In a standard time of flight measurement, the RX path is activated after the TX burst is completed, as shown in
Figure 38.
The standard TOF measurement sequence is enabled if the value of the TIMING_REG field is greater than or
equal to 30, and only if the FORCE_SHORT_TOF bit is set to 0. The TIMING_REG is a 10-bit wide field, with its
2 most significant bits located in the TOF_1 register, and the 8 least significant bits located in the TOF_0 register.
The FORCE_SHORT_TOF bit is located in the TIMEOUT register.
The comparator's input offset is stored in an internal capacitor during the auto-zero period. The length of the
auto-zero period is controlled by the AUTOZERO_PERIOD field in the CLOCK_RATE register.
The length of the window when the comparators are able to qualify and generate STOP pulses is configured by a
combination of the TIMING_REG field and the TOF_TIMEOUT_CTRL field. With the addition of the
TIMING_REG in the calculation, the standard TOF measurement allows for a longer wait time and listening
window. A timeout will occur if the number of expected pulses is not received during the allocated time and an
error condition is reported to the ERROR_FLAGS register and the ERRB pin. It is possible to disable the echo
timeout (see TOF Measurement Interval). The TOF_TIMEOUT_CTRL field is located in the TIMEOUT register.
NOTE
If the FORCE_SHORT_TOF bit = 1, the measurement sequencing will behave as a Short
TOF Measurement, thus overriding the setting of the TIMING_REG field.

TDC1000, TDC1000-Q1
8.4.6.3 Standard TOF Measurement with Power Blanking
Analog OFF
Analog ON
TRIG
Echo listen period
TX
(see Note A)
START
(see Note B) (see Note C)
RX
STOP
READY TRANSMIT WAIT COMMON-MODE AUTOZERO ECHO LISTEN END READY
NUM_TX x T1 (TIMING_REG ± 30) x 8 x T0 128 x T0 2AUTOZERO_PERIOD x 64 x T0 2TOF_TIMEOUT_CTRL x 128 x T0 1 x T1

Figure 39. Standard TOF Measurement with Blanking Enabled
The power blanking sequence is a variation to the standard TOF measurement sequence, and can be enabled
by setting the BLANKING bit to 1. In addition, all other conditions described in the Standard TOF Measurement
should be met. The BLANKING bit can be found in the CONFIG_3 register.
Power blanking allows the device to remain in a low-power state while the TX signals propagate to the RX
transducer in situations when the expected time-of-flight is long. Power blanking uses the TIMING_REG to
control a wait time between the transmit sequence and the receive sequence, during which, the complete RX
chain is disabled, as shown in Figure 39. The TIMING_REG is a 10-bit wide field, with its 2 most significant bits
located in the TOF_1 register, and the 7 least significant bits located in the TOF_0 register.
8.4.6.4 Common-mode Reference Settling Time

The duration of the common-mode settling time is defined by the VCOM capacitor. With a 10-nF VCOM
capacitor, the common-mode reference requires 16 µs to settle. On the other hand, the duration of the common-
mode settling window is defined as 128 × T0, where the time unit T0 is determined by the external clock
frequency and the value of the CLOCKIN_DIV bit, as explained in the Timing Control and Frequency Scaling
(CLKIN) section.
A frequency of 8 MHz will result in a settling window of 128 × 1 / 8 MHz, which equals to 16 µs. Increasing the
value of the VCOM capacitor will increase the common-mode settling time, but for the same 8-MHz frequency,
the duration of the common-mode settling window will remain at 16 µs. In such situation, the common-mode
reference will take multiple TOF cycles to reach its final value when starting from zero initial conditions.
8.4.6.5 TOF Measurement Interval

The comparators in the TDC1000's RX path can qualify and generate STOP pulses from a received echo within
an interval set by the TOF_TIMEOUT_CTRL field in the TIMEOUT register. The listening interval can be
extended in the standard TOF measurement (without blanking) by a period controlled with the TIMING_REG field
(see Standard TOF Measurement).

TDC1000, TDC1000-Q1
If the number of STOP events programmed in the NUM_RX field is not received within the listening interval, a
timeout event will occur and the device will return to the READY state. In addition, an error will be reported to the
ERROR_FLAGS register and the ERRB pin will be driven low.
The echo timeout can be disabled by setting the ECHO_TIMEOUT bit to 1 in the TIMEOUT register. If the echo
timeout is disabled, the device will not exit from the receive state until the expected number of STOP events set
in NUM_RX occur. If the number of events does not occur, the device can be forced out of the receive state by
writing a value of 0x03 to the ERROR_FLAGS register, or by de-asserting the EN pin, or asserting the RESET
pin.
NOTE
Writing a logic 1 to bit [1] of the ERROR_FLAGS register clears the state machine. Writing
a logic 1 to bit[0] clears the error flags.
NOTE
It is not recommended to hold the RX in an active state for intervals longer than 100ms, as
the comparator auto-zero may no longer be accurate.
8.4.7 Averaging and Channel Selection

The TDC1000 supports averaging when configured in measurement Mode 2 (see Time-of-Flight Measurement
Mode). Averaging is controlled with the NUM_AVG field located in the CONFIG_1 register. In Mode 2, the
TDC1000 will remain on the channel indicated by CH_SEL for 2NUM_AVG trigger cycles. If CH_SWP is enabled in
the CONFIG_2 register, the TDC1000 will automatically swap the active channel and repeat the averaging cycle.
NOTE
If the bit [1] in the ERROR_FLAGS register is written to 1, the TDC1000 will reset its
internal averaging counter and the software channel selection.
8.4.8 Error Reporting

The TDC1000 will report an error when the receive signals do not match the expected configuration. The ERRB
pin will go low to indicate the presence of an error condition. Reading the ERROR_FLAGS register provides
information about the condition(s) that caused the error.
The ERR_SIG_WEAK bit indicates that the number of received and qualified zero-crossings was less than the
expected number set in the NUM_RX register field and a timeout occurred. This error is cleared when bit [0] is
written to 1.
The ERR_NO_SIG bit indicates that no signals were received and a timeout occurred. Writing a 1 to this bit
resets the state machine, halts active measurements and returns the device to SLEEP or READY mode and
resets the average counter and automatic channel selection in measurement Mode 2. This error is cleared when
bit [0] is written to 1.
The ERR_SIG_HIGH bit indicates that the received echo amplitude exceeds the largest echo qualification
threshold at the input of the comparators. The ERR_SIG_HIGH error is only reported when the
ECHO_QUAL_THDL register field is set to 7h. Writing a 1 to this bit will reset all the error flags and reset the
ERRB pin to high.
NOTE
It is recommended to reset the state machine when the error flags are cleared. This can
be done simultaneously by writing a value of 0x03 to the ERROR_FLAGS register.

TDC1000, TDC1000-Q1
8.5 Programming
8.5.1 Serial Peripheral Interface (SPI)
The serial interface consists of serial data input (SDI), serial data output (SDO), serial interface clock (SCLK) and
chip select bar (CSB). The serial interface is used to configure the TDC1000 parameters available in various
configuration registers. All the registers are organized into individually addressable byte-long registers with a
unique address.
The communication on the SPI bus normally supports write and read transactions. A write transaction consists of
a single write command byte, followed by single data byte. A read transaction consists of a single read command
byte followed by 8 SCLK cycles. The write and read command bytes consist of 1 reserved bit, a 1-bit instruction,
and a 6-bit register address. Figure 40 shows the SPI protocol for a transaction involving one byte of data (read
or write).
CSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCK
COMMAND FIELD DATA FIELD
MSB LSB
SDI c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0
resvd R/W Address (6 bits) Write Data (8-bits)
MSB LSB
SDO d7 d6 d5 d4 d3 d2 d1 d0
R/W = Instruction Read Data (8-bits)

0: Read
1: Write
Note: Specifying any value other than zero in bit[7] of the command byte is prohibited.
Figure 40. SPI Protocol
8.5.1.1 Chip Select Bar (CSB)

CSB is an active-low signal and needs to be low throughout a transaction. That is, CSB should not pulse
between the command byte and the data byte of a single transaction.
De-asserting CSB always terminates an ongoing transaction, even if it is not yet complete. Re-asserting CSB will
always bring the device into a state ready for the next transaction, regardless of the termination status of a
previous transaction.
8.5.1.2 Serial Clock (SCLK)

SCLK can idle high or low. It is recommended to keep SCLK as clean as possible to prevent glitches from
corrupting the SPI frame.
8.5.1.3 Serial Data Input (SDI)

SDI is driven by the SPI master by sending the command and the data byte to configure the AFE.
8.5.1.4 Serial Data Output (SDO)

SDO is driven by the AFE when the SPI master initiates a read transaction.

TDC1000, TDC1000-Q1
8.6 Register Maps
NOTE
• Reserved bits must be written to 0 unless otherwise indicated.
• Read-back value of reserved bits and registers is unspecified and should be discarded.
• Recommended values must be programmed and forbidden values must not be
programmed where they are indicated to avoid unexpected results.
8.6.1 TDC1000 Registers

Table 4 list the memory-mapped registers for the TDC1000. All register addresses not listed in Table 4 should be
considered as reserved locations and the register contents should not be modified.
Table 4. TDC1000 REGISTERS

Address (Hex) Acronym Register Name Reset Value Section
0h CONFIG_0 Config-0 45h See here
4h CONFIG_4 Config-4 1Fh See here
5h TOF_1 TOF-1 0h See here
6h TOF_0 TOF-0 0h See here
7h ERROR_FLAGS Error Flags 0h See here
8h TIMEOUT Timeout 19h See here
9h CLOCK_RATE Clock Rate 0h See here
8.6.1.1 CONFIG_0 Register (address = 0h) [reset = 45h] (map)

Figure 41. CONFIG_0 Register
(MSB) 7 6 5 4 3 2 1 0 (LSB)
TX_FREQ_DIV NUM_TX
R/W-2h R/W-5h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 5. CONFIG_0 Register Field Descriptions

Bit Field Type Reset Description
Frequency divider for TX clock and T1

0h: Divide by 2
1h: Divide by 4
2h: Divide by 8 (default)
[7:5] TX_FREQ_DIV (1) R/W 2h 3h: Divide by 16
4h: Divide by 32
5h: Divide by 64
6h: Divide by 128
7h: Divide by 256
Number of TX pulses in a burst, ranging from 0 to 31.

[4:0] NUM_TX R/W 5h
5h: 5 pulses (default)
(1) See Timing Control and Frequency Scaling (CLKIN) for the definition of the time period T1.

TDC1000, TDC1000-Q1

(MSB) 7 6 5 4 3 2 1 0 (LSB)
RESERVED NUM_AVG NUM_RX
R/W-1h R/W-0h R/W-0h
[7:6] RESERVED R/W 1h 1h: Reserved (default)
Number of measurement cycles to average in stopwatch/MCU

0h: 1 measurement cycle (default)
1h: 2 measurement cycles
[5:3] NUM_AVG R/W 0h 3h: 8 measurement cycles
Number of expected receive events

0h: Do not count events (32 STOP pulses output) (default)
1h: 1 event (1 STOP pulse output)
2h: 2 events (2 STOP pulses output)
[2:0] NUM_RX R/W 0h 3h: 3 events (3 STOP pulses output)

TDC1000, TDC1000-Q1

(MSB) 7 6 5 4 3 2 1 0 (LSB)
VCOM_SEL MEAS_MODE DAMPING CH_SWP EXT_CHSEL CH_SEL TOF_MEAS_MODE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Common-mode voltage reference control

[7] VCOM_SEL R/W 0h 0h: Internal (default)
1h: External
AFE measurement type

[6] MEAS_MODE R/W 0h 0h: Time-of-flight measurement (default)
1h: Temperature measurement
TX burst damping
[5] DAMPING R/W 0h 0h: Disable damping (default)
1h: Enable damping
Automatic channel swap in Mode 2 of operation. The setting is

ignored if EXT_CHSEL = 1.
[4] CH_SWP R/W 0h
0h: Disable automatic channel swap (default)
1h: Enable automatic channel swap
External channel select by CHSEL pin

0h: Disable external channel select (default).
[3] EXT_CHSEL R/W 0h
1h: Enable external channel select
EXT_CHSEL = 1 overrides the CH_SWP and CH_SEL settings.
Active TX/RX channel pair.
0h: Channel 1 (default)
[2] CH_SEL R/W 0h 1h: Channel 2
See Time-of-Flight Measurement Mode for channel definitions.
The setting is ignored if EXT_CHSEL = 1.
Time-of-flight measurement mode

0h: Mode 0 (default)
[1:0] TOF_MEAS_MODE R/W 0h 1h: Mode 1
2h: Mode 2
3h: Reserved

TDC1000, TDC1000-Q1
8.6.1.4 CONFIG_3 Register (address 3h) [reset = 3h] (map)

(MSB) 7 6 5 4 3 2 1 0 (LSB)
RESERVED TEMP_MODE TEMP_RTD_SEL TEMP_CLK_DIV BLANKING ECHO_QUAL_THLD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-3h
[7] RESERVED R/W 0h 0h: Reserved (default)
Temperature measurement channels

[6] TEMP_MODE R/W 0h 0h: Measure REF, RTD1 and RTD2 (default)
1h: Measure REF and RTD1
RTD type
[5] TEMP_RTD_SEL R/W 0h 0h: PT1000 (default)
1h: PT500
Clock divider for temperature mode

[4] TEMP_CLK_DIV R/W 0h 0h: Divide by 8 (default)
1h: Use TX_FREQ_DIV
Power blanking in standard TOF measurements. The blanking

length is controlled with the TIMING_REG field (see Standard
[3] BLANKING R/W 0h TOF Measurement with Power Blanking).
0h: Disable power blanking (default)
1h: Enable power blanking
Echo qualification DAC threshold level with respect to VCOM

0h: –35 mV
1h: –50 mV
2h: –75 mV
[2:0] ECHO_QUAL_THLD R/W 3h 3h: –125 mV (default)
4h: –220 mV
5h: –410 mV
6h: –775 mV
7h: –1500 mV

TDC1000, TDC1000-Q1
8.6.1.5 CONFIG_4 Register (address = 4h) [reset = 1Fh] (map)

(MSB) 7 6 5 4 3 2 1 0 (LSB)
RECEIVE_ TRIG_EDGE_
RESERVED TX_PH_SHIFT_POS
MODE POLARITY
R/W-0h R/W-0h R/W-0h R/W-1Fh
Receive echo mode

[6] RECEIVE_MODE R/W 0h 0h: Single echo (default)
1h: Multi echo
Trigger edge polarity

[5] TRIG_EDGE_POLARITY R/W 0h 0h: Rising edge (default)
1h: Falling edge
TX 180° pulse shift position, ranging from 0 to 31.

[4:0] TX_PH_SHIFT_POS R/W 1Fh 1Fh: Position 31 (default)
It is not recommended to set TX_PH_SHIFT_POS to 0 or 1.

TDC1000, TDC1000-Q1
8.6.1.6 TOF_1 Register (address = 5h) [reset = 0h] (map)

Figure 46. TOF_1 Register
(MSB) 7 6 5 4 3 2 1 0 (LSB)
PGA_GAIN PGA_CTRL LNA_CTRL LNA_FB TIMING_REG[9:8]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 10. TOF_1 Register Field Descriptions
PGA gain
0h: 0 dB (default)
1h: 3 dB
2h: 6 dB
[7:5] PGA_GAIN R/W 0h 3h: 9 dB
4h: 12 dB
5h: 15 dB
6h: 18 dB
7h: 21 dB
PGA control
[4] PGA_CTRL R/W 0h 0h: Active (default)
1h: Bypassed and powered off
LNA control
[3] LNA_CTRL R/W 0h 0h: Active (default)
1h: Bypassed and powered off
LNA feedback mode

[2] LNA_FB R/W 0h 0h: Capacitive feedback (default)
1h: Resistive feedback
TIMING_REG field's 2 most-significant bits (see Standard TOF

Measurement and Standard TOF Measurement with Power
[1:0] TIMING_REG[9:8] R/W 0h
Blanking)
0h: 0 (default)
8.6.1.7 TOF_0 Register (address = 6h) [reset = 0h] (map)

Figure 47. TOF_0 Register
(MSB) 7 6 5 4 3 2 1 0 (LSB)
TIMING_REG[7:0]
R/W-0h
Table 11. TOF_0 Register Field Descriptions

TIMING_REG field's 8 least-significant bits (see Standard TOF

Measurement and Standard TOF Measurement with Power
[7:0] TIMING_REG[7:0] R/W 0h
Blanking)
0h: 0 (default)

TDC1000, TDC1000-Q1
8.6.1.8 ERROR_FLAGS Register (address = 7h) [reset = 0h] (map)

Figure 48. ERROR_FLAGS Register
7 (MSB) 6 5 4 3 2 1 0 (LSB)
ERR_ ERR_
RESERVED ERR_NO_SIG
SIG_WEAK SIG_HIGH
R-0h R-0h R/W1C-0 R/W1C-0
Table 12. ERROR_FLAGS Register Field Descriptions (1) (2)
[7:3] RESERVED R 0h 0h: Reserved (default)
1h: The number of received and qualified zero-crossings was

[2] ERR_SIG_WEAK R 0h less than the expected number set in NUM_RX field and a
timeout occurred.
1h: No signals were received and timeout occurred.

Writing a 1 to this field resets the state machine, halts active
[1] ERR_NO_SIG R/W1C 0h measurements and returns the device to the SLEEP or READY
mode and resets the average counter and automatic channel
selection in measurement Mode 2.
1h: The received echo amplitude exceeds the largest echo

qualification threshold at the input of the comparators. The error
[0] ERR_SIG_HIGH R/W1C 0h is only reported when ECHO_QUAL_THLD = 0x07.
Writing a 1 to this field will reset all the error flags and reset the
ERRB pin to high.
(1) It is recommended to read the error status register or the ERRB pin before initiating a new measurement.
(2) All error flags should be cleared before initiating a new measurement.

TDC1000, TDC1000-Q1
8.6.1.9 TIMEOUT Register (address = 8h) [reset = 19h] (map)

Figure 49. TIMEOUT Register
(MSB) 7 6 5 4 3 2 1 0 (LSB)
FORCE_ ECHO_
RESERVED SHORT_TOF_BLANK_PERIOD TOF_TIMEOUT_CTRL
SHORT_TOF TIMEOUT
R/W-0h R/W-0h R/W-3h R/W-0h R/W-1h
Table 13. TIMEOUT Register Field Descriptions
Short time-of-flight control

[6] FORCE_SHORT_TOF R/W 0h 0h: Disabled (default)
1h: Force a short time-of-flight measurement
Short time-of-flight blanking period (see Short TOF

Measurement)
0h: 8 × T0
1h: 16 × T0
2h: 32 × T0
[5:3] SHORT_TOF_BLANK_PERIOD (1) R/W 3h
3h: 64 × T0 (default)
4h: 128 × T0
5h: 256 × T0
6h: 512 × T0
7h: 1024 × T0
Echo receive timeout control (see TOF Measurement Interval)

[2] ECHO_TIMEOUT R/W 0h 0h: Enable echo timeout (default)
1h: Disable timeout
Echo listening window timeout (see TOF Measurement Interval)

0h: 128 × T0
[1:0] TOF_TIMEOUT_CTRL (1) R/W 1h 1h: 256 × T0 (default)
2h: 512 × T0
3h: 1024 × T0

TDC1000, TDC1000-Q1
8.6.1.10 CLOCK_RATE Register (address = 9h) [reset = 0h] (map)

Figure 50. CLOCK_RATE Register
(MSB) 7 6 5 4 3 2 1 0 (LSB)
RESERVED CLOCKIN_DIV AUTOZERO_PERIOD
R/W-0h R/W-0h R/W-0h
Table 14. CLOCK_RATE Register Field Descriptions (1)
[7:3] RESERVED R/W 0h 0h: Reserved (default)
CLKIN divider to generate T0

[2] CLOCKIN_DIV (1) R/W 0h 0h: Divide by 1 (default)
1h: Divide by 2
Receiver auto-zero period

0h: 64 × T0 (default)
[1:0] AUTOZERO_PERIOD (1) R/W 0h 1h: 128 × T0
2h: 256 × T0
3h: 512 × T0

TDC1000, TDC1000-Q1
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

The TDC1000 is an analog front-end for ultrasonic sensing applications. The device is typically used for the
driving and sensing of ultrasonic transducers to perform accurate time-of-flight measurements. Ultrasonic time-of-
flight sensing allows for fluid level measurements, fluid identification or concentration, flow measurements, and
proximity/distance sensing.
9.2 Typical Applications

9.2.1 Level and Fluid Identification Measurements
TX2/RX1
A
RREF
TX1/RX2 RTD
B
TX2
TX1 START
OR
RX1 TDC1000 STOP Gate
RX2
TRIGGER
16-MHz CLK
RESET
ERRB
SPI
EN
OSC
TMS320F28035
C2000 MCU
Figure 51. Level and Concentration Measurement Application Diagram

TDC1000, TDC1000-Q1
Typical Applications (continued)

9.2.1.1 Design Requirements
Table 15. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Fluid Level
Range 2 – 10 cm
Fluid Identification
Accuracy 0.5% concentration variation
Distance 5.08 cm
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Level Measurements

For level sensing applications, the total time-of-flight (TOF) of the sound wave in the fluid is measured. The
pulses transmitted by transducer B travel through the fluid, typically from the bottom, to the surface of the fluid.
The discontinuity between the fluid and air generates a reflected wave which returns back to transducer B.
At the beginning of a measurement cycle, the transducer is connected to a transmit channel of the AFE, and the
transmit burst excites the transducer to generate an ultrasound wave. Synchronous to the TX burst, a START
pulse is generated by the TDC1000 to indicate the start of a measurement. After the transmission is completed,
and depending on the device configuration, the transducer is connected to a receive channel of the AFE.
When a valid echo is received, the TDC1000 generates a STOP pulse. Generation of multiple STOP pulses is
possible through register configuration of the device. The START and STOP signal times are compared to
determine the TOF.
The level of the fluid can be determined using the following equation:
61( × ?
@=
2
where
• d is the fluid level in meters (m)
• TOF is the time-of-flight in seconds (s)
• c is the speed of sound in the fluid in meters per second (m/s) (6)

TDC1000, TDC1000-Q1
Trigger
START
TX1
Echo Pulse
received
RX2
TOF
STOP
Figure 52. Relation Between Transmit and Receive Pulses in Level Measurements
Level measurements have 2 main criteria: resolution and range (maximum height). Resolution accuracies of 1-2
mm are achievable but are impractical due to any environmental disturbances, such as tank vibrations, creating
millimeter level surface waves. Ranges of up to 1 m are measurable utilizing VDD level excitation pulses, but
surface disturbances and signal loss over longer distances make the reliable echo reception an issue. Greater
level measurement reception can be achieved by mechanical means (level guide tube) and/or electronic means
(level shifting the TX pulses to greater voltages; see TIDA-00322).
9.2.1.2.2 Fluid Identification

The TDC1000 can be used to measure the time-of-flight for a known distance to calculate the speed of sound
(cmedium) in the fluid. This application utilizes the same circuitry as the level example but a transducer in a
different configuration connected to the second channel. In this example, the speed of sound in the fluid (cmedium)
is measured by using transducer A.
The temperature can also be measured to compensate for the temperature variation of sound. With the known
distance, TOF and temperature, the speed of sound in the fluid can be determined and the identity of the
medium verified.
After measuring the time-of-flight for the fixed distance, the speed of sound can be calculated as follows:
2×@
?IA@EQI =
61(
where
• cmedium is the speed of sound in the fluid in meters per second (m/s)
• d is the level in meters (m)
• TOF is the time of flight in seconds (s) (7)

TDC1000, TDC1000-Q1
The measurement process is identical to the level example above. The speed of sound can be used to uniquely
identify a variety of fluids. In this example, the concentration of diesel exhaust fluid (DEF) is measured with a
desired accuracy resolution of 0.5% of concentration variation. For most fluids, the speed of sound varies over
temperature, so every application will be different. In this example, all samples were all at ambient temperature of
23°C.
9.2.1.3 Application Curves

The data used in the following level and fluid identification graphs was collected using ultrasonic test cells. The
test cells are acrylic plastic containers with width of 2.54 cm and ultrasonic transducers attached to the outside
using cyanoacrylate glue. The transducers in this experiment are STEMiNC 1MHz piezo electric ceramic discs
(SMD10T2R111). Equivalent transducers with the following characteristics could be used:
• Piezo material: SM111
• Dimensions: 10mm diameter x 2mm thickness
• Resonant frequency: 1050 kHz (thickness mode)
150 1650
1625
135
Speed of sound in medium (m/s)

1600
120
1575
Time-of-flight (Ps)
105 1550
90 1525
1500
75
1475
60
1450
45 1425
30 1400
2 3 4 5 6 7 8 9 10
er
%
er
at
at
.0
.0
.0
.5
.0
.5
Height (cm)
W
10
20
30
31
32
32
d
EF
EF
EF
EF
EF
EF
le
Ta
Fluid Height in Tank Time-of-Flight (µs)

til
D
is
D
Full (10 cm) 145

Fluid Speed of sound (m/s)
Full – 1 (9 cm) 131
Distilled water 1481.87
Full – 2 (8 cm) 118
Tap water 1483.13
3 cm 50
DEF 10.0% 1530.49
2 cm 35
DEF 20.0% 1576.42
Figure 53. Time-of-Flight for Fluid Height in Tank DEF 30.0% 1620.00
DEF 31.5% 1627.37
DEF 32.0% 1629.15
DEF 32.5% 1630.00
Figure 54. Speed of Sound for Various Fluids and Diesel

Exhaust Fluid (DEF) Concentration

TDC1000, TDC1000-Q1
1483.5 1632
1630

1483.0
1628
1482.5
1626
1624
1482.0
1622
1481.5
1620
1481.0 1618
%
er
er
.0
.5
.0
.5
at
at
30
31
32
32
W
W
d
EF
EF
EF
EF
le
Ta
til
D
is
D

DEF 30.0% 1620.00
Distilled water 1481.87
DEF 31.5% 1627.37
Tap water 1483.13
DEF 32.0% 1629.15
Figure 55. Speed of Sound in Distilled Water and Tap DEF 32.5% 1630.00
Water
Figure 56. Speed of Sound of Various Diesel Exhaust Fluid
(DEF) Concentrations

TDC1000, TDC1000-Q1
9.2.2 Water Flow Metering

RREF
RTD
Flow
l
TX1/RX2 TX2/RX1
B A TX2 START
TX1 STOP
RX1 TDC1000 TRIGGER TDC7200
RX2
EN
RESET
ERRB
SPI
8-MHz CLK
OSC
SPI
MSP430 ENABLE
MCU INT
Figure 57. Water Flow-meter Application Simplified Diagram
9.2.2.1 Design Requirements

The parameters in Table 16 are considered for this example.
Table 16. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Pipe diameter 15 mm
Distance between transducers 60 mm
Minimum flow rate 0.015 m3/h
Accuracy at minimum flow rate 5%
9.2.2.2 Detailed Design Procedure

The design of flow-meters requires a thorough technical assessment of the system where the device will be
used. The following is a list of areas to consider:
• Minimum and maximum flow rate at maximum allowable error in the system
• Transitional flow rate
• Instantaneous and total quantity pumped over time
• Accuracy of the meter within prescribed limits per applicable standards
• Pressure in the system
• Operating temperature range
The appropriate ultrasonic sensor and the proper electronics for interfacing to the sensor are determined based
on the system requirements. The following is a list of specifications applicable to the senor/assembly used in the
system:
• Excitation frequency
• Excitation source voltage
• Pipe diameter
• Distance between the transducers (or reflectors)

TDC1000, TDC1000-Q1
9.2.2.2.1 Regulations and Accuracy

If the flow meter is intended for residential applications, it must be designed to meet the required standards. For
example, per the INTERNATIONAL ORGANIZATION OF LEGAL METROLOGY (OIML), the metrological
requirements of water meters are defined by the values of Q1, Q2, Q3 and Q4, which are described in Table 17.
Table 17. Flow-rate Zones per OIML

FLOW-RATE ZONE DESCRIPTION
Q1 Lowest flow rate at which the meter is to operate within the maximum permissible errors.
Flow rate between the permanent flow rate and the minimum flow rate that divides the flow
Q2 rate range into two zones, the upper flow rate zone and the lower flow rate zone, each
characterized by its own maximum permissible errors.
Highest flow rate within the rated operating condition at which the meter is to operate within
Q3
the maximum permissible errors.
Highest flow rate at which the meter is to operate for a short period of time within the
Q4 maximum permissible errors, while maintaining its metrological performance when it is
subsequently operating within the rated operating conditions.
A water meter is designated by the numerical value of Q3 in m3/h and the ratio Q3/Q1. The value of Q3 and the
ratio of Q3/Q1 are selected from the lists provided in the OIML standards.
Water meters have to be designed and manufactured such that their errors do not exceed the maximum
permissible errors (MPE) defined in the standards. For example, in OIML standards, water meters need to be
designated as either accuracy class 1 or accuracy class 2, according to the requirements.
For class 1 water meters, the maximum permissible error in the upper flow rate zone (Q2 ≤ Q ≤ Q4) is ±1%, for
temperatures from 0.1°C to 30°C, and ±2% for temperatures greater than 30°C. The maximum permissible error
for the lower flow-rate zone (Q1 ≤ Q < Q2) is ±3%, regardless of the temperature range.
For class 2 water meters, the maximum permissible error for the upper flow rate zone (Q2 ≤ Q ≤ Q4) is ±2%, for
temperatures from 0.1°C to 30°C, and ±3% for temperatures greater than 30°C. The maximum permissible error
for the lower flow rate zone (Q1 ≤ Q < Q2) is ±5% regardless of the temperature range.
The flow meter accuracy specified in the standards dictates the required accuracy in the electronics used for
driving the ultrasonic transducers, circuits in the receiver path, and time measurement sub circuits. The stringent
accuracy required at lower flow rates would require a very low noise signal chain in the transmitter and receiver
circuits used in ultrasonic flow meters, as well as the ability to measure picosecond time intervals.
9.2.2.2.2 Transit-Time in Ultrasonic Flow-Meters

Transit-time ultrasonic flow meters works based on the principle that sound waves in a moving fluid travel faster
in the direction of flow (downstream), and slower in the opposite direction of flow (upstream).
The system requires at least two transducers. The first transducer operates as a transmitter during the upstream
cycle and as a receiver during the downstream cycle, and the second transducer operates as a receiver during
the upstream cycle and as a transmitter during the downstream cycle. An ultrasonic flow meter operates by
alternating transmit and receive cycles between the pair of transducers and accurately measuring the time-of-
flight both directions.

TDC1000, TDC1000-Q1
Trigger
START
Echo Pulse from

Transducer 2
Transducer B
TX1/RX2
Echo Pulse from

Transducer 1
Transducer A
TX2/RX1
STOP
Upstream Downstream
tBA tAB
Figure 58. Relation Between Transmit and Receive Pulses Upstream/Downstream
In this example, the upstream TOF is defined as:

H
P$# =
:? F R;
where
• l is the path length between the two transducers in meters (m)
• c is the speed of sound in water in meters per second (m/s)
• v is the velocity of the water in the pipe in meters per second (m/s) (8)
In this example, the downstream TOF is defined as:
H
P#$ =
:? + R;
where
• l is the path length between the two transducers in meters (m)
• v is the velocity of the water in the pipe in meters per second (m/s) (9)

TDC1000, TDC1000-Q1
The difference of TOF is defined as:

¿61( = P$# F P#$
where
• tBA is the upstream TOF from transducer B to transducer A in seconds (s)
• tAB is the downstream TOF from transducer A to transducer B in seconds (s) (10)
After the difference in time-of-flight (ΔTOF) is calculated, the water velocity inside the pipe can be related to the
ΔTOF using the following equation:
¿61( × ? 2
R=
2×H
where
• l is the path length between the two transducers in meters (m) (11)
Finally, the mass flow rate can be calculated as follows:
3 =G×R×#
where
• k is the flow-meter constant
• v is the velocity of the water in the pipe in meters per second (m/s)
• A is the cross-section area of the pipe in meters-squared (m2) (12)
9.2.2.2.3 ΔTOF Accuracy Requirement Calculation

Based on the minimum mass flow requirement and accuracy requirements in Table 16, the ΔTOF accuracy
needed can be calculated as follows:
1. Convert the mass flow rate to m3/s:
1D
3 = :0.015 I3 /D; l p = 4.167T10F6 I3 /O
3600 O
2. Calculate the flow velocity assuming k = 1:
3 4.167T10F6 I3 /O
R= = = 0.0236 I/O
G# 0.015 I 2
è@ A
2
3. Calculate the ΔTOF for the given speed of sound. In this example, a speed of sound c = 1400 m/s is
assumed:
2 × H × R (2)(0.06 I)(0.0236 I/O)
¿61( = = = 1.445 JO
?2 1400 I/O 2
4. The requirement of 5% accuracy for minimum flow will result in a ΔTOF accuracy of:
¿61(ANNKN = :0.05;:1.445 JO; = 72.25 LO
For this reason, this system requires a high accuracy timer/stopwatch that can measure the lower flow rate state.
9.2.2.2.4 Operation
The TDC1000 is used to drive the transmitter, amplify and filter the received signal and conditioning the echo for
START and STOP pulse generation. The TDC7200 ps-accurate timer is used to measure the time interval
between the rising edge of the START pulse and the rising edge of the STOP pulse produced by the TDC1000.
The microcontroller should first configure the TDC7200 and the TDC1000 for the measurement. When the
microcontroller issues a start command to the TDC7200 via the SPI interface, the TDC7200 sends a trigger pulse
to the TRIGGER pin of the TDC1000. When the TDC1000 drives the transmit transducer, a synchronous START
pulse is produced on the START pin, which commands the TDC7200 to start its counters. When a valid echo
pulse is received on the receive transducer, the TDC1000 generates a STOP pulse on the STOP pin, which
commands the TDC7200 to stop its counters. This procedure is repeated for the upstream and downstream
cycles.

TDC1000, TDC1000-Q1
A temperature measurement can be performed and the result can be used to correct for temperature
dependency of the speed of sound.
9.2.2.3 Application Curves

The following figures show data and histograms created with data collected under a zero flow condition at room
temperature. A simple offset calibration has been applied, where the overall average of the data is subtracted
from the data.
0.4
Raw calibrated data
0.3 10x running average
0.2
Delta time-of-flight (ns)
0.1
-0.1
-0.2
-0.3
-0.4
0 1000 2000 3000 4000 5000 6000
Samples (n)
Figure 59. Calibrated Raw and Averaged Delta Time-of-Flight Data
1800 1600
V = 82 ps V = 31 ps
1600 1400
1400
1200
1200
Number of hits
Number of hits
1000
1000
800
800
600
600
400
400
200 200
0 0
6
04
10
16
22
28
01
03
05
07
09
.2
.2
.1
.0
.0
.0
.0
.0
.0
.0
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
Delta time-of-flight (ns) Delta time-of-flight (ns)

Figure 60. Raw Calibrated Data Histogram Figure 61. 10x Running Average Data Histogram

TDC1000, TDC1000-Q1
10 Power Supply Recommendations

The analog circuitry of the TDC1000 is designed to operate from an input voltage supply range between 2.7V
and 5.5V. It is recommended to place a 100nF ceramic bypass capacitor to ground as close as possible to the
VDD pins. In addition, an electrolytic or tantalum capacitor with value greater than 1µF is recommended. The
bulk capacitor does not need to be in close vicinity with the TDC1000 and could be close to the voltage source
terminals or at the output of the voltage regulators powering the TDC1000.
The IO circuitry of the TDC1000 is designed to operate from an input voltage supply range between 1.8V and
5.5V. The IO voltage supply (VIO) can be lower than the analog voltage supply (VDD), but it should not exceed it.
It is also recommended to place a 100nF ceramic bypass capacitor to ground as close as possible to the VIO
pin. If a separate source or regulator is used for VIO, an additional electrolytic or tantalum capacitor with value
greater than 1µF is recommended.
In some cases an additional 10µF bypass capacitor may further reduce the supply noise.

TDC1000, TDC1000-Q1
11 Layout
11.1 Layout Guidelines

• In a 4-layer board design, the recommended layer stack order from top to bottom is: signal, ground, power
and signal.
• Bypass capacitors should be placed in close proximity to the VDD and VIO pins.
• The length of the START and STOP traces from the DUT to the stopwatch/MCU should be matched to
prevent uneven signal delays. Also, avoid unnecessary via-holes on these traces and keep the routing as
short/direct as possible to minimize parasitic capacitance on the PCB.
• Match the length of the TX pair from the DUT to the transducers to prevent uneven signal delays from one
channel direction to the other.
• Match the length of the RX pair from the transducers to the DUT to prevent uneven signal delays from one
channel direction to the other.
• Match the length (or resistance) of the traces leading to the RTD sensors. PCB series resistance will be
added in series to the RTD sensors.
• Route the SPI signal traces close together. Place a series resistor at the source of SDO (close to the DUT)
and series resistors at the sources of SDI, SCLK and CSB (close to the master MCU).
11.2 Layout Example

Matched TX pair length to transducers VIA to Ground Plane
Matched RX pair length from transducers
VIA to Bottom or Internal Layer
Top Layer
GND
Bottom Layer
GND
RX1 1 TX1
GND RX2 TX2 System Clock
VCOM GND
GND LNAOUT CLKIN
RTD1 PGAIN VDD
GND
TDC1000
PGAOUT VDD
COMPIN VIO
To RTDs: Match trace RTD1 SDO
length (resistance) RTD2 SDI MCU
RREF CSB SPI Master
GND CHSEL SCLK
RTD2 ERRB RESET
MCU
GND START TRIGGER I/Os
STOP EN Trigger:stop
watch/MCU
Matched
trace
length to
MCU stopwatch
I/Os /MCU
Figure 62. TDC1000 Board Layout (Capacitive Feedback Mode)

TDC1000, TDC1000-Q1
12 Device and Documentation Support
12.1 Device Support

12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support

For development support see the following:
• Automotive Ultrasonic Fluid Level/Quality Measurement Reference Design, TIDA-00322
12.2 Documentation Support

For related documentation see the following:
• TDC1000 Temperature Sensing Interface, SNAA218
12.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 18. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TDC1000 Click here Click here Click here Click here Click here
TDC1000-Q1 Click here Click here Click here Click here Click here
12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

TDC1000, TDC1000-Q1
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Mar-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TDC1000PW ACTIVE TSSOP PW 28 48 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 TDC1000PW

& no Sb/Br)
TDC1000PWR ACTIVE TSSOP PW 28 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 TDC1000PW
& no Sb/Br)
TDC1000QPWQ1 ACTIVE TSSOP PW 28 48 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 TDC1000
& no Sb/Br) PWQ1
TDC1000QPWRQ1 ACTIVE TSSOP PW 28 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 TDC1000
& no Sb/Br) PWQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Mar-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TDC1000, TDC1000-Q1 :
• Catalog: TDC1000
• Automotive: TDC1000-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Oct-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TDC1000PWR TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1
TDC1000QPWRQ1 TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Oct-2015
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TDC1000PWR TSSOP PW 28 2500 367.0 367.0 35.0
TDC1000QPWRQ1 TSSOP PW 28 2500 367.0 367.0 35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
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Product Sample & Technical Tools & Support & Reference

Folder Buy Documents Software Community Design

Changes from Revision A (December 2014) to Revision B Page

• Added PW package nomenclature throught document.......................................................................................................... 1

Changes from Original (October 2014) to Revision A Page

2 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated

Product Folder Links: TDC1000 TDC1000-Q1

5 Pin Configuration and Functions

(1) G = Ground, I = Input, O = Output, P = Power

Pin Functions (continued)

6.2 ESD Ratings

6.3 Recommended Operating Conditions

4 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated

Product Folder Links: TDC1000 TDC1000-Q1

6.4 Thermal Information (1)

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6.5 Electrical Characteristics

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Electrical Characteristics (continued)

(2) Specified by design.

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6.6 Timing Requirements

Figure 1. SPI Timing Diagram

6.7 Switching Characteristics

(1) Specified by design.

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6.8 Typical Characteristics

Output Impedance Magnitude (|_

Figure 2. LNA ZOUT vs Frequency Figure 3. PGA ZOUT vs Frequency

Input-referred Noise (nV/O,Ì

VDD = VIO = 3.1V Capacitive RL = ∞ VDD = VIO = 3.7V Gain of 21dB RL = ∞

Output Voltage (250mV/DIV)

Time (1s/DIV) Time (1s/DIV)

Figure 6. LNA Response Figure 7. PGA Response

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Typical Characteristics (continued)

Figure 8. LNA Gain vs Frequency Figure 9. PGA Gain vs Frequency

Time (ps) C009

Figure 10. RX Jitter Histogram Figure 11. RX Jitter Histogram

Time (ps) C011

Figure 12. RX Jitter Histrogam Figure 13. RX Jitter Histogram

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7 Parameter Measurement Information

CF3 = 51 pF RF2 = 5.1 N

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8.2 Functional Block Diagram

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8.3 Feature Description

8.3.2 Receiver Signal Path

Figure 15. TDC1000 Receiver Path

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Feature Description (continued)

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Output Impedance Magnitude (|_

Input-referred Noise (nV/O,Ì

Time (1s/DIV) Time (1s/DIV)

CF3 = 51 pF RF2 = 5.1 N

CF1 = 1 nF RF1 = 1 N CF2 = 50 pF

CF3 = 53 pF RF2 = 5 N