Frequency Divider D-Flip-flops

Frequency Division using flip-flops

In the Sequential Logic tutorials we saw how D-type Flip-Flop´s work and how they can be
connected together to form a Data Latch. Another useful feature of the D-type Flip-Flop is as a
Binary Divider, a Frequency Divider or as a "divide-by-2" counter. Here the inverted output
terminal Q (NOT-Q) is connected directly back to the Data input terminal D giving the device
"feedback" as shown below.

Divide-by-2 Counter

It can be seen from the frequency waveforms above, that by "feeding back" the output from Q to
the input terminal D, the output pulses at Q have a frequency that are exactly one half (f/2) that
of the input clock frequency. In other words the circuit has become a "Frequency Divider" as it
now divides the input frequency by a factor of two (an octave). This then produces another type
of device that can best be described as a "Toggle" or "T-type" flip-flop as it toggles from one
state to the next, (HIGH to LOW or LOW to HIGH) at every clock cycle.

Toggle Flip-Flop

A T-type or Toggle flip-flop is basically a JK-type flip-flop with its inputs tied together
resulting in a device with only two inputs, the "Toggle" input itself and the controlling "Clock"
input. If we connect together in series, two T-type flip-flops the initial input frequency will be
"divided-by-two" by the first flip-flop (f/2) and then "divided-by-two" again by the second flip-
flop ((f/2)/2), giving an output frequency which has efectively been divided four times, then its
output frequency becomes one quarter value (25%) of the original clock frequency, (f/4). Each
time we add another toggle or "T-type" flip-flop the output clock frequency is halved or divided-
by-2 again and so on, giving an output frequency of 2n where "n" is the number of flip-flops used
in the sequence.

Then the Toggle or T-type flip-flop is an edge triggered divide-by-2 device based upon the
standard RS-type flip flop. They can be triggered to switch on either the leading or trailing edge
of the input clock signal.

Divide-by-8 Counter

This type of counter is commonly known as an Asynchronous 3-bit Binary Counter as the
output on QA to QC, which is 3 bits wide, is a binary count from 0 to 7 for each clock pulse,
with the output of one flip-flop stage providing the clocking signal for the next flip-flop stage.
This arrangement is commonly known as Asynchronous as each clocking event occurs
independently. As the counter counts sequencially in an upwards direction from 0 to 7 this type
of counter is also known as an "up" or "forward" counter (CTU) or a "3-bit Asynchronous Up
Counter". Asynchronous "Down" counters (CTD) are also available

Truth Table for a 3-bit Asynchronous Up Counter

Clock Output bit Pattern
Cycle
QC QB QA

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1
 4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

Any number of flip-flops can be connected or "cascaded" together to form a "divide-by-n" binary
counter where "n" is the the number of counter stages used and which is generally called the
Modulus. The modulus or simply "MOD" of a counter is the number of output states the counter
goes through before returning itself back to zero, ie, one complete cycle. A counter with three
flip-flops like the circuit above will count from 0 to 7 ie, 2n-1. It has eight different output states
representing the decimal numbers 0 to 7 and is called a Modulo-8 or MOD-8 counter. A counter
with four flip-flops will count from 0 to 15 and is therefore called a Modulo-16 counter and so
on.

An example of this is given as.

 3-bit Binary Counter = 23 = 8 (modulo-8 or MOD-8)


 4-bit Binary Counter = 24 = 16 (modulo-16 or MOD-16)

 8-bit Binary Counter = 28 = 256 (modulo-256 or MOD-256)

The Modulo number can be increased by adding more flip-flops to the counter. Then the modulo
or MOD number can simply be written as: MOD number = 2n
4-bit Modulo-16 Counter

Multi-bit asynchronous counters connected in this manner are also called "Ripple" counters or
ripple dividers because the change of each stage appears to "ripple" itself through the counter
from the LSB output to it´s MSB output connection. Ripple counters are available in standard i.c.
form, from the 74LS393 Dual 4-bit counter to the 74HC4060, which is a 14-bit ripple counter
with its own built in clock oscillator. With asynchronous ripple divider circuits there is a small
delay between the arrival of the clock pulse and its output due to the internal circuitry of the gate.
This delay is called the Propogation Delay and in some cases can produce false output counts.
In large bit ripple counter circuits the delay of all the separate stages are added together to give a
summed delay at the end of the chain which is why asynchronous counters are generally not used
for in high frequency counting circuits with large numbers of bits. Then, the more flip-flops that
are added to an asynchronous counter the lower the maximum operating frequency becomes. To
overcome the problem of propogation delay Synchronous Counters were developed.
Asynchronous Decade Counter
The Decade Counter

In the previous Counter tutorial we saw that an Asynchronous binary counters can have 2n-1
counting states. But it is also possible to construct special counters with states less than their
maximum output number by forcing the counter to reset itself to zero at a pre-determined value
and these are called "truncated sequences".

If we take the modulo-16 ripple counter and modified it with additional logic gates it can be
made to give a decade (divide-by-10) counter output for use in standard decimal counting and
arithmetic circuits. Such counters are generally referred to as Decade Counters. A decade
counter requires resetting to zero when the output count reaches the decimal value of 10, ie.
when DCBA = 1010 and feed this back to the reset input. A counter with a count sequence from
binary "0000" (BCD = "0") through to "1001" (BCD = "9") is generally referred to as a BCD
Decade counter because its ten state sequence is that of a BCD code but binary decade counters
are also available.

Asynchronous Decade (decimal 10) Counter

The counter counts upwards on each leading edge of the input clock signal starting from "0000"
until it reaches an output "1010" (decimal 10). Both outputs QB and QD are now equal to logic
"1" and the output from the NAND gate changes state from logic "1" to a logic "0" level and
whose output is also connected to the CLEAR (CLR) inputs of all the J-K Flip-flops. This causes
all of the Q outputs to be reset back to binary "0000" on the count of 10. Once QB and QD are
both equal to logic "0" the output of the NAND gate returns back to a logic level "1" and the
counter restarts again from "0000". We now have a decade or Modulo-10 counter.

Clock Output bit Pattern Decimal

 Count QD QC QB QA Value

1 0 0 0 0 0

2 0 0 0 1 1

3 0 0 1 0 2

4 0 0 1 1 3

5 0 1 0 0 4

6 0 1 0 1 5

7 0 1 1 0 6

8 0 1 1 1 7

9 1 0 0 0 8

10 1 0 0 1 9

11 Counter Resets its Outputs back to Zero

Decade Counter Timing Diagram

Using the same idea of truncating counter output sequences, the above circuit could easily be
adapted to other counting cycles be simply changing the connections to the AND gate. For
example, a scale-of-twelve (modulo-12) can easily be made by simply taking the inputs to the
AND gate from the outputs at "QC" and "QD", noting that the binary equivalent of 12 is "1100"
and that output "QA" is the least significant bit (LSB).

Standard i.c. asynchronous counter packages available are the TTL 74LS90 programmable ripple
counter/divider which can be configured as a divide-by-2, divide-by-5 or any combination of
both. The 74LS390 is a very flexable dual decade driver i.c. with a large number of "divide-by"
combinations available ranging form 2, 4, 5, 10, 20, 25, 50, and 100.

Frequency Dividers

This ability of the counter to truncate sequences to produce a "divide-by-N" output means that
counters and especially ripple counters, can be used as frequency dividers to reduce a high clock
frequency down to a more usable value for use in digital clocks and timing applications. For
example, assume we require an accurate 1Hz timing signal to operate a digital clock. We could
quite easily produce a 1Hz square wave signal from a standard 555 timer chip but the
manufacturers datasheet tells us that it has a typical 1-2% timing error depending upon the
manufacturer, and at low frequencies a 2% error at 1Hz is not good. However the datasheet also
tells us that the maximum operating frequency of the 555 timer is about 300kHz and a 2% error
at this high frequency would be acceptable. So by choosing a higher timing frequency of say
262.144kHz and an 18-bit ripple (Modulo-18) counter we can make a precision 1Hz timing
signal as shown below.

Simple 1Hz timing signal using an 18-bit ripple counter/divider.

This is of course a very simple example of how to produce accurate frequencies, but by using
high frequency crystal oscillators and multi-bit frequency dividers, precision frequency
generators can be produced for for a range of applications ranging from clocks or watches to
event timing and even electronic piano/synthesizer music applications.
Synchronous Binary Counters
Synchronous Counter

In the Asynchronous binary counter tutorial, we saw that the output of one counter stage is
connected directly to the input of the next counter stage and so on along the chain, and as a result
the asynchronous counter suffers from what is known as "Propagation Delay". However, with
Synchronous Counters, the external clock signal is connected to the clock input of EVERY
individual flip-flop within the counter so that all of the flip-flops are clocked together
simultaneously (in parallel) at the same time giving a fixed time relationship. This results in all
the individual output bits changing state at exactly the same time with no ripple effect and
therefore, no propagation delay.

4-bit Synchronous Counter

It can be seen that the external clock pulses (pulses to be counted) are fed directly to each J-K
flip-flop in the counter chain and that both the J and K inputs are all tied together, but only in the
first flip-flop, flip-flop A (LSB) are they connected HIGH, logic "1" allowing the flip-flop to
toggle on every clock pulse.

The J and K inputs of flip-flop B are connected to the output "Q" of flip-flop A, but the J and K
inputs of flip-flops C and D are driven from AND gates which are also supplied with signals
from the input and output of the previous stage. If we enable each J-K flip-flop to toggle based
on whether or not all preceeding flip-flop outputs (Q) are "HIGH" we can obtain the same
counting sequence as with the asynchronous circuit but without the ripple effect, since each flip-
flop in this circuit will be clocked at exactly the same time. As there is no propagation delay in
synchronous counters because all the counter stages are triggered in parallel the maximum
operating frequency of this type of counter is much higher than that of a similar asynchronous
counter.
4-bit Synchronous Counter Waveform Timming Diagram.

Because the counter counts sequencially on every clock pulse the resulting outputs count
upwards from 0 ("0000") to 15 ("1111") therefore, this type of counter is also known as a "4-bit
Synchronous Up Counter".

Counters can count on either the "rising-edge" or the "falling-edge" of the clock pulse resulting
in one single count when the clock input changes state. Generally, synchronous counters count
on the rising-edge which is the low to high transition of the clock signal and asynchronous ripple
counters count on the falling-edge which is the high to low transition of the clock signal.

It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state,
but this makes it easier to link counters together because the most significant bit (MSB) of one
counter can drive the clock input of the next. This works because the next bit must change state
when the previous bit changes from high to low - the point at which a carry must occur to the
next bit. Synchronous counters usually have a carry-out and a carry-in pin for linking counters
together without introducing any propagation delays.
Bidirectional Counter
Count Down Counter

As well as counting UP from zero, it is sometimes necessary to count DOWN from a

predetermined value to zero and to produce an output that activates when the zero count or other
pre-set value is reached. This type of counter is normally referred to as a Down Counter,
(CTD). In a binary or BCD down counter, the count decreases by one for each external clock
pulse from some preset value. Special dual purpose i.c's such as the TTL 74LS193 or CMOS
CD4510 are 4-bit binary UP or DOWN counters which have an additional input pin to select
either the up or down count mode.

4-bit Count Down Counter

In the 4-bit counter above the output of each flip-flop changes state on the falling edge (1-to-0
transistion) of the CLK input which is triggered by the Q output of the previous flip-flop, rather
than by the Q output as in the UP counter configuration. As a result, each flip-flop will change
state when the previous one changes from 0 to 1 at its output, instead of changing from 1 to 0.

Bidirectional Counter

Both Synchronous and Asynchronous counters are capable of counting UP or counting DOWN,
but their is another more "Universal" type of counter that can count in both directions either UP
or DOWN and these are known as Bidirectional Counters. Bidirectional counters, or more
commonly UP/DOWN counters, are capable of counting in either direction through any given
count sequence and they can be reversed at any point within their count sequence by using an
additional control input as shown below.
Synchronous 3-bit UP/DOWN Counter

The circuit above is of a simple 3-bit UP/DOWN synchronous counter using JK flip-flops
configured to operate as toggle or T-type flip-flops giving a maximum count of zero (000) to
seven (111) and back to zero again. An additional input determines the direction of the count,
either UP or DOWN and the timing diagram gives an example of the counters operation as this
UP/DOWN input changes state.

Nowadays, both UP and DOWN counters are incorporated into standard i.c´s that are fully
programmable to count in both an UP and a DOWN direction from any preset value. Common
chips available are the 74HC190 4-bit BCD decade UP/DOWN counter to the CMOS 4029 4-bit
Synchronous UP/DOWN counter.