Panel Chimei Innolux v320bj3-p02 0

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PRODUCT SPECIFICATION
Ƒ Tentative Specification
ϭ Preliminary Specification
Ϯ Approval Specification
MODEL NO.: V320BJ3

SUFFIX: P02
32”HD_60Hz_Open Cell
Source Board + Control Board
Customer:
APPROVED BY SIGNATURE
Name / Title
Note
Please return 1 copy for your confirmation with your

signature and comments.
Refer to "V320” Incoming Inspection Spec
Approved By Checked By Prepared By
Chao-Chun Chung Vincent Chou Andy Chen
Version 2.0 1 Κ30 Oct 2011

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The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center www.panelook.com
- CONTENTS -
REVISION HISTORY ------------------------------------------------------- 3
1. GENERAL DESCRIPTION ------------------------------------------------------- 4

1.1 OVERVIEW
1.2 CHARACTERISTICS
1.3 MECHANICAL SPECIFICATIONS
2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 5

2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASED ON CMI MODULE V320BJ3-L02)
2.2 ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL)
2.3 ELECTRICAL ABSOLUTE RATINGS (OPEN CELL)
3. ELECTRICAL CHARACTERISTICS ------------------------------------------------------- 7

3.1 TFT LCD OPEN CELL
4. BLOCK DIAGRAM ------------------------------------------------------- 10

5. INPUT TERMINAL PIN ASSIGNMENT ------------------------------------------------------- 11

5.2 BLOCK DIAGRAM OF INTERFACE
5.3 LVDS INTERFACE
5.4 COLOR DATA INPUT ASSIGNMENT
5.5 PATTERN FOR Vcom ADJUSTMENT
6. INTERFACE TIMING ------------------------------------------------------- 17

6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE
7. OPTICAL CHARACTERISTICS ------------------------------------------------------- 21

7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS
8. PRECAUTIONS ------------------------------------------------------- 26
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
8.2 SAFETY PRECAUTIONS
9. DEFINITION OF LABELS ------------------------------------------------------- 28

9.1 OPEN CELL LABEL
9.2 CARTON LABEL
10. PACKAGING ------------------------------------------------------- 29

10.1 PACKING SPECIFICATIONS
10.2 PACKING METHOD
11. MECHANICAL DRAWING ------------------------------------------------------- 30

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REVISION HISTORY
Version Date Page(New) Section Description
Ver.1.0 Sep 15, 2011’ All All Preliminary Specification was first issued.
Ver.2.0 Oct. 25. 2011 All All
Approval Specification was first issued.

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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V320BJ3-P02 is a 315” TFT LCD cell with driver ICs and 1ch-LVDS interface. This module supports 1366 x
768 WXGA format and can display true 16.7M colors (8-bit)..
1.2 CHARACTERISTICS
CHARACTERISTICS ITEMS SPECIFICATIONS
Screen Diagonal [in] 31.5
Pixels [lines] 1366×768
Active Area [mm] 697.6845 (H) x 392.256 (V) (31.5” diagonal)
Sub -Pixel Pitch [mm] 0.17025 (H) x 0.51075 (V)
Pixel Arrangement RGB vertical stripe
Weight [g] 940
Physical Size [mm] 716.1(W) x 410(H) x 1.35(D) Typ.
Display Mode Transmissive mode / Normally black
Contrast Ratio (3500:1) Typ.
(Typical value measured at CMI’s module)
Glass thickness (Array/CF) [mm] 0.5 / 0.5
Viewing Angle (CR>20) +88/-88(H),+88/-88(V) Typ.
(Typical value measured at CMI’s module)
Color Chromaticity R=0.654, 0.330
G=0.274, 0.596
B=0.130, 0.130
W=0.305, 0.360
(With C source)
Cell Transparency [и] 5.2%Typ.
(Typical value measured at CMI’s module: V320BJ3-L02)
Polarizer (CF side) Super Wide View Anti-glare coating, 709.7(W) x 405(H)
Hardness:3H
Polarizer (TFT side) Super Wide View, 709.7(W) x 405(H).
1.3 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note
Weight 940 g -
I/F connector mounting The mounting inclination of the connector makes
(2)
position the screen center within ±0.5mm as the horizontal.
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
(2) Connector mounting position

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Value
Item Symbol Unit Note
Min. Max.
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.

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2.2 PACKAGE STORAGE

When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS

2.3.1 TFT LCD MODULE
Value
Item Symbol Unit Note
Min. Max.
Power Supply Voltage VCC -0.3 13.5 V

(1)
Logic Input Voltage VIN -0.3 3.6 V

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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol Unit Note
Min. Typ. Max.
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Rush Current IRUSH －－ 1.86 A
White Pattern PT 3.46 － W
Power consumption Horizontal Stripe PT 5.2 5.62 W (2)
Black Pattern PT － 3.2 － W
White Pattern －－ 0.3 － A

Power Supply
Current
Horizontal Stripe －－ 0.44 0.52 A (3)
Black Pattern －－ 0.27 － A

Differential Input High
VLVTH +100 －－ mV
Threshold Voltage
Differential Input Low
VLVTL －－ -100 mV
Threshold Voltage
LVDS Common Input Voltage VCM 1.0 1.2 1.4 V (4)
interface
Differential input
voltage |VID| 200 － 600 mV
(single-end)
Terminating Resistor RT － 100 － ohm
Input High Threshold
VIH 2.7 － 3.3 V
CMIS Voltage
interface Input Low Threshold
VIL 0 － 0.7 V
Voltage
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:

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Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
GND
470us
Note (3) The specified power supply current and power consumption is under the conditions at Vcc = 12 V,
Ta = 25 ± 2 ºC, fv = 60 Hz, whereas a power dissipation check pattern below is displayed.
a. White Pattern b. Black Pattern
Active Area Active Area

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c. Horizontal Pattern
Note (4) The LVDS input characteristics are as follows:
/9'6
_9,'_
/9'6
9&0
*1'
_9,'_
9
/9'6

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4. BLOCK DIAGRAM
RX0(+/-) FRAME BUFFER

(YEONHO 10031HR-30 or
SCAN DRIVER IC
UNE FZC8A030TF13 or
INPUT CONNECTOR
RX1(+/-) TFT LCD PANEL
RX2(+/-) (1366x3x768)
compatible)
RX3(+/-) TIMING
RXCLK(+/-)
CONTROLLER
Vcc
GND
DC/DC CONVERTER & DATA DRIVER IC
SELLVDS
REFERENCE VOLTAGE

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5. INTERFACE PIN CONNECTION

CNF1 Connector Pin Assignment
Pin No. Symbol Description Note
1 NC No connection (3)
2 SCL EEPROM Serial Clock
3 SDA EEPROM Serial Data
4 GND Ground
5 RX0- Negative transmission data of pixel 0
6 RX0+ Positive transmission data of pixel 0
7 GND Ground
10 GND Ground
13 GND Ground
14 RXCLK- Negative of clock
15 RXCLK+ Positive of clock
16 GND Ground
19 GND Ground
20 NC No connection (3)
21 SELLVDS Select LVDS data format (2)(4)
22 WP EEPROM Write Protection
23 GND Ground
24 GND Ground
25 GND Ground
26 VCC Power supply: +12V
Note (1) Connector type: 196422-30041-3 (P-TWO)
LVDS connector pin orderdefined as follows
Note (2) Low = Open or connect to GND: JEIDA Format, High = Connect to +3.3V: VESA Format.
Note (3) Reserved for internal use. Please leave it open.

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Note (4) LVDS signal pin connected to the LCM side has the following diagram. R1 in the system side should
be less than 1K Ohm. (R1 < 1K Ohm)

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5.2 BLOCK DIAGRAM OF INTERFACE

CNF1
Rx0+ 51Ө
100pF Rx
TxIN Rx0- R0-R7
R0-R7 51Ө
Rx1+ 51Ө G0-G7
G0-G7 100pF
Rx1-
51Ө B0-B7
B0-B7
Rx2+ 51Ө
100pF
DE Rx2- DE
51Ө
Rx3+ 51Ө
100pF
Rx3-
51Ө
Host
CLK+ 51Ө
Graphics PLL 100pF DCLK
CLK- PLL
Controller 51Ө Timing
Controller
Tvd LVDS Receiver
THC63LVDF84A
R0~R7 : Pixel R Data

G0~G7 : Pixel G Data
B0~B7 : Pixel B Data
DE : Data Enable Signal
DCLK : Data clock signal
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially

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5.3 LVDS INTERFACE

VESA LVDS formatΚ(SELLVDS pin=H)
JEIDA LVDS formatΚ(SELLVDS pin= L or open)
R0~R7: Pixel R Data (7; MSB, 0; LSB)

G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE: Data enable signal
Notes(1) RSVD(reserved)pins on the transmitter shall be “H” or( “L” or OPEN)

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5.4 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color.
The higher the binary input, the brighter the color. The table below provides the assignment of the color versus data
input.
Data Signal
Color Red Green Blue
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Basic Blue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Colors Cyan 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Magenta 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Red(0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(1) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(2) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Red(253) 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red
Red(254) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(255) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green(0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Green(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Green(253) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0
Green
Green(254) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
Green(255) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Blue(0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Blue(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Blue(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Blue(253) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1
Blue
Blue(254) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0
Blue(255) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Note (1) 0: Low Level Voltage, 1: High Level Voltage

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5.5 PATTERN FOR Vcom ADJUSTMENT

Sub-pixel on and off pattern
Gray level = 128
(2) Adjustment method: (Digital V-com)

Programmable memory IC is used for Digital V-com adjustment in this model. CMI provide Auto Vcom tools
to adjust Digital V-com.The detail connection and setting instruction, please directly contact with Account
FAE or refer CMI Auto V-com adjustment OI. Below items is suggested to be ready before Digital V-com
adjustment in customer LCM line.
a. USB Sensor Board
b. Programmable software

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6.1 INPUT SIGNAL TIMING SPECIFICATIONS (Ta = 25 ± 2 ºC)

The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note

Fclkin
Frequency 60 76 80 MHz
(=1/TC)
Input cycle to
LVDS Trcl Ё Ё 200 ps (3)
cycle jitter
Receiver Spread spectrum
Clock Fclkin_mod Fclkin-2% Ё Fclkin+2% MHz
modulation range
(4)
Spread spectrum
FSSM 200 KHz
modulation frequency
LVDS Setup Time Tlvsu 600 Ё Ё ps
Receiver (5)
Data Hold Time Tlvhd 600 Ё Ё ps
Fr5 50 Hz
Frame Rate
Fr6 60 Hz
Vertical
Active Total Tv 796 806 816 Th Tv=Tvd+Tvb
Display
Term Display Tvd 768 768 768 Th Ё
Blank Tvb 28 38 48 Th Ё
Total Th 1540 1560 1610 Tc Th=Thd+Thb

Horizontal
Active
Display Thd 1366 1366 1366 Tc Ё
Display
Term
Blank Thb 174 194 244 Tc Ё
Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low
logic level. Otherwise, this module would operate abnormally.
Note (2) Please make sure the range of pixel clock has follow the below equationΚ
Fclkin(max) Њ Fr6 Ѽ Tv Ѽ Th
Fr5 Ѽ Tv Ѽ Th Њ Fclkin(min)

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INPUT SIGNAL TIMING DIAGRAM
Tv
Tvd
Tvb
DE
Th
DCLK
Tc
Thd
Thb
DE
DATA Valid display data (1366)
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI

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Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T 3T 5T 7T 9T 11T 13T
14 14 14 14 14 14 14

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6.2 POWER ON/OFF SEQUENCE

(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram
below.
Power Supply 0.9 VCC 0.9 VCC
VCC
0.1VCC 0.1Vcc
0V
0.5ЉT1Љ10ms T1 T3
0ЉT2Љ50ms
0ЉT3Љ50ms
500ms ЉT4 T2 T4
VALID
LVDS Signals
0V
Power On Power Off
0ЉT7ЉT2
0ЉT8ЉT3
T7 T8
Option Signals
(SELLVDS)
Backlight (Recommended) 50% 50%

500msЉT5
100msЉT6
T5 T6
Power ON/OFF Sequence
Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If
T2<0, that maybe cause electrical overstress failures.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.

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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
o
Ambient Temperature Ta 25±2 C
Ambient Humidity Ha 50±10 %RH
Supply Voltage VCC 5.0 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Inverter Current IL 10.5±0.5 mA
Inverter Driving Frequency FL 63±3 KHz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring in a windless room.

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7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown as below. The following items
should be measured under the test conditions described in 7.1 and stable environment shown in Note (5).
Item Symbol Condition Min. Typ. Max. Unit Note
Rx 0.654 -
Red
Ry 0.330 -
Gx θ x=0° , θ Y =0° 0.275 -
Green
Color Gy Viewing angle at 0.596 -
Typ.-0.03 Typ+0.03 (0),(5)
Chromaticity Bx normal direction 0.130 -
Blue
By With C source 0.130 -
Wx 0.305 -
White
Wy 0.360 -
Center Transmittance T% θ x=0° , θ Y =0° - 5.2 % (1), (7)
Contrast Ratio CR With CMO Module 2600 3500 - (1), (3)
Gray to θ x=0° , θ Y =0°
Response Time gray With CMO - 8.5 ms (1), (4)
average Module@60Hz
θ x=0° , θ Y =0°
White Variation δW 1.3 - (1), (6)
With CMO Module
θ x+ 80 88 -
Horizontal
θ x- CR≥20 80 88 -
Viewing Angle Deg. (1), (2)
θ Y+ With CMO Module 80 88 -
Vertical
θ Y- 80 88 -
Note (0) Light source is the standard light source “C” which is defined by CIE and driving voltages are based on
suitable gamma voltages. The calculating method is as following:
1. Measure Module’s and BLU’s spectrums. W, R, G, B are with signal input. BLU(for V315B5-L10) is
supplied by
2. Calculate cell’s spectrum.
3. Calculate cell’s chromaticity by using the spectrum of standard light source “C”
Note (1) Light source is the BLU which supplied by CMI and driving voltage are based on suitable gamma voltages.
Note (2) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by Autronic Conoscope Cono-80.

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Normal
θx = θy = 0º
θy- θ y+
θ X- = 90º x- 12 o’clock direction

y+
θx− θ y+ = 90º
θx+
6 o’clock
y- x+ θ X+ = 90º
θ y- = 90º
Note (3) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.
Surface Luminance of L255
Contrast Ratio (CR) =
Surface Luminance of L0
L255: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).
Note (4) Definition of Gray-to-Gray Switching Time:
100%
90%
Optical
Response
10%
0%
Time
Gray to gray Gray to gray
Switching time Switching time
The driving signal means the signal of gray level 0, 31, 63, 95, 127, 159, 191, 223 and 255.
Gray to gray average time means the average switching time of gray level 0, 31, 63, 95, 127, 159, 191,
223 and 255 to each other.

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Note (5) Definition of Response Time (TR, TF):
Gray Level 255 Gray Level 255
100%
90%
Optical
Gray Level 0
Response
10%
0%
Time
TR TF
Note (6) Definition of White Variation (δW):

Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
where L (X) is corresponding to the luminance of the point X at the figure below.
Horizontal Line
D
D/4 D/2 3D/4
Vertical Line
W/4 1 2
W W/2 5 X : Test Point
X=1 to 5
3W/4 3 4
Active Area
Note (7) Definition of Transmittance (T%):

Measure the luminance of gray level 255 at center point of LCD module
Luminance of LCD module

Transmittance = Ϡ 100%
Luminance of backlight

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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly.
(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The dust
and oil may cause electrical short or worsen the polarizer.
(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
(5) The distance between COF edge and rib of BLU must bigger than 5mm. This can prevent the damage of COF
when assemble the module.
(6) Do not design sharp-pointed structure / parting line / tooling gate on the COF position of plastic parts, because
the burr will scrape the COF.
(7) If COF would bended to assemble in the module. Do not put the IC location on the bending corner of COF.
(8) The gap between COF IC and any structure of BLU must bigger than 2mm. This can prevent the damage of
COF IC
(9) Bezel opening must have no burr. Burr will scrape the panel surface.
(10)Bezel of module and bezel of set can not press or touch the panel surface. It will make light leakage or scrape.
(11)When module used FFC / FPC, but no FFC / FPC to be attached in the open cell. Customer can refer the FFC
/ FPC drawing and buy it by self.
(12)The gap between Panel and any structure of Bezel must bigger than 2mm. This can prevent the damage of
Panel.
(13)Do not plug in or pull out the I/F connector while the module is in operation.
(14)Do not disassemble the module.
(15)Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
(16)Moisture can easily penetrate into LCD module and may cause the damage during operation.
(17)When storing modules as spares for a long time, the following precaution is necessary.
AΕDo not leave the module in high temperature, and high humidity for a long time. It is highly recommended
to store the module with temperature from 0 to 35кat normal humidity without condensation.
BΕThe module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or f
luorescent light.
(18)When ambient temperature is lower than 10ºC, the display quality might be reduced

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8.2 SAFETY PRECAUTIONS

(1) The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
After the module’s end of life, it is not harmful in case of normal operation and sto

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9. DEFINITION OF LABELS
9.1 OPEN CELL LABEL
The barcode nameplate is pasted on each open cell as illustration for CMI internal control.
V320BJ3-P02 Rev.XX
Made in China
9.2 CARTON LABEL

The barcode nameplate is pasted on each box as illustration, and its definitions are as following explanation.
(a) Model Name: V320BJ3-P02

(b) Carton ID: CM0 internal control
(c) Quantities: 10

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10. PACKAGING
10.1 PACKING SPECIFICATIONS
(1) 10 LCD TV Panels / 1 Box
(2) Box dimensions : 810 (L) X 555 (W) X92 (H)mm
(3) Weight : approximately 16Kg ( 10 panels per box)
(4) 260 LCD TV Panels / 1 Group
10.2 PACKING METHOD

Figures 9-1 and 9-2 are the packing method
PP Belt
Film
Label
(L1150*W850*H140mm)
Figure.9-1 packing method

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Figure.9-2 packing method

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11. Mechanical Drawing

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MODEL NO.: V320BJ3

Source Board + Control Board

Please return 1 copy for your confirmation with your

Approved By Checked By Prepared By

Chao-Chun Chung Vincent Chou Andy Chen

Version 2.0 1 Κ30 Oct 2011

1. GENERAL DESCRIPTION ------------------------------------------------------- 4

2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 5

3. ELECTRICAL CHARACTERISTICS ------------------------------------------------------- 7

4. BLOCK DIAGRAM ------------------------------------------------------- 10

5. INPUT TERMINAL PIN ASSIGNMENT ------------------------------------------------------- 11

6. INTERFACE TIMING ------------------------------------------------------- 17

7. OPTICAL CHARACTERISTICS ------------------------------------------------------- 21

9. DEFINITION OF LABELS ------------------------------------------------------- 28

10. PACKAGING ------------------------------------------------------- 29

11. MECHANICAL DRAWING ------------------------------------------------------- 30

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1.3 MECHANICAL SPECIFICATIONS

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2. ABSOLUTE MAXIMUM RATINGS

Storage Temperature TST -20 +60 ºC (1)

Operating Ambient Temperature TOP 0 50 ºC (1), (2)

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2.2 PACKAGE STORAGE

2.3 ELECTRICAL ABSOLUTE RATINGS

Power Supply Voltage VCC -0.3 13.5 V

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Power Supply Voltage VCC 10.8 12 13.2 V (1)

Rush Current IRUSH － － 1.86 A

White Pattern PT 3.46 － W

Power consumption Horizontal Stripe PT 5.2 5.62 W (2)

Black Pattern PT － 3.2 － W

White Pattern － － 0.3 － A

Black Pattern － － 0.27 － A

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Vcc rising time is 470us

a. White Pattern b. Black Pattern

Active Area Active Area

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Note (4) The LVDS input characteristics are as follows:

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RX0(+/-) FRAME BUFFER

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5. INTERFACE PIN CONNECTION

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5.2 BLOCK DIAGRAM OF INTERFACE

R0~R7 : Pixel R Data

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5.3 LVDS INTERFACE

JEIDA LVDS formatΚ(SELLVDS pin= L or open)

R0~R7: Pixel R Data (7; MSB, 0; LSB)

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5.4 COLOR DATA INPUT ASSIGNMENT

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5.5 PATTERN FOR Vcom ADJUSTMENT

Gray level = 128

(2) Adjustment method: (Digital V-com)

Rush Current IRUSH －－ 1.86 A

White Pattern －－ 0.3 － A

Black Pattern －－ 0.27 － A