module vending_machine(nw_pa,clk,coin,rst);

output reg nw_pa;

input [1:0] coin;
input clk,rst;
reg [1:0] state;
reg [1:0] next_state;

parameter [1:0] s0=2'b00;

parameter [1:0] s5=2'b01;
parameter [1:0] s10=2'b10;
parameter [1:0] s15=2'b11;

always @(posedge clk)

begin
if (rst)
state=s0;
else
state=next_state;
end

always @(state,coin)
begin
case (state)
s0:
begin
if (coin==2'b00)
next_state=s0;
else
if (coin==2'b01)
next_state=s5;
else
if (coin==2'b10)
next_state=s10;
end
s5:
begin
if (coin==2'b00)
next_state=s5;
else
if (coin==2'b01)
next_state=s10;
else
if (coin==2'b10)
next_state=s15;
end
 s10:
begin
if (coin==2'b00)
next_state=s10;
else
if (coin==2'b01)
next_state=s15;
else
if (coin==2'b10)
next_state=s15;
end
s15:
begin
next_state=s0;
end
default : next_state=s0;

endcase // case (state)

end // always @ (state,next_state)

always @(state)
begin
case (state)
s0 : nw_pa<=1'b0;
s5 : nw_pa<=1'b0;
s10: nw_pa<=1'b0;
s15: nw_pa<=1'b1;
default: nw_pa<=1'b0;
endcase // case (state)
end

endmodule
2)

Code Verilog - [expand]

1 module test(clk,coin,reset,change,vend_out);
2
3 input clk,reset;
4 input [2:0] coin;
5 output reg vend_out;
6 output reg [2:0] change;
7
8 parameter [3:0] idle=4'b0000;
9 parameter [2:0]nickle=3'b001;
10 parameter [2:0]dime=3'b010;
11 parameter [2:0]quarter=3'b011;
12 parameter [2:0]nickle_dime=3'b100;
13 parameter [2:0]two_dime=3'b101;
14 parameter [2:0]quarter_nickle=3'b110;
15 parameter [2:0]quarter_dime=3'b111;
16
17 parameter [3:0]five=4'b0001;
18 parameter [3:0]ten=4'b0010;
19 parameter [3:0]fifteen=4'b011;
20 parameter [3:0]tweenty=4'b0100;
21 parameter [3:0]tweenty_five=4'b0101;
22 parameter [3:0]thirty=4'b110;
23 parameter [3:0]thirty_five=4'b111;
24 parameter [3:0]fourty=4'b1000;
25 parameter [3:0]fourty_five=4'b1001;
26 parameter [3:0]fifty=4'b1010;
27
28 reg [3:0] state, next_state;
29
30
31
32 always@(posedge clk, negedge reset) begin
33 if(!reset)
34 state<=idle;
35 else state<=next_state;
36 end
37
38 always@(coin,state) begin
39
40 case(state)
41 idle: case(coin)
42 nickle:begin
43 next_state= five;
44 change=3'b000;
45 vend_out=1'b0;
Code Verilog - [expand]
46 end
47 dime:begin
48 next_state= ten;
49 change=3'b000;
50 vend_out=1'b0;
51 end
52 quarter:begin
53 next_state= tweenty_five;
54 change=3'b000;
55 vend_out=1'b0;
56 end
57 default:begin
58 next_state=idle;
59 change=3'b000;
60 vend_out=1'b0;
61 end
62 endcase
63 five: case(coin)
64 nickle: next_state=ten;
65 dime : next_state=fifteen;
66 quarter : next_state=thirty;
67 default:next_state=nickle;
68 endcase
69 ten: case(coin)
70 nickle:next_state=fifteen;
71 dime: next_state=tweenty;
72 quarter:next_state=thirty_five;
73 default:next_state=dime;
74 endcase
75 fifteen:case(coin)
76 nickle:next_state=tweenty;
77 dime:next_state=thirty_five;
78 quarter:begin
79 next_state=idle;
80 vend_out=1'b1;
81 change=3'b000;
82 end
83 default:next_state=fifteen;
84 endcase
85 tweenty:case(coin)
86 nickle:next_state=tweenty_five;
87 dime:next_state=thirty;
88 quarter:begin
89 next_state=idle;
90 change=nickle;
91 vend_out=1'b1;
92 end
Code Verilog - [expand]
93 default:next_state=tweenty;
94 endcase
95 tweenty_five:case(coin)
96 nickle:next_state=thirty;
97 dime:next_state=thirty_five;
98 quarter:begin
99 next_state=idle;
100 change=dime;
101 vend_out=1'b1;
102 end
103 default:next_state=tweenty_five;
104 endcase
105 thirty:case(coin)
106 nickle:begin
107 next_state=thirty_five;
108 change=3'b000;
109 vend_out=1'b0;
110 end
111 dime:begin
112 next_state=idle;
113 vend_out=1'b1;
114 change=3'b000;
115 end
116 quarter:begin
117 next_state=idle;
118 change=nickle_dime;
119 vend_out=1'b1;
120 end
121 default:next_state=thirty;
122 endcase
123 thirty_five:case(coin)
124 nickle:begin
125 next_state=idle;
126 vend_out=1'b1;
127 change=3'b000;
128 end
129 dime:begin
130 next_state=idle;
131 change=nickle;
132 vend_out=1'b1;
133 end
134 quarter:begin
135 next_state=idle;
136 change=two_dime;
137 vend_out=1'b1;
138 end
139 default:next_state=thirty_five;
Code Verilog - [expand]
140 endcase
141 fourty:case(coin)
142 nickle:begin
143 next_state=idle;
144 change=nickle;
145 vend_out=1'b1;
146 end
147 dime:begin
148 next_state=idle;
149 change=dime;
150 vend_out=1'b1;
151 end
152 quarter:begin
153 next_state=idle;
154 change=quarter;
155 vend_out=1'b1;
156 end
157 default:begin
158 next_state=idle;
159 vend_out=1'b1;
160 change=3'b000;
161 end
162 endcase
163 fourty_five:case(coin)
164 nickle:begin
165 next_state=idle;
166 change=dime;
167 vend_out=1'b1;
168 end
169 dime:begin
170 next_state=idle;
171 change=nickle_dime;
172 vend_out=1'b1;
173 end
174 quarter:begin
175 next_state=idle;
176 change=quarter_nickle;
177 vend_out=1'b1;
178 end
179 default:begin
180 next_state=idle;
181 change=nickle;
182 vend_out=1'b1;
183 end
184 endcase
185 fifty:case(coin)
186 nickle:begin
Code Verilog - [expand]
187 next_state=idle;
188 change=nickle_dime;
189 vend_out=1'b1;
190 end
191 dime:begin
192 next_state=idle;
193 change=two_dime;
194 vend_out=1'b1;
195 end
196 quarter:begin
197 next_state=idle;
198 change=quarter_dime;
199 vend_out=1'b1;
200 end
201 default:begin
202 next_state=idle;
203 change=dime;
204 vend_out=1'b1;
205 end
206 endcase
207 default:begin
208 next_state=idle;
209 change=3'b000;
210 vend_out=1'b0;
211 end
212 endcase
213 end
214 endmodule
3) module candy(d,n,q, reset, clk, y);
output reg y;
input d,n,q; //n=5,d=10,q=25;
input clk;
input reset;
reg [2:0] cst, nst;
parameter S0 = 3'b000,
S1 = 3'b001,
S2 = 3'b010,
S3 = 3'b100,
S4 = 3'b101,
S5 = 3'b110,
S6 = 3'b111;
always @(cst or d or n or q)
begin
case (cst)
S0: if (n== 1'b1 && d==1'b0 && q==1'b0)
begin
nst = S1;
y=1'b0;
end
else if(n== 1'b0 && d==1'b1 && q==1'b0)
begin
nst=S2;
y=1'b0;
end
else if(n== 1'b0 && d==1'b0 && q==1'b1)
begin
nst=S5;
y=1'b0;
end
else
begin
nst = cst;
y=1'b0;
end
S1: if (n== 1'b1 && d==1'b0 && q==1'b0)
begin
nst = S2;
y=1'b0;
end
else if(n== 1'b0 && d==1'b1 && q==1'b0)
begin
nst=S3;
y=1'b0;
end
else if(n== 1'b0 && d==1'b0 && q==1'b1)
begin
nst=S6;
y=1'b0;
end
else
begin
nst = cst;
y=1'b0;
end
S2:if (n== 1'b1 && d==1'b0 && q==1'b0)
begin
nst = S3;
 y=1'b0;
end
else if(n== 1'b0 && d==1'b1 && q==1'b0)
begin
nst=S4;
y=1'b0;
end
else if(n== 1'b0 && d==1'b0 && q==1'b1)
begin
nst=S0;
y=1'b1;
end
else
begin
nst = cst;
y=1'b0;
end
S3: if (n== 1'b1 && d==1'b0 && q==1'b0)
begin
nst = S4;
y=1'b0;
end
else if(n== 1'b0 && d==1'b1 && q==1'b0)
begin
nst=S5;
y=1'b0;
end
else if(n== 1'b0 && d==1'b0 && q==1'b1)
begin
nst=S0;
y=1'b1;
end
else
begin
nst = cst;
y=1'b0;
end
S4: if (n== 1'b1 && d==1'b0 && q==1'b0)
begin
nst = S5;
y=1'b0;
end
else if(n== 1'b0 && d==1'b1 && q==1'b0)
begin
nst=S6;
y=1'b0;
end
else if(n== 1'b0 && d==1'b0 && q==1'b1)
begin
nst=S0;
y=1'b1;
end
else
begin
nst = cst;
y=1'b0;
end
S5: if (n== 1'b1 && d==1'b0 && q==1'b0)
begin
nst = S6;
y=1'b0;
 end
else if(n== 1'b0 && d==1'b1 && q==1'b0)
begin
nst=S0;
y=1'b1;
end
else if(n== 1'b0 && d==1'b0 && q==1'b1)
begin
nst=S0;
y=1'b1;
end
else
begin
nst = cst;
y=1'b0;
end
S6: if (n== 1'b1 && d==1'b0 && q==1'b0)
begin
nst =S0;
y=1'b1;
end
else if(n== 1'b0 && d==1'b1 && q==1'b0)
begin
nst=S0;
y=1'b1;
end
else if(n== 1'b0 && d==1'b0 && q==1'b1)
begin
nst=S0;
y=1'b1;
end
else
begin
nst = cst;
y=1'b0;
end

default: nst = S0;

endcase
end
always@(posedge clk) //or posedge reset)
begin
if (reset)
cst <= S0;
else
cst <= nst;
end
endmodule

TEST BENCH

module candy_tb;
reg n,d,q,clk,reset;
wire y;
candy m1(n,d,q,reset, clk, y);
initial
begin
reset=0 ;clk=0;n=0;q=0;d=0;
$monitor($time, ,
,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",d,,"n=%b",n,,"q=%b",q);
#10 d=0;n=1;q=0;
#10 d=1;n=0;q=0;
#10 d=1;n=0;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=0;q=0;
end
always
#5 clk=~clk;
initial
#100 $finish ;

endmodule