Overview

sequential circuits
• adding state to combinational circuits
• clocks
Flip flops and flip-flops
sequential circuits •
•
a state-holding component
there are several of them: SR,D,JK and T
Lecture 5 — § 1.6-1.7 • excitation tables
Computer Science 218 designing a sequential circuit
• state tables and diagrams
Mike Feeley • some examples

Flip flops Building a flip flop

one-bit memory element some initial attempts
• latches input for one clock cycle • consider x
not good because x is unstable (i.e., x=x´)
several types –

S Q
• a bit better
• S – y = x´, x = y´ y x
>C
R – possible states are xy=01 or 10
•
– can’t set values
• D D Q
>C how about this?
• • if S=0 and R=0
• JK J Q
– x=Q´, Q=x´ S x
>C • if S=1 and R=0 what if S=1 and R=1?
• K
– Q = (R+x)´ = (R + (S+Q)´)´ = 1 Q Q = (1 + (1 + Q)´)´ = 0
R
– S→0, value is saved x = (1 + (1 + x)´)´ = 0
• T T Q
>C • if S=0 and R=1 don’t do this
– Q = (R+x)´ = (R + (S+Q)´)´ = 0
3 – R→0, value is saved 4
SR flip flop Edge-triggered flip flops
characteristic table S Q most common way to build synchronized flip-flop
>C
S R Q(t+1) • flip-flop latches on rising (falling) edge of clock
R
0 0 Q(t) S = set – rising edge is called positive, falling edge is called negative
0 1 0 R = reset
• holds value until clock starts next rise (or fall for negative)
1 0 1
1 1 ? how the flip flop latches
• setup time – before transition when input cannot change
add a clock S x • threshold voltage – transition
• so we can ignore propagation delays • hold time – after transition when input cannot change
C Q
• but when C=1, have the same problem R

master-slave SR flop flop

• solves problem
S S Q
– when one FF is “pulsed” other is stable S Q
• another approach in the R R input must not change output does not change
R
– clock-edge triggered
C
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Edge-triggered flip flops How edge triggering works

exaggerated view of clock cycle
key idea
• ensure stable FF output using narrow window to capture input
• most of the time output is saved FF state
• output=input only for narrow region on clock edge
flip flop latching characteristic values
output does not change
• threshold voltage
– voltage at which FF begins to produce new output
input cannot change
• setup time
– time before threshold voltage is reached when input cannot change
– allows input voltage to settle in FF illustration of timing requirements a D Q b D Q c
• hold time
on each clock “pulse” (rising or falling edge): >C >C
– time after threshold voltage is reached when input cannot change •!ci+1 = bi
– allows input voltage to be reliably captured by FF X Y
•!bi+1 = a
• propagational delay
both flip flops are pulsed at once
– time after threshold voltage is reached that it takes FF to output a new value • X’s new output is delayed until after Y’s hold time
– delay ≥ hold time
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D flip flop T flip flop
T Q
similar to SR D
>C
Q
characteristic table >C
• D = S+R T Q(t+1)
• gets rid of S=1,R=1 undefined state 0 Q(t) T = toggle
1 Q´(t)
characteristic table
D Q(t+1)
0 0
D = data • Q(t+1) = Q(t) T
1 1

• Q(t+1) = D
to leave state unchanged
• don’t pulse the clock

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JK flip flop Flip flop excitation table

J Q
characteristic table >C describes state transitions of flip-flop
K
J K Q(t+1) • used when designing circuit using flip flops
0 0 Q(t)
like SR, but with 11 defined excitation tables for the flip flops we know
0 1 0
1 0 1 Q(t) Q(t+1) S R Q(t) Q(t+1) D
1 1 Q(t)´ 0 0 0 x 0 0 0
0 1 1 0 0 1 1
1 0 0 1 1 0 0
1 1 x 0 1 1 1

J
T Q Q(t) Q(t+1) J K Q(t) Q(t+1) T
K >C 0 0 0 x 0 0 0
0 1 1 x 0 1 1
1 0 x 1 1 0 1
1 1 x 0 1 1 0

most popular flip flop

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Sequential circuit behaviour Key idea
composed of sequential circuit is d e f
• combination circuit plus memory (state) u
• combinational circuit a combinational
• flip flops are its memory (one per bit) b v flip
– just like before circuit
c w flops
• flip flops DA
D Q A
• output is function of inputs + current state
inputs >C
describe it using x y z
• external inputs to combinational part • truth table, boolean functions or logic diagram
• outputs of flip flops – for combinational part (truth table, boolean function, logic diagram)
DB D Q B
– e.g., A >C – inputs are external inputs plus flop-flop outputs u = g(a,b,c,d,e,f)
outputs – outputs are external outputs plus flip-flop inputs v = h(a,b,c,d,e,f)
– one boolean function for each output in terms of all inputs w= i(a,b,c,d,e,f)
• external outputs x = j(a,b,c,d,e,f)
• outputs of flip flops • finite state machine y = k(a,b,c,d,e,f)
– for sequential part z = l(a,b,c,d,e,f)
flip flops – finite state machine
• inputs to flip flops – lists all possible states (memory settings)
– e.g., DA – describes how current input and state determine external output and next state

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Understanding them Designing a sequential circuit

DA x=0
determine flip-flop input equations D Q A example: a two-bit counter
>C 00
• DA = (A+B)´
1. draw a state diagram x=0
x=1 x=1
• DB = A
2. draw excitation table 01 11 x=0
create state table DB D
>C
Q B • left hand columns x=1 x=1
Q(t) Q(t+1) – all combinations of current state + input => next state 10
A B A B • right hand columns x=0
0 0 1 0 – one flip flop for each state variable (e.g., A,B)
0 1 0 0
– column for each flip-flop input, from excitation table
1 0 0 1 Q(t) in Q(t+1) flip-flop inputs
1 1 0 1 A B x A B JA KA JB KB Q(t) Q(t+1) J K
0 0 0 0 0 0 x 0 x 0 0 0 x
draw state diagram 0 0 1 0 1 0 x 1 x 0 1 1 x
0 1 0 0 1 0 x x 0 1 0 x 1
00 10 0 1 1 1 0 1 x x 1 1 1 x 0
edges may be lablled a/b
•!meaning that input a causes transition 1 0 0 1 0 x 0 0 x
•!and output b is the result 1 0 1 1 1 x 0 1 x
01 11 1 1 0 1 1 x 0 x 0
15 1 1 1 0 0 x 1 x 1 16
Designing a sequential circuit (II)
Q(t) in Q(t+1) flip-flop inputs
3. get boolean functions A B x A B JA KA JB KB
• for 0 0 0 0 0 0 x 0 x
– flip-flop inputs and external outputs 0 0 1 0 1 0 x 1 x
0 1 0 0 1 0 x x 0
• in terms of 0 1 1 1 0 1 x x 1
– flip-flop outputs and external inputs 1 0 0 1 0 x 0 0 x
• using k-maps 1 0 1 1 1 x 0 1 x
1 1 0 1 1 x 0 x 0
Bx JA Bx JB 1 1 1 0 0 x 1 x 1
A 00 01 11 10 A 00 01 11 10
0 0 0 1 0 0 0 1 x x
1 x x x x 1 0 1 x x
JA = Bx JB = x x J Q A
Bx KA Bx KB >C
A 00 01 11 10 A 00 01 11 10 K
0 x x x x 0 x x 1 0
1 0 0 1 0 1 x x 1 0 J Q B
KA = Bx KB = x clock >C
K
4. draw logic diagram
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