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IO Ring Design PDF

The document discusses the design of input/output (IO) rings in integrated circuits. It describes how IO rings contain pad cells for interfacing circuitry on and off the chip, as well as power buses and electrostatic discharge protection structures. It outlines different types of pad cells for power, input, output, bidirectional and analog signals. The document also covers IO ring design flow, floorplanning considerations, interface standards, assembly stress relief rules, and provides examples of pad cell and IO ring layouts.

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Sure Avinash
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934 views20 pages

IO Ring Design PDF

The document discusses the design of input/output (IO) rings in integrated circuits. It describes how IO rings contain pad cells for interfacing circuitry on and off the chip, as well as power buses and electrostatic discharge protection structures. It outlines different types of pad cells for power, input, output, bidirectional and analog signals. The document also covers IO ring design flow, floorplanning considerations, interface standards, assembly stress relief rules, and provides examples of pad cell and IO ring layouts.

Uploaded by

Sure Avinash
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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IO

 RING  DESIGN    
29  Oct  2018  
Introduc0on  
IO  Ring  (Pad  Ring  or  Pad  Frame)  forms  the  periphery  or  
circumference  of  a  chip  
Contains  pad  cells,  wide  power  buses,  ESD  structures,  
assembly  stress  relief  structures,  logo,  part  numbers  etc  
Pad  Cells  
Why  need  Pad  cells  or  what  is  special  about  those  cells  
²   Circuitry  on  a  chip  has  to  interface  to  circuitry  off  chip  
²   Need  special  type  of  buffers;  core  buffers  won’t  do  the  job  
²   Has  to  drive  large  capacitance  off  chip  (few  pico  Farads)  
²   Need  to  operate  at  compa0ble  voltage  levels  (TTL  etc)  
²   Need  protec0on  against  Latch-­‐up  (Guard  rings)  
²   Need  protec0on  against  electrosta0c  discharge  (ESD)  
²   Slew  rate  controls  to  limit  the  di/dt  noise  
²   Dedicated  power  supply  to  avoid  introducing  noise  in  core  supply  
²   Wide  power  busses  to  supply  to  core  area  as  well  
²   Wide  metal  area  called  bond  pad  to  connect  to  package  pin  
²   Compliance  to  assembly  stress  relief  rules  
Types  of  Pad  Cells  
Different  types  of  pad  cells  are  needed  
²   Pad  cells  for  VDD/GND  

²   Input  Pads  


²   Output  Pads  
²   I/O  Pads    (Bidirec0onal  Pads)  
²   Analog  pads  
Input  Pads  
Output  Pads  

Guard  rings  for  latchup  protec0on  


²   large  N  transistors  
²   P+  inner  guard  ring  
²   N+  outer  guard  ring  in  N-­‐well  
Bidirec0onal  Pad  (I/O  Pad)  
Bidirec0onal  pad  is  a  tristate  inver0ng  output  pad  +  input  pad    

ESD  protec0on  not  shown  

Series  transistor  avoided  


Simple  Implementa0on  
Increased  drive  strength  
Analog  Pads  
Pass  analog  voltages  directly  in  or  out  of  chip    
²   No  buffering  

²   Protec0on  circuits  must  not  distort  voltages  


Design  Flow  
IO  ring  design  involves  following  steps;  
Genera0ng  the  structural  Verilog  code  of  the  IO  ring  –  instan0ate  all  
relevant  func0onal  cells  and  connect  appropriately  
²   Iden0fying  appropriate  padcells  for  each  of  the  interfaces  i.e  pad  
type  and  drive  strength  based  on  load  and  package  parasi0c,  etc  
²   Number  of  power  pads  for  core  and  various  interfaces  based  on  IR  
drop  limits,  package  parasi0c  and  recommended  signal  to  power  
pad  ra0o  
²   Stand  alone  ESD  cells  if  ESD  structures  in  the  padcells  are  not  
enough,  based  on  ESD  plan  ;    
²   Any  other  hard  macro  if  relevant  
²   So\  macros  are  not  included  in  the  IO  ring  
IO  Ring  Floorplanning  
² Placement  of  the  padcells  based  on  package  requirement  i.e  
which  signal  pin  on  which  part  of  the  package  
²   Hard  macros  based  on  padcell  and  core  connec0vity  
² Wide  and  short  padcell  (if  op0on  exists)  for  core  limited  die  
² Thin  and  tall  pad  cell  (if  op0on  exists)  for  pad  limited  die  
² Staggered  bonding  for  pad  limited  die  
² Double  bonding  for  VDD/VSS  to  reduce  wire  resistance  
²   U0lize  le\  over  space  for  non  func0onal  cells  like  logo,  part  
number,  etc  
²   Take  into  account  assembly  stress  relief  rules,  pins  with  
high  parasi0c,  etc  
Need  to  perform  spice  analysis  with  package  parasi0c  to  ensure  
simultaneous  switching  noise  is  within  limits  
IO  Standards  
Variety  of  standards  exist  
²   Single  ended  vs  Differen0al  

²   TTL  and  LVTTL  


²   CMOS  and  LVCMOS  
²   LVPECL,  LVDS,  HSTL,  SSTL,  etc  
Interface  Standards  
Interface  Standards  
Sample  IO  Ring  Layout  
Assembly  Stress  Relief  Rules  
Being  the  periphery  of  the  chip,  IO  ring  regions  are  
more  vulnerable  to  mechanical  stress  and  strain.      
Need  to  follow  assembly  stress  relief  rules  to  avoid  
cracking  of  the  chips  
Typical  rules  are  
²   Dead  zone  –  No  circuitry  allowed  in  this  region  

²   Cri0cal  Corner  Area  –  Slobng  and  Rive0ng  of  metals  


and  450  bend  for  metals  –  900  not  allowed  
² Cri0cal  Side  Area  -­‐  450  bend  for  metals  –  900  not  
allowed  
Assembly  Stress  Relief  Rules  
Bond  Pad  Layout  (2  Metal  Process)  
References  
•  hep://users.ecs.soton.ac.uk/bim/notes/vlsi/lecture/
pdf/vlsi05.pdf  
•  hep://www2.eng.cam.ac.uk/~dmh/4b7/resource/
sec0on14.htm  

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