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Novel design of a fast reversible Wallace sign multiplier circuit in

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DOI: 10.1016/j.mejo.2011.05.007 · Source: DBLP

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 Microelectronics Journal 42 (2011) 973–981

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Novel design of a fast reversible Wallace sign multiplier circuit

in nanotechnology
Ehsan Pour Ali Akbar a, Majid Haghparast b,n, Keivan Navi c
a
Department of Computer Engineering, Dezful Branch, Islamic Azad University, Dezful, Iran
b
Department of Computer Engineering, Shahre-Rey Branch, Islamic Azad University, Tehran, Iran
c
Faculty of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran

a r t i c l e i n f o abstract

Article history: Today, reversible logic is emerging as an intensely studied research topic, having applications in diverse
Received 21 January 2011 fields, such as low-power design, optical information processing, and quantum computation. In this
Received in revised form paper, we have proposed two reversible Wallace signed multiplier circuits through modified Baugh–
30 May 2011
Wooley approach, which are much better than the two available counterparts in all the terms. The
Accepted 31 May 2011
multiplier is an essential building block for the construction of computational units of quantum
Available online 24 June 2011
computers. Besides, we need signed multiplier circuits for numerous operations. However, only two
Keywords: reversible signed multiplier circuits have been presented so far. In the first proposed architecture, our
Reversible logic goals are to decrease the depth of the circuit and to increase the speed of the circuit. In the second
ZS series gates
proposed circuit, we aimed to improve the quantum cost, garbage outputs, and other parameters. All
Reversible array multiplier
the proposed circuits are in the nanometric scales and can be used in the design of very complex
Wallace sign multiplier
systems.
& 2011 Elsevier Ltd. All rights reserved.

1. Introduction in the low-power CMOS circuits, bioinformatics, optical information

processing, quantum computing, thermodynamic technology, DNA
One of the problems in the conventional irreversible circuits is computations, and nanotechnology. Designing the quantum circuits
the wastage of large amount of internal energy. A main goal in the needs reversible logic gates. The reversible logic circuit structures
VLSI circuit design is to minimize the energy wastage. Landauer are much more complex than the irreversible logic circuits, because
[1] proved that irreversible hardware calculations cause a lot of feedback and Fan-out are not allowed [3]. The quality of a reversible
internal energy wastage. According to Landauer’s principle, circuit is identified by some criteria as follows.
losing one information bit dissipates KTln2 Joules of energy, The number of used gates (NOG), the number of constant
where K¼ 1.3806505  10  23 m2 kg  2 k  1(joules Kelvin  1) is the inputs (Gin), the number of garbage outputs (Gout), total quan-
Boltzmann’s constant and T is the absolute temperature in which tum costs (QC), circuit delay, and the total logical calculations
the operation takes place. In the reversible logic circuits, the internal (circuit cost) [4].
power consumption is equal to zero, because these reversible The inputs that are added to an N  K function to make it
circuits do not have internal energy wastage. Bennett proved that reversible are called constant inputs [7]. They are also known as
the reversible circuits would not lose KTln2 joules of energy [2] Don’t Care inputs (DC inputs). The garbage outputs are outputs that
because they do not lose data. A circuit is reversible if there is a one- are not used for further computations [5]. They are also known as
to-one correspondence between its input and output assignments, Don’t Care outputs (DC outputs). Each reversible logic gate has a
i.e. not only the outputs can be uniquely determined from the specific QC. QC of a circuit is equal to the total QCs of its reversible
inputs, but also the inputs can be recovered from the outputs [3–5]. gates. The delay in a circuit is the maximum number of gates
Therefore, in the reversible circuits, the number of inputs and between its inputs to outputs paths. Total logical calculation is the
outputs should be equal to connect the inputs and the outputs in count of the XOR (a), AND (b), and NOT (d) in the output expressions.
a one-to-one manner [3,4,6]. In the recent years, reversible logic was In designing a reversible circuit, the above-mentioned criteria is
added to the circuits’ technology, and it boomed due to its property tried to improve. Thus, in designing the new circuits, it is attempted
of no internal energy wastage. The reversible logic has applications to minimize the number of constant inputs, garbage outputs, circuit’s
delay, QC of circuits, and total logical calculations.
In the computational units, the multipliers are one of the most
n
Corresponding author. useful operations. Besides, numerous of these operations take
E-mail address: [email protected] (M. Haghparast). place on the signed digits. Therefore, developing a signed

0026-2692/$ - see front matter & 2011 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2011.05.007
974 E.P.A. Akbar et al. / Microelectronics Journal 42 (2011) 973–981

multiplier circuit is necessary. However, just two reversible as follows:

signed multiplier circuits have been presented so far. In this
Iv ¼ ðA,BÞ
paper, we have proposed two Wallace reversible signed multiplier
circuits by Feynman gate (FG), Peres gate (PG), Toffoli gate (TG), Ov ¼ ðP ¼ A,Q ¼ A  BÞ
and Haghparast-Navi gate (HNG), and the only differentiation in
these circuits is in producing AND and NAND gates. In the first here, the Iv and Ov are the input and output vectors, respectively.
proposed circuit, we have used not only 25 PG and TG gates, but Fig. 1 shows the FG. The truth table of the FG is depicted in
also FG gate to produce Fan-out to minimize the circuit delay by Table 1.
these gates. In the second proposed circuit, we have employed 25 FG can be used to copy a signal. If we give 0 to the B input of
PG and TG gates and no Fan-out was required. Regarding the this gate (B ¼0), then the two outputs of gate will be equal to A.
delay point of view, the first circuit is found to be better than the This approach can be used for Fan-out production (see Fig. 2).
second one, and with regard to the number of gates, garbage The QC of the FG is equal to 1. Also, the total logical calculation
outputs, constant inputs, logical costs, and QCs, the second of this gate is equal to
proposed circuit is observed to be much better than the first
T ¼ 1a
one. We will prove that our Wallace reversible signed multiplier
circuits have much better functionality than the existing counter- TG, which is also known as Controlled controlled-not (CCNOT),
parts with respect to the number of gates, constant inputs, has three inputs and three outputs. The inputs and outputs of TG
garbage outputs, total logic calculation, QCs, and delay. are as follows:
The rest of the paper is organized as follows: In Section 2, we
have presented the definitions of reversibility and some elemen- Iv ¼ ðA,B,CÞ
tary reversible logic gates. Then, we have provided some litera- Ov ¼ ðP ¼ A,Q ¼ B,R ¼ AB  CÞ
ture survey on the existing reversible signed and unsigned
multipliers. Our proposed fast reversible Wallace sign multiplier here, Iv and Ov are the input and output vectors, respectively.
circuits have been introduced in Section 3. Furthermore, we have Fig. 3 indicates the TG, and the truth table of TG is depicted in
analyzed and evaluated the proposed reversible signed multiplier Table 2.
circuits in Section 4. The conclusion has been given in Section 5, TG can be used to produce AND for two signals. If we give 0 to
and a comprehensive list of references has also been provided. the C of this gate, the third output (R) will be the AND of the first
and second inputs. This operation is shown in Fig. 4.
TG can be used as a two-input AND gate. Also, if we give 1 to
2. Basic concepts the third input of this gate (C ¼1), in its third output (R), NAND
result of the first and second input will be produced. This
2.1. Reversible logic operation is shown in Fig. 5.

A circuit (gate) is reversible if there is a one-to-one correspon-

dence between its input vector (Iv) and output vector (Ov). In the
reversible circuits (gates), not only the outputs can be uniquely
determined from the inputs, but also the inputs can be recovered
from the outputs. Thus, they are N  N circuits (gates):
Fig. 1. Reversible Feynman gate [8].
Iv ¼ ðI1,I2,I3,. . .,InÞ
Ov ¼ ðO1,O2,O3,. . .,OnÞ

The garbage outputs are outputs of a gate that would not be Table 1
Truth table of the reversible Feynman gate.
used in the next computation procedures. In a circuit, the outputs
that are never used are called garbage outputs. The constant A B P Q
inputs are inputs that are added to the N  K functions to make
them reversible. 0 0 0 0
Quantum circuits are also reversible because closed quantum 0 1 0 1
1 0 1 1
mechanical systems are inherently reversible. The QC is another 1 1 1 0
criterion of the reversible logic gates. The 1  1 gates have no QC.
The QC of the 2  2 gates is 1. However, bigger gates, such as 3  3
gates, cannot be directly realized in quantum technology. There-
fore, we use the 1  1 and 2  2 gates to implement the bigger
ones. The QC of a reversible or quantum circuit is defined as the A P=A
number of 1  1 or 2  2 gates used to implement the circuit [23]. FG
0 Q=A
The total logical calculation is another criterion of the rever-
sible logical circuits, which indicates the XORs, ANDs, and NOTs.
The a indicates the number of XORs and b is equal to the number Fig. 2. Copy of a signal by Feynman gate.
of ANDs of the circuit. The number of NOTs of the circuit is shown
by d. The total logical calculation is equal to the total of a, b,
and d.
Several reversible logical gates have been presented so far, A P=A
which can be used for designing the reversible circuits. In this B TG Q=B
paper, four reversible gates have been used and we will analyze
C R = AB ⊕ C
them. These four gates are FG [8], TG [9], PG [10], and HNG [11].
FG, which is also known as the controlled-not gate (1-CNOT),
has two inputs and two outputs. The inputs and outputs of FG are Fig. 3. Reversible Toffoli gate [9].
 E.P.A. Akbar et al. / Microelectronics Journal 42 (2011) 973–981 975

Table 2
Truth table of the reversible Toffoli gate. A P=A

A B C P Q R B PG Q= A ⊕ B
0 R=AB
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
Fig. 7. Producing Half Adder (HA) and AND operation by Peres gate.
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 1
1 1 1 1 1 0 A P=A
B PG Q= A⊕B
1 R = AB

P=A
Fig. 8. Producing NAND operation by Peres gate.
Q=B

R=AB

Fig. 4. Producing AND operation by Toffoli gate.

A P=A
Fig. 9. Reversible HNG gate [11].
B TG Q=B

1 R = AB If we give 0 to the third input of PG (C¼0), in its third output

(R), AND result of the first and second inputs will be produced.
Fig. 5. Producing NAND operation by Toffoli gate.
This operation is shown in Fig. 7.
PG can be used as a two-input AND gate. The third output of
the gate will create AND result. Furthermore, this gate can be
used as a Half Adder (HA), so that, its sum will be acquired
through the second output and its Carry through the third output
of the gate.
Also, if we give 1 to the third input of this gate (C¼ 1), in its
third output (R), NAND result of the first and second inputs will be
produced. This operation is shown in Fig. 8.
Fig. 6. Reversible Peres gate [10]. The QC of the PG is equal to 4, and its total logical calculation is
as follows:
T ¼ 2a þ 1b
Table 3
Truth table of the reversible Peres gate. The reversible HNG gate has four inputs and four outputs,
given as follows:
A B C P Q R
Iv ¼ ðA,B,C,DÞ
0 0 0 0 0 0 Ov ¼ ðP ¼ A,Q ¼ B,R ¼ A  B  C,S ¼ ðA  BÞC  AB  DÞ
0 0 1 0 0 1
0 1 0 0 1 0 here, Iv and Ov are the input and output vectors, respectively.
0 1 1 0 1 1 Fig. 9 indicates the HNG, and the HNG truth table is shown in
1 0 0 1 1 0
1 0 1 1 1 1
Table 4.
1 1 0 1 0 1 HNG gate can be used as FA. If we give 0 to the D input of this
1 1 1 1 0 0 gate, its third output (R) will be the sum of FA function, and the
fourth output of this gate (S) will be its Carry results. This
operation is shown in Fig. 10.
The QC of TG is equal to 5, and the total logical calculation of This gate will be used as a Full Adder (FA) provided that its
TG is as follows: third input is as Cin and the fourth input is equal to 0. The third
T ¼ 1a þ 1b output creates the sum and the fourth output creates the Carry.
The QC of the reversible HNG is equal to 6, and its total logical
PG, which is also known as New Toffoli Gate (NTG) has three calculation is as follows:
inputs and three outputs. The inputs and outputs of the PG are as
T ¼ 5a þ 2b
follows:
Iv ¼ ðA,B,CÞ Till date, some reversible logic gates to be used as FA have
been presented. Among those gates, HNG is the best choice with
Ov ¼ ðP ¼ A,Q ¼ A  B,R ¼ AB  CÞ
respect to the total logical calculation of this gate, when com-
Here, Iv and Ov are the input and output vectors, respectively. pared with the other gates, and hence, its use as FA is better. Also,
Fig. 6 indicates the PG, and the truth table of PG is shown in this gate has the least QC, when compared with the other gates
Table 3. We can create a PG by combining TG with FG. used as FA.
976 E.P.A. Akbar et al. / Microelectronics Journal 42 (2011) 973–981

Table 4 2.4. Existing reversible signed multiplier

Truth table of the reversible HNG gate [11].
Many reversible unsigned multiplier circuits have been
A B C D P Q R S
designed so far. In addition, a 4  4 reversible signed multiplier
0 0 0 0 0 0 0 0 circuit was presented by Thapliyal and Srinivas [28] for the first
0 0 0 1 0 0 0 1 time in 2005. They designed this multiplier by a given MFA gate.
0 0 1 0 0 0 1 0 In 2010, Zhou et al. [32] designed another reversible signed
0 0 1 1 0 0 1 1
0 1 0 0 0 1 1 0
multiplier circuit. They designed a 5  5 reversible and signed
0 1 0 1 0 1 1 1 multiplier by introducing new gates of Zs series as adder in signed
0 1 1 0 0 1 0 1 number.
0 1 1 1 0 1 0 0 Furthermore, we realized that the formula 12 is wrong in [32].
1 0 0 0 1 0 1 0
In formula 12, the first output of ZS3 gate has been used to
1 0 0 1 1 0 1 1
1 0 1 0 1 0 0 1 produce Carry for two negative bits and a positive bit. Therefore,
1 0 1 1 1 0 0 0 the result would not be the Carry with these three bits, but was
1 1 0 0 1 1 0 1 mistaken for the Carry. The ZS3 gate can never be used as a signed
1 1 0 1 1 1 0 0 FA with two negative bits and a positive one. For example, if we
1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 0
give ‘‘101’’ to ‘‘abc’’ (a ¼1, b¼0, c ¼1), then the Carry must be
1 and sum must be 0.
Yet, if we put the mentioned input amounts in formula 12 of
[32], then the result of the beginning of the formula will be as
follows:

Ci þ 1 ¼ A0 B0 þ ðA0  B0 ÞC ¼ A0 B0  ðA0  B0 ÞC ¼ 0:1  ð0  1Þ1 ¼ 0

However, in formula 12 of [32], this result has been considered

as equal to the Carry. Here, we will show that these amounts are
Fig. 10. Reversible HNG gate as a reversible Full Adder (FA) [11].
not equal:
Ci þ 1 ¼ AB  BC  AC ¼ AB  ðA  BÞC ¼ 1:0  ð1  0Þ1 ¼ 1

These results show that the results at the beginning and the
2.2. Existing reversible unsigned multiplier end of formula 12 are not equal. Furthermore, it is impossible to
obtain the Carry result through ZS3 gate.
Multiplier circuits are divided into two categories: unsigned
and signed. Till date, many interesting studies have been done on
reversible circuits. Some examples of such studies in the field of
3. Our proposed fast reversible Wallace sign multiplier
designing reversible circuits are [12–16] and [17], and different
circuits
articles for designing HA and FA function [5,11,18,19], flip flop
[20–22], and multiplier [23–29] have been published. For exam-
In this paper, we have used the modified Baugh–Wooley
ple, the design of a floating point multiplier has been presented in
approach to compute the product of the signed two numbers.
[29]. In some articles, the design of new gates has been presented,
Here, we have divided the reversible signed multiplier into
such as the design of HNG and MKG by Haghparast et al. in
two parts. First, through two various approaches, we have created
[23,25,26] or TKS gate in [28].
two circuits for partial product generation. Then, through the
Maaz designed a fast and low-power irreversible multiplier
second part of the circuit, we have followed the summation
circuit in 1997 [30], and its reversible circuit was developed by
network.
Thapliyal in 2005 [24]. However, this circuit had high QC, garbage
output, and total logical calculation. In addition, it had several
Fan-outs. Subsequently, other unsigned and reversible multipliers 3.1. First part: Partial product generation circuit
were developed [23,25–27,29]. All these reversible multiplier
circuits have been designed for unsigned numbers. However, To compute the ANDs and NANDs, we need 25 gates to create
with a given new gate, the structure of circuits becomes simpler. 17 ANDs and 8 NANDs. In this paper, we have introduced two
For example, Haghparast et al. [23] designed a reversible multi- approaches to compute the product, which are as follows:
plier circuit using HNG and used it as FA. The first proposed approach: In the first approach, we have
used PG and TG to compute the products, and FG to produce Fan-
out. Fig. 12 indicates the first proposed reversible partial product
2.3. Existing irreversible signed multiplier generation circuit.
In the first proposed circuit to compute the product, we have
So far, several approaches have been presented to multiply the tried to use the PG as much as possible and employ less of the TG,
signed numbers, such as 2’s complement, Baugh–Wooley, and because the QC of the PG is less than that of TG. Besides, to
modified Baugh–Wooley methods. These methods act on maximize the circuit speed, the FG has been used. Adding the FG
unsigned numbers. In 1973, Baugh and Wooley [31], worked on gates to the circuit caused to make the circuit end gates outputs
the present Baugh–Wooley method. Subsequently, the modified to be ready earlier.
form of this method was developed. In the modified Baugh– As shown in Fig. 12, we divided the partial product generation
Wooley method, the number quantity is considered as 2’s circuit into four parts. These four parts communicate with each
complement. Fig. 11 indicates how the multiplication operation other with the help of FG. In each part, the entrance of the TG or
takes place in this approach. PG is obtained with the help of the outgoing FG or TG and PG of
Fig. 11 shows that we need 17 AND gates and 8 NAND gates to that part. This shows that these parts need not wait to receive the
produce a signed multiplier. entrance of the other parts. On the other hand, all the four parts
 E.P.A. Akbar et al. / Microelectronics Journal 42 (2011) 973–981 977

X4 X3 X2 X1 X0
Y4 Y3 Y2 Y1 Y0
X 4 Y0 X3Y0 X2y0 X1Y0 X0y0
X 4 Y1 X3Y1 X2Y1 X1Y1 X0Y1
X 4Y2 X3Y2 X2Y2 X1Y2 X0Y2
X 4 Y3 X3Y3 X2Y3 X1Y3 X0Y3
X4Y4 X 3Y4 X 2Y4 X1Y4 X 0Y4
1
1
P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Fig. 11. Signed multiplier 5  5 by Modified Baugh–Wooley.

Fig. 12. Proposed reversible partial product generation circuit, first approach.

act in parallel, and the whole delay of the circuit is equal to the obtain x0 y4 function, x0 entrance should cross from 5 press gates
maximum delay. to create this function. This occurrence happens for y4 entrance.
The number of the garbage outputs in this circuit is 20 and its These consequences show that the delay in the circuit shown in
constant inputs are 35. The advantage of this circuit, when Fig. 12 for parallel entrances is less than the circuit presented in
compared with the second proposed circuit, is its higher speed. Fig. 13.
The second proposed approach: This approach uses the PG The number of garbage outputs in this circuit is 10 and the
and TG in partial product generation circuit. constant inputs are 25. The advantage of this circuit, when
Fig. 13 indicates the second proposed reversible partial pro- compared with the first proposed circuit, is its less constant
duct generation circuit. inputs, garbage outputs, logical costs, and QC.
In the second proposed circuit, to generate the partial pro- In the design of the signed multiplier circuit, if the circuit
ducts, we tried to use less number of gates, garbage outputs, and speed is given higher priority than the other criteria, then it is
constant inputs. Besides, PG were used to produce AND and better to use the first proposed circuit to compute the partial
NAND as much as possible to minimize the QC of the circuit. products; however, if the QC, number of garbage outputs, number
In Fig. 13, in contrast to Fig. 12, the circuit has unified of constant inputs, and logical cost have higher priority than
structure. This means that each gate should retrieve its entrance the circuit delay, then it is better to use the second proposed
from the outgoing gate of the previous step. For example, to approach to compute the partial products. Later, we will prove
978 E.P.A. Akbar et al. / Microelectronics Journal 42 (2011) 973–981

Fig. 13. Second proposed circuit to produce AND and NAND gates by Toffoli and Peres gates.

that both our proposed circuits work better than the circuit
presented in [32].

3.2. The second part: Acquiring the sum of products using Wallace
tree method in the reversible signed multiplier

To compute the partial products of two signed number with

the aid of reversible gates, we should employ the procedure given
in Fig. 11. After acquiring ANDs and NANDs, we should sum up
the bits of each column given in Fig. 11. To sum up these bits, we
need FA and HA. We have to try to sum up these bits in a way that 1 1
our circuit will give the best results from the quantum and logical
costs and the number of garbage outputs and constant inputs. 1
Fig. 14 shows the way of acquiring the sum up in our proposed
circuit. The Wallace approach has been used to acquire a circuit
with less delay.
As shown in Fig. 14, after acquiring the products, we should
sum them up. To sum up the bits in each column, we need the HA
and FA gates. In our proposed circuit, the PG shown in Fig. 7 has 1
been used as HA, and the HNG presented in Fig. 10 has been
employed as FA.
In our proposed circuit, according to Fig. 14, to compute P9, we
need a HA that can only use the sum and dispose the Carry.
1
Therefore, to compute P9, an FG is sufficient to mark the
computed carry NOT (from the pre-last column) and enter it as
P9. Besides, if we put 1 instead of 0 as the HNG’s fourth input in
P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
the pre-last column, then the sum of that gate would not change
and the Carry becomes NOT and can be used as P9. As a result, one Fig. 14. To compute the product of two digits in Wallace approach in the proposed
gate is minimized from the circuit, and thus, the circuit delay will circuit.
 E.P.A. Akbar et al. / Microelectronics Journal 42 (2011) 973–981 979

Fig. 15. Our proposed Wallace reversible signed multiplier circuit using Haghparast-Navi and Peres gates.

Table 5
Comparative results of partial product generation circuits of different reversible signed multipliers.

No. of gates No. of garbage outputs No. of constant inputs Total logical calculation Quantum cost Delay

First proposed method (Fig. 12) 25þ 10 20 25 þ10 51a þ 25b 119 4
Second proposed method (Fig. 13) 25 10 25 34a þ 25b 116 5
[32] 25þ 20 30 25 þ20 45a þ 25b 145 5

be minimized for one gate. Fig. 15 demonstrates our proposed difference between our first and second approaches can be found
reversible signed multiplier. in their first part, while there are no differences in their summa-
In Fig. 14, one HA and five FA have been used to calculate the tion networks.
sum of the columns in the first step. Thus, in Fig. 15, in first step, The reversible signed multiplier circuits are acquired through
the same entrance quantity has been added with the help of one the sum of the first and second parts of the circuits. Table 7 shows
PG and five HNG. Similarly, in Fig. 14, for the second step, add the sum of Table 5 and 6, clearly demonstrating that our proposed
operation has been carried out with the help of one HA and four circuit works much better than that presented in [32].
FA. We have shown this operation in Fig. 15 for entrances, and The difference between the first and the second proposed
have continued until all the quantities of P0–P9 have been circuit to compute the partial products is that we used FG in the
calculated. first circuit to produce Fan-out, because it maximizes the circuit
The circuit proposed in Fig. 15 needs 4 PG and 16 HNG. speed. Yet, increasing the FG maximizes the QCs, logical cost,
garbage outputs, and constant inputs, when compared with the
second proposed circuit. Besides, in the first proposed circuit, 16
4. Evaluation of the proposed reversible signed multiplier PG have been used and in the second proposed circuit, only 9 PG
circuits have been employed. Although owing to the FG in the first
proposed circuit, the QC is increased, due to the huge number
Both the proposed circuits of this study have a better quality of PG (when compared with the second proposed circuit), a
than the reversible signed multiplier circuit presented in [32]. balance of the QC is achieved, because it is well known that the
Table 5 and 6 show the quality of our proposed circuits, when QC of the PG is lower than that of TG.
compared with the existing reversible circuit presented in [32]. From Table 7, it is obvious that the gates used in our proposed
Furthermore, in Table 6, the results of [28] have been eval- circuits are less than those employed in the existing counterpart
uated. However, it must be noted that the circuit presented in presented in [32]. Also, our first proposed circuit has used 10 FG
[28] is a 4  4 reversible signed multiplier, but those proposed by more than our second proposed circuit. The number of used gates
us and that given in [32] are 5  5 circuits. in our first proposed circuit is 55, while that in our second
Table 5 shows the comparison between the reversible partial proposed circuit and in the circuit presented in [32] is 45 and
product generation circuits of the proposed designs and the 65, respectively.
existing design given in [32]. Table 6 demonstrates the compar- One of the most important criteria in analyzing reversible
ison between the summation network of our proposed circuit and circuits is their garbage outputs. Our first and second proposed
the existing counterpart presented in [32]. In our paper, the circuits have 56 and 46 garbage outputs, respectively. However,
980 E.P.A. Akbar et al. / Microelectronics Journal 42 (2011) 973–981

Table 6
Comparative results of summation networks of different reversible signed multiplier circuits.

No. of gates No. of garbage outputs No. of constant inputs Total logical calculation Quantum cost Delay

The proposed method (Fig. 14) (5  5) 20 36 21 88a þ 36b þ 0d 112 8

[32] (5  5) 20 40 25 160a þ 80b þ 61d Not known 8
[28] (4  4)a 13 39 18 Not known Not known 7

a
It must be noted that the circuit in [28] is a 4  4 reversible circuit.

Table 7
Comparative results of different reversible signed multiplier circuits.

No. of gates No. of garbage outputs No. of constant inputs Total logical calculation Quantum cost Delay

First proposed method 55 56 56 139a þ 61b þ0d 231 12

Second proposed method 45 46 46 122a þ 61b þ0d 228 13
[32] 65 70 70 205a þ 105b þ 61d Not known 13

the number of garbage outputs of the circuit presented in [32] is outputs (partial product generation), and in the second part, we
70, and thus, our proposed circuits have a better quality than that have computed the sum of the products (summation network). In
given in [32] in terms of the number of garbage outputs. both the proposed circuits, to produce AND and NAND gates, TG
Furthermore, our second proposed circuit is better than our first and PG have been used. In the first proposed circuit, we have used
proposed circuit in this criterion. FG to produce Fan-out. Furthermore, in the second proposed
Another criterion for reviewing the circuits’ quality is their circuit, we also tried to minimize the circuit garbage outputs as
constant inputs. It is clear from Table 7 that the number of much as possible. The summation network has been designed
constant inputs in our first and second proposed circuits is 56 and using the HNG and PG. Table 7 demonstrates that our proposed
46, respectively. However, the number of constant inputs in the reversible signed multiplier circuits have a better quality than the
circuit presented in [32] is 70. This shows that our proposed circuit presented in [32] in terms of QC, total logical calculation,
circuits have a better quality than the circuit given in [32] in number of gates, number of garbage outputs, number of constant
terms of the number of constant inputs. inputs, and delay. The circuits presented in this paper could be
Another criterion to analyze the quality of the reversible useful to design the complex systems in nanotechnology, because
circuits is their total logical calculation. According to Table 7, all the reversible circuits are in nanometric scales.
the total logical calculation in the first and second proposed
circuit is 139a þ61b and 122a þ61b, respectively. However, the
total logical calculation of the circuit presented in [32] is
205a þ105b þ61d. This shows that the first proposed circuit is References
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