ADIGRAT UNIVERSITY

COLLEGE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRICAL AND COMPUTER
ENGINEERING
COURSE TITLE MICROCOMPUTER AND INTERFACING

COURSE CODE

ASSIGNMENT 1

SECTION ONE

NETWORK FIVE

NO GROUP MEMBERS ID NO
1 MEKONEN HAILE RET/01839/08
2 TESFAYE TEKLU RET/05415/08
3 HELEN HAILE RET/01516/08
4 URGESSA FEYISSA RET/02437/08
5 NATNAEL AMBAW RET /0 /08

SUBMITTED TO INST. MEHARI.G (ASS.PROF)

SUBMISSION DATE 23/05/2011 E.C

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 Table of Contents

CONTENT……………………………………………………………………………………………………………………..PAGE NO
AKNOWLEDGMENTS……………………………….…………………………………………………………………………………1

CHAPTER 1 INSTRUCTION SET OF 80386 MICROPROCESSOR ........................................................ 2

1.1 INTRODUCTION ..................................................................................................................... 2
1.2 Instruction set of 80386 microprocessor .............................................................................. 2
1.2.1 Arithmetic Instructions ................................................................................................... 3
1.2.2 Data transfer instructions ............................................................................................. 4
1.2.3 Flag Control Instructions................................................................................................ 5
1.2.4 Logical Instructions ........................................................................................................ 5
1.2.5 String Instructions ........................................................................................................ 6
1.2.6 Set Byte on Condition Instructions ............................................................................... 7
1.3 80386 Technology…………………………………………………………………………………………………………..7
1.4 Working principle of 80386 microprocessor ......................................................................... 7

SUMMERY……………………………………………………………………………………….9

REFFERENCE…………………………………………………………………………….......10

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 AKNOWLEDGMENTS
This ASSIGNMENT would not have been possible
without all of my friends, and coworkers encouraging us,
helping us, and supporting us.
WE wish to thank the LORD God, for “with man this is
impossible, but with God all things are possible.”
To our coworkers, friends, we could not have done this
without them and we thank them for making this
experience enjoyable.
Finally, we wish to acknowledge instructor MEHARI.G
(ASS.PROF) for providing us this assignment because this
make us know all about the INSTRUCTION SET OF 80386
MICROPROCESSOR.

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 CHAPTER 1

INSTRUCTION SET OF 80386 MICROPROCESSOR

1.1 INTRODUCTION
 The 80386 includes 32-bit extended register and a 32-bit address
and data bus
 The 80386 has a physical memory size of 4GBytes that can be
addressed as a virtual memory with up to 64TBytes
 The 80386 is operated in the pipelined mode, it sends the address of
the next instruction or memory data to the memory system prior to
completing the execution of the current instruction
 This allows the memory system to begin fetching the next
instruction or data before the current is completed
 This increases access time, thus reducing the speed of the
memory
 The instruction set of the 80386 is enhanced to include instructions
that address the 32-bit extended register set.
 Interrupts, in the 80386 microprocessor, have been expanded to
include additional predefined interrupts in the interrupt vector table
 The 80386 is also capable of paging
 In the protected mode, 80386 addresses any location in its 4G bytes
of physical address space.

1.2 Instruction set of 80386 microprocessor

The 80386 can execute all 16-bit instructions in real and protected
modes. This is provided in order to make the 80386 software
compatible with the 8086. The 80386 uses either 8- or 32-bit

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 displacements and any register as the base or index register while
executing 32-bit code. However, the 80386 uses either 8- or 16-bit
displacements with the base and index registers while executing 16-
bit code. The base and index registers utilized by the 80386 for 16-
and 32-bit addresses are as follows:
16-bit 32-bit addressing
addressing
Base register BX,BP Any 32-bit general purpose
register
Index register SI,DI Any 32-bit general purpose
register except ESP
Scale factor None 1,2,4,8
displacement 0,8,16 bits 0,8,32 bits

1.2.1 Arithmetic Instructions

There are two new sign extension instructions beyond those of
the 8086

CWDE Sign-extend 16 bit contents of AX to a 32-bit double word in

EAX.

CDQ Sign-extend a double word (32 bits) in EAX to a quad word (64
bits) in EDX:EAX

The 80386 includes all of the 8086 arithmetic instructions plus some
new ones. Two of the instructions are as follows:

Instruction Operation
ADC reg32/mem32,imm32 [reg32 or mem32]←[reg32 or
mem32]+32-bit immediate data
+CF
ADC reg32/mem32,imm8 [reg32 or mem32] ← [reg32 or
mem32]+8-bit immediate data
sign-extended to 32-bits+CF

Similarly, the other add instructions include the following:

ADC Reg32/mem32, Reg32/mem32

ADD Reg32/mem32, Imm32
ADD Reg32/mem32, Imm8

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ADD Reg32/mem32, Reg32/mem32

The 80386 SUB/SBB instructions have the same operands as the

ADD/ADC instructions.

1.2.2 Data transfer instructions

a. move instructions

the move instructions are described as follows

MOVsx d, s move and sign-extend

MOVzx d, s move and zero-extend

reg16, reg8

reg16, mem8

reg32, reg8

reg32, mem8

reg32, reg16

reg32, mem16

b. Push and Pop Instructions

There are new push and pop instructions in the 80386 beyond those
of the 8086: PUSHAO and POPAO. PUSHAO saves all 32-bit general
registers (the order is EAX, ECX, EDX, EBX, original ESP, EBP, ESI,
and EDI) onto the 80386 stack. . POPAO reverses a previous PUSHAO.

c. Load Pointer Instructions

There are five instructions in the load pointer instruction category:

LOS, LES, LFS, LGS, and LSS. The 80386 can have four versions for
each one of these instructions as follows:

LDS reg16, Mem16:mem16

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LDS Reg32, Mem16:mem32
LDS reg16, Mem16:mem16
LDS Reg32, Mem16:mem32

1.2.3 Flag Control Instructions

There are two new flag control instructions in the 80386 beyond those
of the 8086: PUSHFD and POPFD. PUSHFD decrements the stack
pointer by 4 and saves the 80386 EFLAGS register to the new top of
the stack. No flags are affected. POPFD pops the 32 bits (double
word) from the top of the stack and stores the value in EFLAGS. All
flags except VM and RF are affected.

1.2.4 Logical Instructions

There are new logical instructions in the 80386 beyond those of the
8086:

SHLD d, s, count shift left double

SHRD d, s, count shift right double

d s count

reg16, reg16, imm8

mem16, reg16, imm8

reg16, reg16, CL

mem16, reg16, CL

reg32, reg32, CL

mem32, reg32, imm8

reg32, reg32, CL

mem32, reg32, CL

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SHLD shifts the contents of d:s by the specified shift count with the
result stored back into d; d is shifted to the left by the shift count with
the low-order bits of d filled from the high-order bits of s.

SHRD shifts the contents of d:s by the specified shift count to the
right with the result stored back into d. The bits in dare shifted right
by the shift count, with the high order bits filled from the low-order
bits of s.

1.2.5 String Instructions

a. Compare String Instructions: A new 80386 instruction, CMPS mem32,

mem32 (or CMPSD) beyond the compare string instructions available
with the 8086 compares 32-bit words ES:EDI (second operand) with
DS:ESI and affects the flags.

b. Load and Move String Instructions

There are new load and move instructions in the 80386 beyond those
of 8086. These are LODS mem32 (or LODSD) and MOVS mem32,
mem32 (or MOVSD).

c. Store and Scan String Instructions

There is a new 80386 STOS mem32 (or STOSD) instruction. STOS

stores the contents of the EAX register to a double word addressed
by ES and EDI. ES cannot be overridden. After the storage, EDI is
automatically incremented by 4 if DF = 0 and decremented by 4 if DF =
I. No flags are affected. STOS can be preceded by the REP prefix for a
block fill of ECX double words. There is also a new scan instruction,
the SCAS mem32 (or SCASD) in the 80386.

d. Table Look-Up Translation Instruction

A modified version of the 8086 XLAT instruction is available in the

80386. XLAT mem8 (XLATB) replaces the AL register from the table
index to the table entry. AL should be the unsigned index into a table
addressed by DS:BX for a 16-bit address and by DS:EBX for the 32-bit
address. DS can be overridden.

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1.2.6 Set Byte on Condition Instructions

These instructions set a byte to 1 or reset a byte to 0 depending on

any of the 16 conditions defined by the status flags. The byte may be
located in memory or in a 1-byte general register. These instructions
are very useful in implementing Boolean expressions in high-level
languages. The general structure of these instructions is SET cc (set
byte on condition cc), which sets a byte to 1 if condition cc is true or
else resets the byte to 0.

1.3 80386 Technology

The significance of new 80386 processor lies in the fact that it is

the first IBM type microcomputer processor to have sufficient power
to support multiple users practically.

The operating system used with a computer basic program

required to make the computer able to understand and carry out basic
function. Basic functions are those such as “reading” the key board,
putting information onto the screen, copying files , deleting files ,
printing information, etc….

The most popular operating system currently available for

microcomputer is known as PC-DOS as supplied by IBM or MS-DOS
as supplied by Microsoft ; these are essentially the same product . all
of the popular programs many have heard about such as Dbase, word
perfect etc. run as application program in the MS-DOS environment.

1.4 Working principle of 80386 microprocessor

•The Intenral Architecture of 80386 is divided into 3 sections.
•Central processing unit
•Memory management unit
•Bus interface unit
•Central processing unit is further divided into Execution unit and
Instruction unit
•Execution unit has 8 General purpose and 8 Special purpose registers
which are either used for handling data or calculating offset addresses.

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• The Instruction unit decodes the opcode bytes received from
the 16-byte instruction code queue and arranges them in a
3- instruction decoded instruction queue.
• After decoding them pass it to the control section for deriving
the necessary control signals. The barrel shifter increases the
speed of all shift and rotate operations.
• The multiply / divide logic implements the bit-shift-rotate
algorithms to complete the operations in minimum time.
• Even 32- bit multiplications can be executed within one
microsecond by the multiply / divide logic.

• The Memory management unit consists of a Segmentation unit

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and a Paging unit.
• Segmentation unit allows the use of two address components,
viz. segment and offset for relocability and sharing of code and
data.
• Segmentation unit allows segments of size 4Gbytes at max.
• The Paging unit organizes the physical memory in terms of
pages of 4kbytes size each.
• Paging unit works under the control of the segmentation unit,
i.e. each segment is further divided into pages. The virtual
memory is also organizes in terms of segments and pages by
the memory management unit.

• The Segmentation unit provides a 4 level protection

mechanism for protecting and isolating the system code and
data from those of the application program.
• Paging unit converts linear addresses into physical addresses.
• The control and attribute PLA checks the privileges at the page
level. Each of the pages maintains the paging information of
the task. The limit and attribute PLA checks segment limits
and attributes at segment level to avoid invalid accesses to
code and data in the memory segments.

SUMMERY
 The 80386 includes 32-bit extended register and a 32-bit address
and data bus
 The 80386 has a physical memory size of 4GBytes that can be
addressed as a virtual memory with up to 64TBytes
 Instruction set of 80386 microprocessor
 Arithmetic Instructions
 String Instructions
 Set Byte on Condition Instructions
 Logical Instructions
 Data transfer instructions
 Flag Control Instructions

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 REFERENCES
GOOGLE
 https://pdos.csail.mit.edu
 www.ece.ubc.ca
 https://en.m.wikpedia.org
 https://www.tutorialspoint.com .
 www.logix.cz

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