LSI/CSI

UL
®
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
LS7266R1
(516) 271-0400 FAX (516) 271-0405

24-BIT DUAL-AXIS QUADRATURE COUNTER January 1998

PIN ASSIGNMENT - TOP VIEW
FEATURES: 28-Pin Package
• 30 MHz count frequency in non-quadrature mode,
17MHz in X4 quadrature mode.
YLCNTR/YLOL 1 28 YRCNTR/YABG
• Dual 24-bit counters to support X and Y axes in
motion control applications FCK 2 27 YFLG1

• Dual 24-bit comparators V DD (+5V) 3 26 YFLG2

• Digital filtering of the input quadrature clocks
D0 4 25 YA
• Programmable 8-bit separate filter clock prescalers
for each axis D1 5 24 YB

• Error flags for noise exceeding filter band width D2 6 23 XFLG2

• Programmable Index Input and other programmable I/Os. 7 22

LS726 6R1
D3 XFLG1
• Independent mode programmability for each axis
• Programmable count modes: D4 8 21 XB
Quadrature (X1, X2, X4) / Non-quadrature, D5 9 20 XA
Normal / Modulo-N / Range Limit / Non-Recycle,
D6 10 19 XLCNTR/XLOL
Binary / BCD.
• 8-bit 3-State data I/O bus D7 11 18 XRCNTR/XABG

• 5V operation (VDD-VSS) V SS (GND) 12 17 X/Y

• TTL/CMOS compatible I/Os
C/D 13 16 RD
• 28-Pin SOIC, 28-Pin PDIP (300mil, 600mil)
WR 14 15 CS

LS7266R1 Registers:
LS7266R1 has a set of registers associated with each X and Y axis. All X-axis registers have the name prefix X,
whereas all Y-axis registers have the prefix Y. Selection of a specific register for Read/Write is made from the decode
of the three most significant bits (D7-D5) of the data-bus. CS input enables the IC for Read/Write. C/D input selects
between control and data information for Read/Write. Following is a complete list of LS7266R1 registers.

Preset Registers: XPR and YPR

Each of these PRs are 24-bit wide. 24-bit data can be written into a PR, one byte at a time, in a sequence of three data
write cycles.
PR
7 0 7 0 7 0
HI BYTE MID BYTE LO BYTE
(PR2) (PR1) (PR0)

Counters: XCNTR and YCNTR

Each of these CNTRs are 24-bit synchronous Up/Down counters. The count clocks for each CNTR is derived from its
associated A/B inputs. Each CNTR can be loaded with the content of its associated PR.

Output Latches: XOL and YOL

Each OL is 24-bits wide. In effect, the OLs are the output ports for the CNTRs. Data from each CNTR can be loaded
into its associated OL and then read back on the data-bus, one byte at a time, in a sequence of three data Read
cycles.
OL
7 0 7 0 7 0
HI BYTE MID BYTE LO BYTE
(OL2) (OL1) (OL0)

Byte Pointers: XBP and YBP

The Read and Write operations on an OL or a PR always accesses one byte at a time. The byte that is accessed is
addressed by one of the BPs. At the end of every data Read or Write cycle on an OL or a PR, the associated BP is
automatically incremented to address the next byte.
Flag Register: XFLAG and YFLAG
The FLAG registers hold the status information of the CNTRs and can be read out on the data bus. The E bit of a
FLAG register is set to 1 when the noise pulses at the quadrature inputs are wide enough to be validated by the
input filter circuits. E = 1 indicates excessive noise at the inputs but not a definite count error. Once set, E can
only be reset via the RLD.
FLAG

7 6 5 4 3 2 1 0

BT: Borrow Toggle flip-flop.

Toggles every time CNTR underflows.
CT: Carry toggle flip-flop.
Toggles every time CNTR overflows.

CPT: Compare toggle flip-flop.

Toggles every time PR equals CNTR.
S: Sign flag. Set to1 when CNTR underflows.
Reset to 0 when CNTR overflows.

E: Error flag. Set to 1 when excessive noise is present at the count

inputs in quadrature mode. Irrelevant in non-quadrature mode.
U/D: Up/Down flag. Set to 1 when counting up
and reset to 0 when counting down.

IDX: Index. Set to 1 when selected index input is at active level.

0: Not used. Always reset to 0.

Filter Clock Prescalers: XPSC and YPSC

Each PSC is an 8-bit programmable modulo-N down counter, driven by the FCK clock. The factor N is down load-
ed into a PSC from the associated PR low byte register PR0. The PSCs provide the ability to generate in-
dependent filter clock frequencies for each channel.
Final filter clock frequency fFCKn = ( fFCK/(n+1) ) , where n = PSC = 0 to FFH

Reset and Load Signal Decoders: XRLD and YRLD

Following functions can be performed by writing a control byte into an RLD: Transfer PR to CNTR, Transfer
CNTR to OL, reset CNTR, reset FLAG and reset BP.

RLD
7 6 5 4 3 2 1 0

0: NOP
1: Reset BP
0
: NOP
0
1
: Reset CNTR
0
0
: Reset BT, CT, CPT,S
1
1
: Reset E
1
0
: NOP
0
1
: Transfer PR to CNTR
0 (Note: All 24-bits are transferred in parallel)
0
: Transfer CNTR to OL
1 (Note: All 24-bits are transferred in parallel)
1 : Transfer PR0 to PSC
1

0
: Select RLD
0
0 : Select the RLD addressed by X/Y input
1 : Select both XRLD and YRLD together
(Note: D7 = 1 overrides X/Y input)
Counter Mode Registers: XCMR and YCMR
The CNTR operational mode is programmed by writing into the CMRs.

CMR
7 6 5 4 3 2 1 0

0: Binary count
1: BCD count

0 : Normal count
0

1 : Range Limit
0
0
: Non-recycle count
1
1
: Modulo-N
1
0
: Non-quadrature
0
1
: Quadrature X1
0

0
: Quadrature X2
1
1
: Quadrature X4
1
1 : Select CMR
0
0: Select CMR addressed by X/Y input
1: Select both XCMR and YCMR together (Note: D7=1 overrides X/Y input)

DEFINITIONS OF COUNT MODES:

Range Limit. In range limit count mode, an upper and a lower limit is set, mimicking limit switches in the me-
chanical counterpart. The upper limit is set by the content of the PR and the lower limit is set to be 0. The
CNTR freezes at CNTR=PR when counting up and at CNTR=0 when counting down. At either of these limits,
the counting is resumed only when the count direction is reversed.

Non-Recycle. In non-recycle count mode, the CNTR is disabled, whenever a count overflow or underflow takes
place. The end of cycle is marked by the generation of a Carry (in Up Count) or a Borrow (in Down Count). The
CNTR is re-enabled when a reset or load operation is performed on the CNTR.

Modulo-N. In modulo-N count mode, a count boundary is set between 0 and the content of PR. When counting
up, at CNTR=PR, the CNTR is reset to 0 and the up count is continued from that point. When counting down, at
CNTR=0, the CNTR is loaded with the content of PR and down count is continued from that point.

The modulo-N is true bidirectional in that the divide-by-N output frequency is generated in both up and down di-
rection of counting for same N and does not require the complement of N in the UP instance. In frequency di-
vider application, the modulo-N output frequency can be obtained at either the Compare (FLG1) or the Borrow
(FLG2) output. Modulo-N output frequency, fN = (fi / (N+ 1) ) where fi = Input count frequency and N=PR.

The information included herein is believed to be

accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
Input/Output Control Register: XIOR and YIOR
The functional modes of the programmable input and output pins are written into the IORs.

IOR

7 6 5 4 3 2 1 0

0 : Disable inputs A and B

1 : Enable inputs A and B
0 : LCNTR/LOL pin is Load CNTR input
1 : LCNTR/LOL pin is Load OL input

0 : RCNTR/ABG pin is Reset CNTR input

1 : RCNTR/ABG pin is A and B Enable gate

0
: FLG1 pin is CARRY output; FLG2 pin is BORROW output
0

1
: FLG1 pin is COMPARE output; FLG2 pin is BORROW output
0
0
: FLG1 pin is Carry/Borrow output and FLG2 pin is U/D (FLAG register bit 5)
1
1
: FLG1 is IDX (FLAG register bit 6); FLG2 is E (FLAG register bit 4)
1

0
: Select IOR
1

0: Select IOR addressed by X/Y input

1: Select both XIOR and YIOR together (Note: D7=1 overrides X/Y input)

INDEX CONTROL REGISTERS: XIDR and YIDR

Either the LCNTR/LOL or the RCNTR/ABG inputs can be initialized to operate as an index input. When
initialized as such, the index signal from the encoder, applied to one of these inputs performs either the
Reset CNTR or the Load CNTR or the Load OL operation synchronously with the quadrature clocks. Note
that only one of these inputs can be selected as the Index input at a time and hence only one type of in-
dexing function can be performed in any given set-up. The index function must be disabled in non-
quadrature count mode.

IDR
7 6 5 4 3 2 1 0

0: Disable Index
1: Enable Index
0: Negative Index Polarity
1: Positive Index Polarity

0: LCNTR/LOL pin is indexed (See Note 1)

1: RCNTR/ABG pin is indexed (See Note 2)

: Not used

1
: Select IDR
1
0: Select IDR addressed by X/Y input
1: Select both XIDR and YIDR (Note: D7=1 overrides X/Y input)

Note 1 : Function selected for this pin via IOR, becomes the operating INDEX function.

Note 2: RCNTR/ABG input must also be initialized as the reset CNTR input via IOR
 REGISTER ADDRESSING MODES
D7 D6 D5 C/D RD WR X/Y CS FUNCTION
X X X X X X X 1 Disable both axes for Read/Write

X X X 0 1 0 0 Write to XPR byte segment addressed by XBP (Note 3)

X X X 0 1 1 0 Write to YPR byte segment addressed by YBP (Note 3)

0 0 0 1 1 0 0 Write to XRLD

0 0 0 1 1 1 0 Write to YRLD

1 0 0 1 1 X 0 Write to both XRLD and YRLD

0 0 1 1 1 0 0 Write to XCMR
0 0 1 1 1 1 0 Write to YCMR

1 0 1 1 1 X 0 Write to both XCMR and YCMR

0 1 0 1 1 0 0 Write to XIOR

0 1 0 1 1 1 0 Write to YIOR
1 1 0 1 1 X 0 Write to both XIOR and YIOR
0 1 1 1 1 0 0 Write to XIDR
0 1 1 1 1 1 0 Write to YIDR

1 1 1 1 1 X 0 Write to both XIDR and YIDR

X X X 0 0 1 0 0 Read XOL byte segment addressed by XBP (Note 3)

X X X 0 0 1 1 0 Read YOL byte segment addressed by YBP (Note 3)

X X X 1 0 1 0 0 Read XFLAG

X X X 1 0 1 1 0 Read YFLAG

X = Don't Care

Note 3 : Relevant BP is automatically incremented at the trailing edge of RD or WR pulse

Absolute Maximum Ratings:

Parameter Symbol Values Unit
Voltage at any input VIN VSS-.3 to VDD+.3 V
Supply Voltage VDD +7.0 V
Operating Temperature TA -25 to +80 oC
Storage Temperature TSTG -65 to +150 oC

DC Electrical Characteristics. (TA = -25˚C to +80°C, VDD = 4.5V to 5.5V)

Parameter Symbol Min. Value Max.Value Unit Remarks

Supply Voltage VDD 4.5 5.5 V -
Supply Current IDD - 800 µA All clocks off
Input Logic Low VIL - 0.8 V -
Input Logic High VIH 2.0 - V -
Output Low Voltage VOL - 0.5 V IOSNK=5mA
Output High Voltage VOH VDD-.5 - V IOSRC=1mA
Input Leakage Current IILK - 30 nA -
Data Bus Leakage Current IDLK - 60 nA Data bus off
Output Source Current IOSRC 1.0 - mA VO = VDD-.5V
Output Sink Current IOSNK 5.0 - mA VO = 0.5V

7266R1-111196-5
Transient Characteristics. (TA = -25˚C to +80˚C, VDD = 4.5V to 5.5V)

Parameter Symbol Min. Value Max.Value Unit Remarks

Read Cycle (See Fig. 1)
RD Pulse Width tr1 50 - ns -
CS Set-up Time tr2 50 - ns -
CS Hold Time tr3 0 - ns -
C/D Set-up Time tr4 50 - ns -
C/D Hold Time tr5 10 - ns -
X/Y Set-up Time tr6 50 - ns -
X/Y Hold Time tr7 10 - ns -
Data Bus Access Time tr8 50 - ns Access starts when both RD
and CS are low.
Data Bus Release Time tr9 - 25 ns Release starts when either RD
or CS is terminated.
Back to Back Read delay tr10 60 - ns -

Write Cycle (See Fig. 2)

WR Pulse Width tW1 30 - ns -
CS Set-up Time tW2 30 - ns -
CS Hold Time tW3 0 - ns -
C/D Set-up Time tW4 30 - ns -
C/D Hold Time tW5 10 - ns -
X/Y Set-up Time tW6 30 - ns -
X/Y Hold Time tW7 10 - ns -
Data Bus Set-up Time tW8 30 - ns -
Data Bus Hold Time tW9 10 - ns -
Back to Back Write Delay tW10 60 - ns -

Quadrature Mode (See Fig. 3-5)

FCK High Pulse Width t1 14 - ns -
FCK Low Pulse Width t2 14 - ns -
FCK Frequency fFCK - 35 MHz -
Mod-n Filter Clock(FCKn)Period t3 28 - ns t3 = (n+1) (t1+t2), where
n = PSC= 0 to FFH
FCKn frequency fFCKn - 35 MHz -
Quadrature Separation t4 57 - ns t4 ≥ 2t3
Quadrature Clock Pulse Width t5 115 - ns t5 ≥ 4t3
Quadrature Clock frequency fQA, fQB - 4.3 MHz fQA = fQB = 1/8t3
Quadrature Clock to Count Delay tQ1 5t3 6t3 - -
X1/X2/X4 Count Clock Pulse Width tQ2 28 - ns tQ2 = t3
Index Input Pulse Width tidx 85 - ns tidx ≥ 3t3
Index Skew from A tAi - 28 ns tAi ≤ t3
Carry/Borrow/Compare Output Width tQ3 28 - ns tQ3 = t3

Non-Quadrature Mode (See Fig. 6-7)

Clock A - High Pulse Width t6 16 - ns -
Clock A - Low Pulse Width t7 16 - ns -
Direction Input B Set-up Time t8S 20 - ns -
Direction Input B Hold Time t8H 20 - ns -
Gate Input (ABG) Set-up Time tGS 20 - ns -
Gate Input (ABG) Hold Time tGH 20 - ns -
Clock Frequency (non-Mod-N) fA - 30 MHz fA = ( 1/ (t6 + t7) )
Clock Frequency (Mod-N) fAN - 25 MHz -

Clock to Carry or Borrow Out Delay t9 - 30 ns -

Carry or Borrow Out Pulse Width t10 16 - ns t10 = t7
Load CNTR, Reset CNTR and
Load OL Pulse Width t11 20 - ns -
Clock to Compare Out Delay t12 50 - ns -
 INPUTS/OUTPUTS

X-AXIS I/Os:
XA (Pin 20) X-axis count input A Either quadrature encoded clocks or non-quadrature clocks can be applied
XB (Pin 21) X-axis count input B to XA and XB. In quadrature mode XA and XB are digitally filtered and decoded
for UP/DN clock. In non-quadrature mode, the filter and the decoder circuits are
by-passed. Also, in non-quadrature mode XA serves as the count input and XB
as the UP/DOWN direction control input, with XB = 1 selecting Up Count mode
and XB = 0, selecting Down Count mode.
XLCNTR/XLOL X-axis programmable input, to operate as either direct load XCNTR or direct load XOL or synchronous
(Pin 19) load XCNTR or synchronous load XOL. The synchronous load mode is intended for interfacing with
the encoder Index output in quadrature clock mode. In direct load mode, a logic low level is the active
level at this input. In synchronous load mode the active level can be programmed to be either logic
low or logic high. Both quarter-cycle and half-cycle Index signals are supported by this input in the in-
dexed Load mode. The synchronous function must be disabled in non-quadrature count mode (See
description of IDR on P. 4)

XRCNTR/XABG X-axis programmable input to operate either as direct reset XCNTR or count enable/disable gate or
(Pin 18) synchronous reset XCNTR. The synchronous reset XCNTR mode is intended for interfacing with the
encoder Index output in quadrature clock mode. In direct reset XCNTR mode, a logic low level is the
active level at this input whereas in synchronous reset XCNTR mode the active level can be pro-
grammed to be either a logic low or a logic high. Both quarter-cycle and half-cycle index signals are
supported by this input in the indexed reset CNTR mode. The synchronous function must be disabled
in non-quadrature count mode (See description of IDR on P. 4). In count enable/disable mode, a logic
high at this input enables the counter and a logic low level disables the counter.

XFLG1 (Pin 22) X-axis programmable output to operate either as XCARRY (Active low), or XCOMPARE (generated
when XPR=XCNTR; Active low), or XIDX (XFLAG bit 6) or XCARRY/XBORROW (Active low).

XFLG2 (Pin 23) X-axis programmable output to operate as either XBORROW (Active low) or XU/D (XFLAG bit 5)
or XE (XFLAG bit 4).

Y-AXIS I/Os:
All the X-axis inputs/outputs are duplicated for the Y-axis with similar functionalities.
YA (Pin 25)
YB (Pin 24)
YLCNTR/YLOL (Pin 1)
YRCNTR/YABG (Pin 28)
YFLG1 (Pin 27)
YFLG2 (Pin 26)

COMMON I/Os:
WR (Pin 14) Write input. Control/data bytes are written at the trailing edge of low level pulse applied to this input.

RD (Pin 16) Read input. A low level applied to this input enables the FLAGs and OLs to be read on the data bus.

CS (Pin 15) Chip select input. A low level applied to this input enables the chip for Read and Write.

C/D (Pin 13) Control/Data input. This input selects between a control register or a data register for Read/Write.
When low, a data register is selected. When high, a control register is selected.

D0-D7 Data Bus input/output. The 8-bit three-state data bus is the I/O port through which all data transfers
(Pins 4-11) take place between the LS7266R1 and the host processor.

FCK (Pin 2) Filter clock input in quadrature mode. The FCK is divided down internally by two 8-bit programmable
prescalers, one for each channel.

X/Y (Pin 17) Selects between X and Y axes for Read or Write. X/Y = 0 selects X-axis and X/Y = 1 selects Y-axis.
X/Y is overridden by D7 =1 in Control Write Mode (C/D = 1).

VDD (Pin 3) +5VDC

VSS (Pin 12) GND

 tr1 tr10
RD

tr2 tr3
CS

tr4 tr5
C/D
tr6 tr7
X/Y
tr8 tr9
DB VALID
DATA VALID DATA

FIGURE 1. READ CYCLE

tw1 tw10

WR

tw2 tw3
CS

tw4 tw5

C/D
tw6 tw7
X/Y
tw8 tw9

DB INPUT DATA INPUT DATA

FIGURE 2. WRITE CYCLE

t1 t2

FCK
t3

FCKn
(Note 4) t5

A
t4 t4 t4 t4

B
t5

FIGURE 3. FILTER CLOCK FCK AND QUADRATURE CLOCKS A AND B

Note 4: FCKn is the final modulo-n internal filter clock, arbitrarily shown here as modulo-1.
 UP DOWN

A
tAi tAi

INDEXI
(Note 5) tidx

X1 CLOCK
(Note 6)
tQ1
X2 CLOCK
(Note 6)
tQ2
X4 CLOCK
(Note 6)

IDX
(Note 7)

FIGURE 4. QUADRATURE CLOCK A, B AND INDEX INPUT

Note 5: Shown here is positive index with solid line depicting 1/4 cycle index and dotted line depicting 1/2 cycle index.
Either LCNTR/LOL or RCNTR/ABG input can be used as the INDEX input.

Note 6: X1, X2 and X4 clocks are the final internal Up/Down count clocks derived
from filtered and decoded Quadrature Clock inputs, A and B.

Note 7: IDX is the synchronized internal "load OL" or "load CNTR" or "reset CNTR" signal based on LCNTR/LOL
or RCNTR/ABG input being selected as the INDEX input, respectively. This signal is identical with
FLAG register bit 6.

UP DOWN

X4 CLOCK
(Internal)
t Q2
CNTR FFFFFD FFFFFE FFFFFF 0 1 2 3 2 1 0 FFFFFF FFFFFE

CY

t Q3
BW

t Q3 t Q3
COMPARE
(Note 8)

CT(FLAG-B1)

BT(FLAG-B0)

CPT(FLAG-B2)

FIGURE 5. CARRY, BORROW, COMPARE, CARRY TOGGLE, BORROW TOGGLE AND

COMPARE TOGGLE IN X4 QUADRATURE, NORMAL, BINARY COUNT MODE.

Note 8: COMPARE is generated when PR = CNTR. In this timing diagram it is arbitrarily assumed that PR = 1.
 DOWN UP DOWN

DIRECTION (B)
t8S t8H

COUNT IN (A)
tGS tGH

GATE (ABG)

COUNT DISABLE COUNT ENABLE

FIGURE 6. COUNT (A), DIRECTION (B) AND GATE (ABG) INPUTS IN NON-QUADRATURE MODE

B
t9

CY
CNTR DISABLED t9 t10
BW

CNTR DISABLED CNTR DISABLED

CNTR 999998 999999 0 1 2 1 0 999999 0 999999 N N-1 N-2

CNTR ENABLED
RCNTR
CNTR ENABLED t11 CNTR ENABLED

LCNTR

t11

FIGURE 7. NON-RECYCLE, NON-QUADRATURE, BCD MODE

B UP DOWN

CNTR 0 1 2 3 0 1 2 1 0 3 2 1 0 3 2
t12

COMP

BW

FIGURE 8. MODULO - N, NON-QUADRATURE (Shown with N = 3)

DOWN
B UP UP

CNTR 0 1 2 3 4 (CNTR FROZEN) 3 2 1 0 (CNTR FROZEN) 1 2

COMP

BW

FIGURE 9. RANGE LIMIT, NON-QUADRATURE (Shown with PR = 4)

 8

WRITE INPUT REG (8) FLAG (8)

8 SBYTE0

BP SBYTE1
SBYTE2 SBYTE1 SBYTE0 SBYTE2
8 8 8

PR2 (8) PR1 (8) PR0 (8) RLD

8
8 8 CMR

IOR

IDR
24
PRO
8

PSC
CNTR (24) (8)

24
FCK PRESCALER FCK
DIRECTION
FCKn

24 ERROR

COMPARATOR (24)

COUNT CLOCK A
BYTE 0 CLOCK
DIRECTION GEN/FILTER
BYTE 1 B

BYTE 2
8
8
SBYTE2 8 SBYTE1 SBYTE0

OL2 (8) OL1 (8) OL0 (8)

8 8 8
8 INTERNAL BUS

READ/WRITE I/O BUF

DATA-BUS
ISA BUS

D7 LS7266R1
D6
D5
D4 D0 4
D3 D0
D1 5 D1 I4 IOW
D2 D2 6
D1 D2 WR I6
D3 7 D3 IOR
D0 D4 8 RD
D4 I3 A0
D5 9 D5 C/D
PC AT/XT D6 10 I7 A1
D6 X/Y
D7 11 D7 I5
CS

AEN

A9
A8
A7 ADDRESS
A6 DECODER
A5
A4
A3
A2
A1
A0
IOR
IOW

FIGURE 11A. LS7266R1 INTERFACE EXAMPLES

ADDRESS CS
A1-A23
DECODE

MC68000 A1 C/D
MC68010 A2 X/Y
MC68HC000

D0-D7 D0-D7

R/W
RD LS7266R1

LDS

WR

DTACK

FIGURE 11B. LS7266R1 INTERFACE EXAMPLES