Low Power VLSI Mid-Term Evaluation

Low Power VLSI

B.Tech. Project
Electronics Engineering

Mentor : (Prof.) Dr. V.N. Mishra

Submitted by :

• Rohit Kumar : 12105EN002

• Tarunvir Singh : 12105EN018
• Ranjit Kumar Singh : 12105EN046
• Vipul Bajpai : 11105EN003

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Low Power VLSI Mid-Term Evaluation

Contents :

1. Abstract

2. VLSI Introduction

3. History and Importance of VLSI

4. Developments and Challenges in VLSI

5. CMOS vs. NMOS tech

6. Power Wastage in CMOS

7. Methods to reduce leakage current

8. Next semester goals

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Low Power VLSI Mid-Term Evaluation

Abstract

Power consumption in electronics is one of the major defining factors. A modern

day consumer wants to extract the most by paying the minimum possible amount.
With the advent of portable wireless devices, that rely on battery; power con-
sumption of underlying circuitry has gained a new importance. Today most of our
electronics spend the majority of their operational lives sitting in standby modes,
ready to be fully operational in minimum possible time. Hence a major chunk of
power is wasted when the device is sitting in stand-by mode.

Also as the technology size shrinks the standby and static power consumptions
start playing a major role in overall power consumption of the device. Sub-thresh-
old leakage currents, channel punch through, tunnelling and currents due to hot
carrier injection from the gate become more dominant as the size of the MOSFET
shrinks.

To combat the above problem various power management techniques are being
applied today. This report discusses the basic of VLSI, various methods due to
which power leakage occurs and methods which are being employed to combat
power leakage. The report will be concluded by laying out the future prospects of
this B.Tech project.

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Low Power VLSI Mid-Term Evaluation

VLSI Introduction

VLSI stands for Very-large-scale Integration. Many sources define it as :

Very-large-scale integration (VLSI) is the process of creating an integrated circuit

(IC) by combining thousands of transistors into a single chip. VLSI began in the
1970s when complex semiconductor and communication technologies were be-
ing developed. The microprocessor is a VLSI device. Before the introduction of
VLSI technology most ICs had a limited set of functions they could perform. An
electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI
lets IC designers add all of these into one chip.

History and Importance

During the early 20th century, electronic scientists attempted to create devices
that could control currents in a solid state device (Triacs) Success did not come
until WWII. During the WWII, worldwide scientists were devoted to researching
how silicon and germanium crystals could be improved and utilised better for ra-
dar detection. This led to a better understanding of how the carriers in a semicon-
ductor behave. After the war the scientist diverted to radar returned back to solid
state electronics. With the new found knowledge of semiconductors, a solid state
transistor was invented in 1947 at Bell Labs.

In the 1950s the electronics shrunk in size as the solid state transistor replaced
vacuum tube transistors. the engineers saw this as an opportunity to construct far
more complicated and fast circuits than previously possible. this led to a pandora
of new problems.

One main problem (again) was the size of circuits. A complex circuit like a com-
puter was usable only due to its speed. But due to discreet components, intercon-
necting wires and the parasitic capacitances the electric signals couldn't travel
fast enough through the circuit, hence making the computer ineffective.

Jack Kilby at Texas Instruments found a solution to this problem in 1958. the
novel idea was to make all the components of an electronic circuit on a single
block of semiconductor crystal and to use another layer of metal to connect the
components fabricated. This idea if implemented successfully would eradicate
wires, the necessity to assemble a circuit from discreet components would not be
there and the whole process of circuit manufacture could be automated.

In September 1958 Jack Kilby had his first integrated circuit ready. The first IC
was crude and had many bugs but it opened the doors to monolithic circuit design
and a patent of making all the parts out of the same block of material and adding

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the metal needed to connect them as a layer on top of it, there was no need for
discrete components. The same patent made billions of dollars for Texas Instru-
ments in the upcoming years as royalty compensation.

From here, the idea of integrating all components on a single crystal came into
existence, which led to development in small-scale integration (SSI) in the early
1960s, medium-scale integration (MSI) in the late 1960s, and then large-scale in-
tegration (LSI) as well as VLSI in the 1970s and 1980s, with tens of thousands of
transistors on a single chip (later hundreds of thousands, then millions, and now
billions (10^9).

Developments
The first transistor chips held two transistors each. Subsequent advances led to a
higher no. of devices being added to the chip. the first fully integrated devices
held only a handful components on chip, around as many as tens of resistors, di-
odes and transistors that led to fabrication of a single gate on a chip. Now known
as small-scale integration (SSI). Improvements in techniques led to hundreds of
components in one chip known as medium-scale integration (MSI). Chips with at
least a thousand logic gates were classified into large -scale integration (LSI).
Technology today has gone way beyond that, today’s VLSI chips containing
many millions of logic gates and billions of individual transistors are common.

Terms like ultra-large-scale integration (ULSI) were used to demarcate between

VLSI and today’s technology. But the line was so thin that the name ULSI was
dropped. today all chips that fall in the ballpark of tens of thousands of logic gates
to millions of logic gates come under VLSI.

As of early 2008, billion-transistor processors are commercially available. This

became more commonplace as semiconductor fabrication advanced from the
then-current generation of 65 nm processes. Current designs, unlike the earliest
devices, use extensive design automation and automated logic synthesis to lay
out the transistors, enabling higher levels of complexity in the resulting logic func-
tionality. Certain high-performance logic blocks like the SRAM (static random-ac-
cess memory) cell, are still designed by hand to ensure the highest efficiency.
VLSI technology may be moving toward further radical miniaturisation with intro-
duction of NEMS (Nanoelectromechanical systems) technology.

Challenges

As ICs became more complex due to technology scaling, IC designers have en-
countered several challenges. Some of the challenges are listed below.

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• Process variation – As photolithography techniques tend closer to the funda-

mental laws of optics, achieving high accuracy in doping concentrations and
etched wires is becoming more difficult and prone to errors due to variation. De-
signers now must simulate across multiple fabrication process corners before a
chip is certified ready for production.

• Stricter design rules – Due to lithography and etch issues with scaling, design
rules for layout have become increasingly stringent. Designers must keep ever
more of these rules in mind while laying out custom circuits. The overhead for
custom design is now reaching a tipping point, with many design houses opting
to switch to electronic design automation (EDA) tools to automate their design
process.

• Timing/design closure – As clock frequencies tend to scale up, designers are

finding it more difficult to distribute and maintain low clock skew between these
high frequency clocks across the entire chip. This has led to a rising interest in
multicore and multiprocessor architectures, since an overall speedup can be ob-
tained by lowering the clock frequency and distributing processing.

• First-pass success – As die sizes shrink (due to scaling), and wafer sizes go up
(due to lower manufacturing costs), the number of dies per wafer increases, and
the complexity of making suitable photomasks goes up rapidly. A mask set for a
modern technology can cost several million dollars. This non-recurring expense
deters the old iterative philosophy involving several "spin-cycles" to find errors in
silicon, and encourages first-pass silicon success. Several design philosophies
have been developed to aid this new design flow, including design for manufac-
turing (DFM), design for test (DFT), and Design for X.

• Power Consumption - As the technology feature size shrink static power con-
sumption dominant the dynamic power exponentially and this static power con-
sumption is known as a sub-threshold leakage. Sub-threshold leakage is a leak-
age that is arises by creating a weak inversion channel between drain to source.
However, tunnelling current through gate oxide insulator, channel punch
through current and gate current due to hot-carrier injection are also responsible
for semiconductor power consumption. Although gate-oxide thickness will be re-
duced as the technology decreases in nano scale, but this reduction causes
sub-threshold leakage.

We will be focusing on the issue of power consumption during the rest of this re-
port.

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CMOS vs. NMOS

Both CMOS and NMOS led to large development of VLSI. the small size of both
the technologies led to exponential reduction in size of the chips. We will discuss
both CMOS and NMOS briefly below.

NMOS

N-type metal-oxide-semiconductor logic uses n-type field effect transistors

(MOSFETs) to implement logic gates and other digital circuits. These nMOS tran-
sistors operate by creating an inversion layer in an p-type transistor body. This in-
version layer, called the n-channel, can conduct electrons between n-type
"source" and "drain" terminals. The n-channel is created by applying voltage to
the third terminal, called the gate.

The MOSFETs are n-type enhancement mode transistors arranged in a so-called

"pull-down network" (PDN) between the logic gate output and negative supply
voltage. A pull up is placed between the positive supply voltage and each logic
gate output. Any logic gate, including the logical inverter, can then be imple-
mented by designing a network of parallel and/or series circuits such that if the
desired output for a certain combination of boolean input values is zero (or false),
the PDN will be active, meaning that at least one transistor is allowing a current
path between the negative supply and the output. This causes a voltage drop
over the load, and thus a low voltage at the output, representing the zero.

As an example, here is a NOR gate implemented in schematic NMOS. If either in-

put A or input B is high (logic 1, = True), the respective MOS transistor acts as a
very low resistance between the output and the negative supply, forcing the out-
put to be low (logic 0, = False). When both A and B are high, both transistors are
conductive, creating an even lower resistance path to ground. The only case
where the output is high is when both transistors are off, which occurs only when
both A and B are low, thus satisfying the truth table of a NOR gate:

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A B A NOR B

0 0 1

0 1 0

1 0 0

1 1 0

CMOS

CMOS stands for Complementary Metal-Oxide-Semiconductor. On the other

hand, NMOS is a metal oxide semiconductor MOS or MOSFET(metal-oxide-sem-
iconductor field effect transistor). These are two logic families, where CMOS uses
both PMOS and MOS transistors for design and NMOS uses only FETs for de-
sign. CMOS is chosen over NMOS for embedded system design. Because,
CMOS propagates both logic o and 1, whereas NMOS propagates only logic 1
that is VDD. The O/P after passing through one, the NMOS gate would be VDD-
Vt. Therefore, CMOS technology is preferred.

In CMOS logic gates, a set of n-type MOSFETs is positioned in a pull-down net-

work between the low-voltage power supply rail and the output. Instead of the
load resistor of NMOS logic gates, CMOS logic gates have a collection of P-type
MOSFETs in a pull-up network between the high-voltage rail and the output.
Therefore, if both transistors have their gates connected to the same input, the p-
type MOSFET will be on when the n-type MOSFET is off, and vice-versa.

A CMOS inverter has a PMOS and an NMOS transistor that is connected at the
gate and drain terminals, a voltage supply VDD at the PMOS source terminal,
and a GND connected at the NMOS source terminal, where Vin is connected to
the gate terminals and Vout is connected to the drain terminals. It is important to
notice that the CMOS does not have any resistors, which makes it more power
efficient than a regular resistor-MOSFET inverter .As the voltage at the input of
the CMOS device varies between 0 and 5 volts, the state of the NMOS and
PMOS varies accordingly. If we model each transistor as a simple switch acti-
vated by Vin, the inverter’s operations can be seen very easily.

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Due to the above mentioned properties, CMOS currently is the most widely used
technology in VLSI design.

We will hence be focusing on the power consumption and power wastage of a

typical CMOS. If the power wastage in a CMOS is minimised then the overall
wastage in a VLSI chip would be drastically reduced.

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Comparison Parameters

 Power dissipation:

• Static :CMOS devices have very low static power dissipation, which
is the result of leakage current. This power consumption occurs when
all inputs are held at some valid logic level and the circuit is not in the
charging states.

• Dynamic: When inputs are switching at a very high frequency, dy-

namic power consumption can contribute considerably to overall
power consumption. Charging and discharging a capacitive output
load further increases this dynamic power consumption.

 Propagation delay: Propagation delay is a time associated with any

digital circuit and is the time between when an input to the circuit
changes until that change propagates through the circuit and changes
the output.

 Power delay product: The power-delay product (PDP) is a fundamen-

tal parameter which is often used for measuring the quality and the
performance of a CMOS process and gate design. As a physical
quantity, the power-delay product can be interpreted as the average
energy required for a gate to switch its output voltage from low to high
and from high to low. The smaller the power delay product is, the
better the logic family is considered to be.

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Low Power VLSI Mid-Term Evaluation

 Area: Area required for the fabrication of a transistor is a very im-

portant point and need to be considered.

 State retention : State retention between pre and post-sleep mode is

also an important factor .If there in no state retention then reconfigura-
tion is required. So state retention is desired.

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Power wastage in CMOS

As mentioned above a typical CMOS should not consume any power in static
mode. But it is not true, as with reducing technology size the static leakage char-
acteristics are dominating.

The following are some phenomenons which are responsible for static leakage
currents leading to power wastage.

• Sub-Threshold leakage
• Gate oxide leakage
• Channel punch through
• Drain inducted barrier lowering
• Gate current due to hot-carrier injection

We will discuss the above phenomenons one by one.

Sub-Threshold leakage

Subthreshold conduction or subthreshold leakage or subthreshold drain current is

the current between the source and drain of a MOSFET when the transistor is in
subthreshold region, or weak-inversion region, that is, for gate-to-source voltages
below the threshold voltage.

In the past, the subthreshold conduction of transistors has usually been very
small in the off state, so small that majority of SPICE models considered zero off
state current. This was because the gate voltage could be significantly below
threshold; but as voltages have been scaled down with transistor size, subthresh-
old conduction has become a bigger factor.

The reason for a growing importance of subthreshold conduction is that the sup-
ply voltage has continually scaled down, both to reduce the dynamic power con-
sumption of integrated circuits (the power that is consumed when the transistor is
switching from an on-state to an off-state, which depends on the square of the
supply voltage), and to keep electric fields inside small devices low, to maintain
device reliability. The amount of subthreshold conduction is set by the threshold
voltage, which sits between ground and the supply voltage, and so has to be re-
duced along with the supply voltage. That reduction means less gate voltage
swing below threshold to turn the device off, and as subthreshold conduction var-
ies exponentially with gate voltage, it becomes more and more significant as
MOSFETs shrink in size.

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Gate oxide leakage

SiO2 is a very good insulator, but at very small thickness levels electrons can tun-
nel across the very thin insulation; the probability drops off exponentially with ox-
ide thickness. Tunnelling current becomes very important for transistors below
130 nm technology with gate oxides of 20 Å or thinner.

Channel punch through

Punch through in a MOSFET is an extreme case of channel length modulation
where the depletion layers around the drain and source regions merge into a sin-
gle depletion region. The field underneath the gate then becomes strongly de-
pendent on the drain-source voltage, as is the drain current. Punch through
causes a rapidly increasing current with increasing drain-source voltage. This ef-
fect is undesirable as it increases the output conductance and limits the maxi-
mum operating voltage of the device

Drain inducted barrier lowering

Drain induced barrier lowering (DIBL) is the effect the drain voltage on the output
conductance and measured threshold voltage. This effect occurs in devices
where only the gate length is reduced without properly scaling the other dimen-
sions. It is observed as a variation of the measured threshold voltage with re-
duced gate length. The threshold variation is caused by the increased current
with increased drain voltage as the applied drain voltage controls the inversion
layer charge at the drain, thereby competing with the gate voltage. This effect is
due to the two-dimensional field distribution at the drain end and can typically be
eliminated by properly scaling the drain and source depths while increasing the
substrate doping density.

Gate current due to hot-carrier injection

Hot carrier injection (HCI) is a phenomenon in solid-state electronic devices
where an electron or a “hole” gains sufficient kinetic energy to overcome a poten-
tial barrier necessary to break an interface state. The term "hot" refers to the ef-
fective temperature used to model carrier density, not to the overall temperature
of the device. Since the charge carriers can become trapped in the gate dielectric
of a MOS transistor, the switching characteristics of the transistor can be perma-
nently changed. Hot-carrier injection is one of the mechanisms that adversely af-
fects the reliability of semiconductors of solid-state devices.
In MOSFETs, hot electrons have sufficient energy to tunnel through the thin oxide
gate to show up as gate current, or as substrate leakage current. The hot elec-
trons may jump from the channel region or from the drain, for instance, and into
the gate or the substrate.

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Methods to combat leakage current

previous low power techniques primarily target reducing power consumption of

CMOS circuits. The prevailing techniques drastically reduce the leakage power of
CMOS circuits with some area or power - delay product trade-offs.

During the stand-by mode, the current state of the logic gates may or may not
need to be saved. Hence the leakage reducing techniques can be divide into two
broad categories namely (1) State saving, and (2) State destructive. Both have
varying results and complexity in designing the system.

The state saving techniques save the state of logic gates in both active as well as
sleep states. Whereas the state destructive techniques save state in only the ac-
tive mode. As a result devices that are made low power using state destructive
techniques have a relatively longer wake-up time. Hence these techniques are
not used where immediate resumption of task from standby mode is required.

We will be considering the following methodologies adapted for reducing leakage

current in CMOS circuits :

• Sleep Transistor Technique

• Sleepy Stack Technique
• Sleepy Keeper technique
• Dual Sleep Technique
• Dual Stack Technique

Sleep Transistor Technique

This is a widely used technique, in this an additional “sleep”
PMOS is placed between the VDD and the pull up network of the
circuit and an additional NMOS is placed between the GND and
the pull down network of the circuit. The sleep transistors cutoff
the power rails from the network when in sleep mode. These
sleep transistors can reduce the leakage current effectively. But
this leads to state destruction and a floating point output in sleep
state.

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Sleepy Stack Technique

This technique divides the existing transistors into two half
length transistors using the stack effect. The sleep transistors
are connected in parallel to one of the divided transistors. Dur-
ing sleep mode the sleep transistors are switched off and the
stacked transistors suppress the leakage current while saving
the logic state. This has major power delay penalty as every
transistor is replaced with 3 transistors.

Sleepy Keeper Technique

This technique utilises leakage feedback. In this technique a
PMOS transistor is placed in parallel to the sleep transistor (S)
and a NMOS transistor is placed in parallel to the sleep transis-
tor (S’). The two transistors are driven by the output of the in-
verter. During sleep mode, sleep transistors are turned off and
one of the transistors in parallel to the sleep transistors keep
the connection with the appropriate power rail.

Dual Sleep Technique

Dual sleep technique uses the advantage of using the two extra
pull-up and two extra pull-down transistors in sleep mode either in
OFF state or in ON state. Since the dual sleep portion can be
made common to all logic circuitry, less number of transistors is
needed to apply a certain logic circuit.

Dual Stack Technique

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In dual stack technique, 2 PMOS in the pull-down network and 2 NMOS in the
pull-up network are used. The advantage is that NMOS degrades the high logic
level while PMOS degrades the low logic level. Compared to previous techniques
it requires greater power delay product. The delay is also increased.

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