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DLD Lab Verilog

The document describes Verilog code implementations for AND, OR, NOT, NOR, and NAND logic gates. Each gate module defines inputs and outputs and assigns the output based on the logic function. A test bench module is provided for each gate that applies stimulus to the inputs and observes the output over time.

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faizan khan
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82 views10 pages

DLD Lab Verilog

The document describes Verilog code implementations for AND, OR, NOT, NOR, and NAND logic gates. Each gate module defines inputs and outputs and assigns the output based on the logic function. A test bench module is provided for each gate that applies stimulus to the inputs and observes the output over time.

Uploaded by

faizan khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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AND GATE:

module ANDGATE(

input A,

input B,

output C

);

assign C=A&&B;

endmodule

TEST BENCH:

module ANDGATECHORU;

// Inputs

reg A;

reg B;

// Outputs

wire C;

// Instantiate the Unit Under Test (UUT)

ANDGATE uut (

.A(A),

.B(B),

.C(C)

);
initial begin

// Initialize Inputs

A = 0;

B = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

A=1;

B=0;

#100;

A=0;

B=1;

#100;

A=1;

B=1;

#100;

end

endmodule

OR GATE:
module OR(

input a,

input b,

output c

);

assign c=a||b;

endmodule

TEST BENCH:

module OR2;

// Inputs

reg a;

reg b;

// Outputs

wire c;

// Instantiate the Unit Under Test (UUT)

OR uut (

.a(a),

.b(b),

.c(c)

);
initial begin

// Initialize Inputs

a = 0;

b = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a=0;

b=1;

#100;

a=1;

b=0;

#100;

a=1;

b=1;

#100;

end

endmodule

NOT GATE:
module NOT(

input a,

output b

);

assign b=~a;

endmodule

TEST BENCH:

module NOT2;

// Inputs

reg a;

// Outputs

wire b;

// Instantiate the Unit Under Test (UUT)

NOT uut (

.a(a),

.b(b)

);

initial begin

// Initialize Inputs
a = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a=1;

#100;

end

endmodule

NOR GATE:

module NOR(

input a,

input b,

output c

);

assign c=~(a||b);

endmodule

TEST BENCH:

module NOR2;
// Inputs

reg a;

reg b;

// Outputs

wire c;

// Instantiate the Unit Under Test (UUT)

NOR uut (

.a(a),

.b(b),

.c(c)

);

initial begin

// Initialize Inputs

a = 0;

b = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a=0;
b=1;

#100;

a=1;

b=0;

#100;

a=1;

b=1;

#100;

end

endmodule

NAND GATE:

module NAND(

input a,

input b,

output c

);

assign c=~(a&&b);

endmodule

TEST BENCH:

module NAND2;
// Inputs

reg a;

reg b;

// Outputs

wire c;

// Instantiate the Unit Under Test (UUT)

NAND uut (

.a(a),

.b(b),

.c(c)

);

initial begin

// Initialize Inputs

a = 0;

b = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a=0;
b=1;

#100;

a=1;

b=0;

#100;

a=1;

b=1;

#100;

end

endmodule

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