Preparatory Guidebook For Comprehensive Examination: Question Bank Dsda
Preparatory Guidebook For Comprehensive Examination: Question Bank Dsda
QUESTION BANK
DSDA
What is the octal equivalent of the binary number: 10111101 (SPLIT INTO 3 bits each)
(a)675
(b)275
(c) 572
(d) 573.
Digital computers are more widely used as compared to analog computers, because they are
(a) less expensive
(b) always more accurate and faster
(c) useful over wider ranges of problem types
(d) easier to maintain.
Most of the digital computers do not have floating point hardware because
(a) floating point hardware is costly
(b) it is slower than software
(c) it is not possible to perform floating point addition by hardware
(d) of no specific reason.
(1(10101)2 is
(a) (37)10
(b) ( 69)10
(c) (41 )10
(d) — (5)10
16. Among the logic families, the family which can be used at very high frequency greater than
100 MHz in a 4 bit synchronous counter is (ECL > 100, TTL 75, CMOS TTLLS 40)
(a) TTLAS
(b) CMOS
(c) ECL
(d) TTLLS
An OR gate has 6 inputs. The number of input words in its truth table is
(a) 6
(b) 32
(c) 64
(d) 128
A denouncing circuit is
(a) an actable MV
(b) a bistable MV
(c) a latch
(d) a monostable MV.
Assuming 8 bits for data, 1 bit for parity, I start bit and 2 stop bits, the number of characters that
1200 BPS communication line can transmit is
(a)10 CPS
(b)120 CPS
(c) 12CPS
(d) None of the above.
S-R type flip-flop can be converted into D type flip-flop if S is connected to R through
(a) OR gate
(c) inverters
The ‘sum’ output in a half-adder can be realized by using a single two-input gate. which should be
a
(a) exclusive -OR gate
(b) NOR gate
(c) AND gate
(d) OR gate.
In a ripple counter using edge-triggered J-K flip-flops, the pulse input is applied to the
(a) clock input of all flip-flops
(b) clock input of one flip-flop
(c) J and K inputs of one flip-flop
(d) J and K inputs of all flip-flops.
The Boolean function x’ y’ + xy + x’ y is equivalent to
(a) x’+y’
(b) x+y
(c) x+y’
(d) x’+y
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then
it will result in
(a)Q=0,Q’=l
(b)Q=1.Q’=O
(c) Q = 1, Q’ =1
(d) Indeterminate states
When an 8-bit Serial in/Serial out shift register is used for a 24uS time delay, the clock frequency
must be
(a) 41.67 KHz
(b) 333 KHz
(c) 125KHz
(d) 8MHz
The group of bits 101110101 is serially shifted(right most bit first) into an 8-bit parallel output shift
register with an initial state of 11100100.After two clock pulses, the register contains
(a) 01011110
(b) 10110101
(c) 01111001
(d) 00101101
The bit capacity of a memory that has 1024 addresses and store 8 bits at each address is
(a) 1024
(b) 8192
(c) 8
(d) 4096
IC s are
a. analog
b. digital
c. both analog and digital
d. mostly analog
The rate of change of digital signals between High and Low Level is
a. very fast
b. fast
c. slow
d. very slow
Logic pulser
a. generates short duration pulses
b. generate long duration pulses
c. generates long and short duration
d. none of above
What is the output state of an AND gate if the inputs are 0 and 1?
a. a.0
b. b.1
c. c.3
d. d.2
A NOT gate has...
a. Two inputs and one output
b. One input and one output
c. One input and two outputs
d. none of above
An OR gate has...
a. Two inputs and one output
b. One input and one output
c. One input and two outputs
d. none of above
The output of a ____ gate is only 1 when all of its inputs are 1
a. NOR
b. XOR
c. AND
d. NOT
A NAND gate is equivalent to an AND gate plus a .... gate put together.
a. NOR
b. NOT
c. XOR
d. none
A gigabyte represents
a. a.1 billion bytes
b. 1000 kilobytes
c. 230 bytes
d. 1024 bytes
A megabyte represents
a. 1 million bytes
b. 1000 kilobytes
c. 220 bytes
d. 1024 bytes
A parity bit is
a. used to indicate uppercase letters
b. used to detect errors
c. is the first bit in a byte
d. is the last bit in a byte
1111+11111=
a.101111
b.101110
c.111111
d.011111
Binary multiplication 1*0=
a.1
b.0
c.10
d.11
110012 -100012=
a.10000
b.01000
c.00100
d.00001