How Phase Shift, Required Time, and Arrival Time Are Calculated in Report - Timing For A Path in Multiple Clock Domain
How Phase Shift, Required Time, and Arrival Time Are Calculated in Report - Timing For A Path in Multiple Clock Domain
Problem
In the timing report, how does the Common Timing Engine (CTE) calculate the Required Time, Phase Shift, Other End
Arrival Time, and Beginpoint Arrival Time for each of the following four cases:
create_clock -name "CLK1" -add -period 4.0 -waveform {0.0 2.0} [get_ports {clk1}]
create_clock -name "CLK2" -add -period 6.0 -waveform {0.0 3.0} [get_ports {clk2}]
Solution
Phase Shift Calculation
Phase shift is the cycle adjustment performed from the ideal clock edge to reflect when data is to be captured. When the
launch clock and capture clock are in different clock domains, the most restrictive time between edges is used. The
following diagram illustrates how the phase shift is calculated for the clocks defined in the problem statement of this
article.
The following report provides details about how phase shift is calculated for different leading and trailing edge
combinations from CLK1 to CLK2. The leading edge is the first edge defined in the create_clock constraint. The trailing
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edge is the second edge defined. To output a table of the phase shifts, run report_clocks -phase_shift_table:
+------------------------------------------------+
| Clock To Clock Phase Shift (Late) |
|------------------------------------------------|
| From | To | L->L | L->T | T->L | T->T |
|-------+-------+-------+--------+-------+-------|
| CLK1 | CLK1 | 4.000 | 0.000 | 4.000 | 4.000 |
| CLK1 | CLK2 | 2.000 | -2.000 | 4.000 | 0.000 |
| CLK2 | CLK1 | 2.000 | 0.000 | 4.000 | 2.000 |
| CLK2 | CLK2 | 6.000 | 0.000 | 6.000 | 6.000 |
+------------------------------------------------+
Phase Shift Calculation: CLK1 Leading Edge -> CLK2 Leading Edge
The most restrictive cycle time occurs between the leading edge of CLK1 at 4ns and the leading edge of CLK2 at 6ns.
The phase shift here between the leading edges of the launch clock and capture clock is therefore 2ns.
Phase Shift Calculation: CLK1 Leading Edge -> CLK2 Trailing Edge
The most restrictive cycle time occurs between the leading edge of CLK1 at 8ns and the trailing edge of CLK2 at 9ns. To
calculate the phase shift, you must align the leading edges of CLK1 and CLK2 for this cycle. The leading edge of CLK2 is
at 6ns. Therefore, the phase shift is 6ns - 8ns = -2ns.
Phase Shift Calculation: CLK1 Trailing Edge -> CLK2 Leading Edge
The most restrictive cycle time occurs between the trailing edge of CLK1 at 10ns and the leading edge of CLK2 at 12ns.
To calculate the phase shift, you must align the leading edges of CLK1 and CLK2 for this cycle. The leading edge of CLK1
is at 8ns. Therefore, the phase shift is 12ns - 8ns = 4ns.
Phase Shift Calculation: CLK1 Trailing Edge -> CLK2 Trailing Edge
The most restrictive cycle time occurs between the trailing edge of CLK1 at 2ns and the trailing edge of CLK2 at 3ns. To
calculate the phase shift, you must align the leading edges of CLK1 and CLK2 for this cycle. The leading edge of CLK1 is
at 0ns and the leading edge of CLK2 is at 0ns. Therefore, the phase shift is 0ns - 0ns = 0ns.
The Beginpoint Arrival Time is the launch clock edge time relative to the leading edge of the ideal clock waveform.
For example, the ideal clock waveform for CLK1 is a leading edge at 0ns and a trailing edge at 2ns. Therefore, if the
launch clock is the leading edge of CLK1, the Beginpoint Arrival Time is 0ns.
<CMD> report_timing -clock_from CLK1 -edge_from lead -clock_to CLK2 -edge_to lead
...
Endpoint: U3/D (v) checked with leading edge of 'CLK2'
Beginpoint: U1/Q (^) triggered by leading edge of 'CLK1'
...
If the launch clock is the trailing edge of CLK1, the Beginpoint Arrival Time is 2ns because the trailing edge occurs 2ns
from the leading edge of the ideal CLK1 waveform:
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<CMD> report_timing -clock_from CLK1 -edge_from trail -clock_to CLK2 -edge_to lead
...
Endpoint: U12/D (v) checked with leading edge of 'CLK2'
Beginpoint: U10/Q (^) triggered by trailing edge of 'CLK1'
...
If clock latency has been defined (for example, set_clock_latency 0.5 [get_clocks CLK1]), it is added to the
Beginpoint Arrival Time:
<CMD> report_timing -clock_from CLK1 -edge_from trail -clock_to CLK2 -edge_to lead
...
Endpoint: U12/D (v) checked with leading edge of 'CLK2'
Beginpoint: U10/Q (^) triggered by trailing edge of 'CLK1'
...
Clock Fall Edge 2.000
+ Clock Network Latency (Ideal) 0.500 <--- Latency added to Beginpoint
= Beginpoint Arrival Time 2.500
+-------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival | Required |
| | | | | Time | Time |
|----------+-------------+-------+-------+---------+----------|
| U10 | CK ^ | | | 2.500 | 3.388 |
The Other End Arrival Time is calculated in the same manner as the Beginpoint Arrival Time. Use the option -
path_type full_clock to show the capture clock path. For example, if the data is captured at the leading edge of
CLK2, the Other End Arrival Time is 0ns.
<CMD> report_timing -clock_from CLK1 -edge_from lead -clock_to CLK2 -edge_to lead -
path_type full_clock
...
Endpoint: U3/D (v) checked with leading edge of 'CLK2'
Beginpoint: U1/Q (^) triggered by leading edge of 'CLK1'
Other End Arrival Time 0.000
...
If the data is captured at the trailing edge of CLK2, the Other End Arrival Time is 3ns because the trailing edge occurs 3ns
after the leading edge of the ideal waveform of CLK2:
<CMD> report_timing -clock_from CLK1 -edge_from lead -clock_to CLK2 -edge_to trail -
path_type full_clock
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...
Endpoint: U7/D (v) checked with trailing edge of 'CLK2'
Beginpoint: U5/Q (^) triggered by leading edge of 'CLK1'
Other End Arrival Time 3.000
...
Once you have calculated the phase shift, and begin and edge point arrival times, it is straightforward to calculate the
required time to achieve a slack of 0ns. The required time equation is:
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