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(Digitare Qui) (Digitare Qui)

The document describes three VHDL components: 1) An 8-bit multiplexer (mux8bit) that selects between its two 8-bit inputs based on a control signal. 2) An 8-bit ripple carry adder (rca) that adds two 8-bit inputs and outputs a 9-bit sum. 3) A main component that instantiates the mux and adder, using the muxes to select inputs for the adder based on a 2-bit control signal and outputting the final 9-bit sum.

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AlfredoSanto
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43 views4 pages

(Digitare Qui) (Digitare Qui)

The document describes three VHDL components: 1) An 8-bit multiplexer (mux8bit) that selects between its two 8-bit inputs based on a control signal. 2) An 8-bit ripple carry adder (rca) that adds two 8-bit inputs and outputs a 9-bit sum. 3) A main component that instantiates the mux and adder, using the muxes to select inputs for the adder based on a 2-bit control signal and outputting the final 9-bit sum.

Uploaded by

AlfredoSanto
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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[Digitare qui] [Digitare qui]

MultiPlexer:
library IEEE;
use IEEE.std_logic_1164.all;
entity mux8bit is
port(A,B : in std_logic_vector(7 downto 0);
C : std_logic;
O: out std_logic_vector(7 downto 0));
End mux8bit;
Architecture MyMux of mux8bit is
Begin
With C select
O <= A when ‘0’,
B when ‘1’,
“xxxxxxxx” others;
End mymux
[Digitare qui] [Digitare qui]

Sommatore:
Library IEEE;
use IEEE.std_logic_1164.all;
entity rca is
port( D, E : in std_logic_vector(7 downto 0);
O : out std_logic_vector(8 downto 0));
End rca;
Architecture myrca of rca is
signal g,p : std_logic_vector(8 downto 0);
signal c : std_logic_vector(9 downto 0);
Begin
G(7 downto 0)<= d and e;
P(7 downto 0) <= d xor e;
g(8)<=g(7);
p(8)<=p(7);
c(0)<=’0’;
C(8 downto 1) <= g or p and c(8 downto 0);
O <= p xor c(8 downto 0);
End myrca;
[Digitare qui] [Digitare qui]

Main

library IEEE;
use IEEE.std_logic_1164.all;
entity main is
port(A, B : in std_logic_vector(7 downto 0);
C : in std_logic_vector(1 downto 0);
O : out std_logic_vector(8 downto0));
End main
Architecture MyMain o main
Signal d, notd, x, y : std_logic_vector(7 downto 0);
component rca is
port( D, E : in std_logic_vector(7 downto 0);
O : out std_logic_vector(8 downto 0));
End component
Component mymux8bit is
port(A,B : in std_logic_vector(7 downto 0);
C : std_logic;
O: out std_logic_vector(7 downto 0));
End component
Begin
Mux1: mux8bit port map(A,B,C(0),D);
notd<=not d;
mux2: mux8bit port map(d,notd,c(1),x);
mux3: mux8bit port map(“00000001”, “00000100”,c(1), y);
sum: rca port map(x,y,o);
End mymain
[Digitare qui] [Digitare qui]

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