Block Diagram Codec TLV320AIC3
Block Diagram Codec TLV320AIC3
Block Diagram Codec TLV320AIC3
DOUT
BCLK
DIN
4 5 2 3
TLV320AIC3104 Functional Block Diagram with Registers
All Output gains
All Output Volume gains HPLOUT Volume Are Positive in 1 dB steps
Sample Rate Select : (R2)
are in 0.5dB steps (0 to -78dB)
Codec Data Path Setup: (R7)
Audio Serial Data Interface Ctrl: (R8-R10 DAC_L1 Gain:
(R47) 0 to 9 dB
DAC_R1 (R50)
PGA_L (R46)
+
To enable Record-Only Digital Audio Processing PGA_R (R49) 19 HPLOUT
(shown with SW-Dx): DAC_L2 (R51)
1. Power Down Both DACs* (R37) All Register Numbers are in Decimal
Audio Serial Bus Interface and in Page 0 Unless Otherwise Noted
Left AGC control:
2. Enable ADC Digital Processing (R107)
(R26-R28, R32, R34, 3. 3-D Processing is not available in Record Mode
R103-R104) *DACs must be powered down in order to use ADC processing HPLCO M Volume
DOUTR
MIC2L
DOUTL
MIC2L/LINE2L/MICDET 14 (R37) Gain:
(0 to -78dB) HPLCOM
DINR
DINL
Gain: (R17, 0 to 9 dB
0 to -12 dB R18) DAC_L1 Drive Ctrl
(R54)
(R107-D3) (R43) DAC_R1 (R37)
1.5dB steps AGC (R57)
Gain: PGA_L (R53) + 20 HPLCOM
Volume PGA_R (R58)
0 to -63.5 dB (R56)
SW-D2 Control VCM
0.5dB steps
Bypass (R12-D3) Bypass (R12-D2)
(R8-D2) DAC_L1
PGA 1st 0 DAC (R37)
MIC1LP / LINE1LP 10 1st Ord DAC_L2 HPRCOM Volume Gain:
MIC1L + 0/59.5dB ADC Order 1 LB1 LB2 deemp
0 (0 to -78dB) 0 to 9 dB HPRCOM
MIC1LM / LINE1LM 11 L DAC_L3
Gain: (R19, 0.5dB steps L HP
SW-D1
1
DAC_L1 (R68) VCM Drive Ctrl
0 to -12 dB R24) Filter P1:R1-R6, P1:R7-R12,
(P1:R16-R21) (R41) DAC_R1 (R71) (R38)
R13-R16 R17-R20
1.5dB steps
(R15) (R12, D6-7) (R8-D2) PGA_L (R67) + 22 HPRCOM
(R107,D7) Normal Left Channel Processing PGA_R
(R70) (R72)
(P1:R65-R70)
PGA_L
BCLK
17 26 25 18 24 21 32 7 6 15 1 31 8 9
IOVDD
MICBIAS
DRVDD
DRVDD
Reset
MCLK
DVDD
AVSS1
AVSS2
SCL
SDA
DRVSS
AVDD
DVSS