Scribd
Upload
38 views4 pages

VHDL

VHDL

Uploaded by

Josip Troha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
38 views4 pages

VHDL

VHDL

Uploaded by

Josip Troha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
You are on page 1/ 4

-----------------------------------------------------------------------------

-----
-- Company:
-- Engineer:
--
-- Create Date: 09:04:49 01/07/2019
-- Design Name:
-- Module Name: Stopwatch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------------
-----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Stopwatch is
generic(clockfreq : integer := 100000000);
port(
clk: in std_logic;
sw : in std_logic_vector(2 downto 0);
an : out std_logic_vector(3 downto 0) := "1111";
seg: out std_logic_vector(7 downto 0);
led: out std_logic_vector(4 downto 0));
end Stopwatch;
-----------------------------------------------------
ARCHITECTURE Behavioral OF Stopwatch IS
signal sek1 :integer;
signal sek2 :integer;
signal min :integer;
signal seg_sek1 : std_logic_vector(7 downto 0) := "11111111";
signal seg_sek2 : std_logic_vector(7 downto 0) := "11111111";
signal led_min : std_logic_vector(4 downto 0) := "00000";
signal start : std_logic := '0';
signal stop : std_logic := '0';
signal reset : std_logic := '0';
signal clk_brojac : integer := 0;
signal sek_freq : integer := clockfreq/100000000;
signal m_clk : std_logic := '0';
signal counter : integer := 0;
signal en : std_logic := '1';
-------------------------------------------------------
begin
sek_freq <= 1;
-------------------------------------------------------
process(clk)
begin
if(clk' event and clk='1') then
if (clk_brojac = sek_freq) then
clk_brojac <= 0;
m_clk <= '1';
else
clk_brojac <= clk_brojac + 1;
m_clk <= '0';
end if;
end if;
end process;
--------------------------------------------------------
process(m_clk,reset,en)
begin
if (reset = '1') then
sek1 <= 0;
sek2 <= 0;
min <= 0;

elsif(m_clk' event and m_clk = '1') then


if(en = '1') then
if(sek1 = 9) then
sek1 <= 0;
sek2 <= sek2+1;

if(sek2 = 5) then
sek2 <= 0;
min <= min+1;
else
sek2 <= sek2+1;
end if;
else
sek1 <= sek1+1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------
with sek1 select
seg_sek1 <=
"11000000" when 0,
"11111001" when 1,
"10100100" when 2,
"10110000" when 3,
"10011001" when 4,
"10010010" when 5,
"10000010" when 6,
"11111000" when 7,
"10000000" when 8,
"10010000" when 9,
"10000110" WHEN OTHERS;

with sek2 select


seg_sek2 <=
"11000000" when 0,
"11111001" when 1,
"10100100" when 2,
"10110000" when 3,
"10011001" when 4,
"10010010" when 5,
"10000010" when 6,
"11111000" when 7,
"10000000" when 8,
"10010000" when 9,
"10000110" WHEN OTHERS;

with min select


led_min <=
"00000" when 0,
"00001" when 1,
"00011" when 2,
"00111" when 3,
"01111" when 4,
"11111" when 5,
"11111" when others;
----------------------------------------------------
process(clk)
begin
if(clk' event and clk='1') then
counter <= counter + 1;

if(counter > 0 and counter < 10) then


seg <= seg_sek1;
an <= "1110";
elsif (counter > 9 and counter < 15) then
seg <= seg_sek2;
an <= "1101";
elsif (counter > 14) then
counter <= 1;
else
an <= "1111";
seg <= "11111111";
end if;
end if;
end process;
------------------------------------------------------------
process (clk)
begin

if (clk' event and clk = '1') then


if (start = '1' and stop = '0') then
en <= '1';
elsif (stop = '1' and start = '0') then
en <= '0';
else
en <= en;
end if;
end if;
end process;
------------------------------------------------------------
led <= led_min;
start <= sw(0);
stop <= sw(1);
reset <= sw(2);
--------------------------------------------------------------
end Behavioral;

You might also like