Creating Value Through Test

Erik Jan Marinissen1 Bart Vermeulen1 Robert Madge2 Michael Kessler3 Michael Müller3
1Philips Research Laboratories 2 3
LSI Logic Corp. IBM Deutschland Entwicklung GmbH
IC Design – Digital Design & Test Product Engineering Hardware Development
Prof. Holstlaan 4 – WAY-41 23400 N.E. Glisan Street Schönaicherstrasse 220
5656 AA Eindhoven Gresham, OR 71032 Böblingen
The Netherlands United States of America Germany
[email protected] [email protected] [email protected]
[email protected] [email protected]

Abstract
Test is often seen as a necessary evil; it is a fact of life that ICs have manufacturing defects and those need to be filtered out by testing
before the ICs are shipped to the customer. In this paper, we show that techniques and tools used in the testing field can also be
(re-)used to create value to (1) designers, (2) manufacturers, and (3) customers alike. First, we show how the test infrastructure can
be used to detect, diagnose, and correct design errors in prototype silicon. Secondly, we discuss how test results are used to improve
the manufacturing process and hence production yield. Finally, we present test technologies that enable systems of high reliability
for safety-critical applications.

1 Value for IC Designers: Silicon Debug

Bart Vermeulen – Philips Research Laboratories
For today’s system chip designs, no designer can guarantee that all de- state dumps of flip flop and memory content while the chip is in the
sign errors are found before first tape-out, despite meticulous analysis application. This method is so popular because the scan chains allow
and verification [1, 2]. These errors can go undetected because the ver- observability of the chip’s full state, while minimizing the amount of
ification methods are only applied to an abstract model of the IC and additional hardware required to implement this functionality, provided
not to the actual silicon. When more detail is added to the IC model (to that design-for-test has already been implemented.
better match it to the reality), most verification methods can no longer
Below, a generic debug methodology is described that utilizes scan
be applied exhaustively because of the computational cost involved.
chains for silicon debug [3]. This debug methodology consists of two
Given that design teams are under continued time-to-market pressure,
steps. First, certain Design-for-Debug (DfD) structures are added dur-
it is important to find design errors quickly. Apart from improving the
ing the design phase of a chip. Second, debugger software that executes
pre-silicon verification methods, it is worthwhile to improve existing
on a computer connected to the application board, is used to debug the
silicon debug methods and complement them with other approaches.
chip. The debugger software is used to control the chip and its debug
Debugging silicon is difficult because the engineer’s ability to observe hardware in the application.
the chip’s internal processes (e.g., states and data flow) is limited. We
can identify two traditional approaches to diagnose faulty behavior of
a chip in the application. First there are diagnosis methods such as vi-
1.1 Scan-Based Silicon Debug
sual inspection (e.g., electron-beam probing) and direct physical con- A scan-based silicon debug methodology is based on re-using scan
tact techniques (e.g., using probe needles). A drawback of these meth- chains, inserted for manufacturing test, to analyze design errors. To
ods is that it is often difficult to pin-point the exact location of an error allow access to the scan chains in the application, certain modifica-
in the chip without additional information. To examine the entire lay- tions need to be made to the design. Figure 1 gives an overview of an
out of a design for a possible error cause using only visual inspection architecture that allows this access. Please note that only two cores are
is clearly not feasible. In addition, with decreasing feature sizes and shown for clarity. This architecture can be easily extended to cover any
an increasing number of metal layers in modern process technologies, number of cores.
the usage of these debugging techniques is becoming more difficult. All debug operations are controlled from the IEEE Std. 1149.1 Test
A second method involves manual and ad-hoc debug techniques, such Acces Port (TAP) controller. The advantage of using this controller for
as trial-and-error programming of the chip. Although these techniques debug is that the TAP controller and its associated pins (1) have often
can help to provide information on the type of design error and its loca- already been included in the design to allow for board-level manufac-
tion, they are often unpredictable in both success rate and time required turing test, (2) are easy to access when the chip is put on its application
to sufficiently localize a design error. board, and (3) are themselves not used by the application.
One other method is to provide electrical observability of on-chip sig- The IEEE Std. 1149.1 TAP is essentially a serial port, with one serial
nals through the device pins. The most popular application of this input (TDI) and one serial output ( TDO). In Figure 1, all debug func-
method involves reusing the scan chains already inserted in the de- tionality is therefore controlled from one or more serial debug control
sign for manufacturing test. These scan chains are used to provide blocks (DCB). These DCBs are under control of the test hardware, to

1530-1591/03 $17.00  2003 IEEE

allow them to be fully tested during manufacturing test and to control stop the chip at a different point in time to obtain more debug infor-
them from the TAP controller. mation. Ultimately this should help the user to diagnose the design
error. Figure 2 shows the debug flow in which state dumps are used to
TDI TRSTn TMS TCK TDO
analyze a design error.
TAP Controller
Start

CC-DCB Power-on Reset

clock generator

Program Breakpoint

BP-DCB BP-DCB Functional reset

Breakpoint hit?
N
core 1 core 2 Y

AC-DCB AC-DCB Create state dump

TCB TCB
IC Done?
N
Y
Figure 1: Scan-based silicon debug architecture. End

The architecture in Figure 1 implements the “ABC” of scan-based sil- Figure 2: Flow used for scan-based silicon debug.
icon debug; Access to the scan chains, Breakpoints to detect one or
more internal events, and Clock control. These are explained below. Clock Control
Access The chip is stopped by gating the on-chip clocks. Stopping the clocks
The scan chains are controlled via dedicated TAP data registers. One effectively freezes the content of all flip flops and embedded memo-
clock domain is scanned out at a time, as the TAP has only one serial ries. After the clocks have stopped, the circuit can be safely switched
output. In debug mode, the scannable flip flops are concatenated into to debug scan mode. In debug scan mode, each internal clock is se-
debug scan probes, one in each clock domain. This concatenation is lected in turn to allow the content of the corresponding scan probe to
performed at core-level using a debug shell, shown in gray in Figure 1. be scanned out. The stop and re-activation functions for the internal
The debug shell hides all core-specific details, such as number of scan clocks for scan chain shifting are added to the on-chip clock genera-
chains and clock domains inside the core, and provides a single, uni- tion unit and controlled from a Clock Control DCB.
form hardware interface for debug at the integration level. Each core The scan-based silicon debug architecture presented above uses scal-
provides one serial input and one serial output to its debug scan probes, able modules to implement the required silicon debug functionality.
and a standardized debug interface to an Access Control Debug Con- These modules are added to each of the submodules in the design, al-
trol Block (AC-DCB), that controls the scan probe multiplexing. At lowing a core-based design, test, and debug methodology to be fol-
the integration level, all serial inputs and outputs are daisy-chained. lowed. The advantage of this is that the debug architecture can be
During a silicon debug session, the AC-DCB is used to select each completely tailored to suit a particular design. As an example, a de-
core-level scan probe in turn, while its input and output are connected sign may contain cores with a different number of scan chains and/or
to the chip’s TDI and TDO pins. To the user this complexity in access- clock domains. The debug shell hides these test-details by providing
ing the various scan probes is hidden. The debugger software takes one core-level debug interface. Each of these cores has the same debug
care of issuing the proper TAP commands to select each probe in turn, interface, allowing a design-for-debug tool to automatically perform
and translating the bit-streams received on the chip’s TDO output to the core interconnect at integration level. This reduces the time re-
individual flip flop, multi-bit register, and memory content. quired for a designer to add design-for-debug hardware to a design. In
addition, because of the scalable nature of the debug architecture, an
Breakpoints estimation tool can be used to make an educated trade-off between for
To examine the behavior of the chip in detail using state dumps, it is example breakpoint granularity and hardware cost.
required to first determine at which point during the chip’s execution a
state dump has to be made. An on-chip breakpoint mechanism is added
to the design to allow the chip to be stopped at regular intervals during 1.2 Silicon Debug Successes
its execution. This regularity is important, as it allows the state dumps This debug methodology has been successfully applied to a number of
to provide a clear insight in the data and control processing going on in- large digital system chips within Philips.
side the chip over time. If the breakpoint mechanism does not provide
The debug facilities on the CPA chip [4] proved essential in verify-
enough temporal resolution, the ‘blind spots’ in between state dumps,
ing its video-processing capabilities. The first silicon exhibited several
where no information can be obtained, might seriously complicate and
problems during initialization, causing the chip to malfunction after 50
lengthen the debug process.
to 75 video frames. The source of the problems was detected by exam-
During a silicon debug session, the breakpoint mechanism is pro- ining scan dumps taken at each cycle during the initialization sequence.
grammed via a Breakpoint DCB to stop the chip at a certain point in Using the debug controllability, we replaced the faulty ROM-based ini-
time. After stopping, a scan dump via the TAP is made and compared tialization code by loading corrected code into an external SDRAM and
to golden reference data. Based on this comparison, the end user can instructing the chip to fetch its code from that SDRAM. After this fix,
use the debugger software to re-program the breakpoint mechanism to the designers could successfully verify all image processing functions
without further silicon spins.
For the PNX8525/Viper chip [5], and more recently for the within Philips.
PNX7100/Chrysalis chip, the state dumping functionality allowed de-
signers to correctly diagnose the faulty behavior of subcomponents. In
one case, the flow shown in Figure 2 was repeatedly used to back-track 1.3 Conclusion
mismatches between simulation states and silicon states back to the The presented debug methodology successfully relies on the existing
output of a single gate. Under specific circumstances, the output of scan chain access to debug prototype silicon. With only little extra
this gate was not able to drive an internal signal to the correct value in hardware to create debug access, breakpoints, and clock control, it be-
time, which ultimately resulted in erroneous behavior. Once this was comes possible to obtain state dumps while the chip is in its applica-
discovered, the fix was easy to implement and verify. tion. These state dumps provide the debug engineer with essential in-
As a result of these successes, a standardization activity is currently on- formation to locate design errors still left in the chip, and overall help
going to make this debug methodology available to all digital designs to reduce the number of silicon spins and time-to-market of the chip.

2 Value for Manufacturing: Understanding Defects and Improving Yield

Robert Madge – LSI Logic Corporation
The increasing complexity of fabrication processes and the prolifera- loss on ASICs with embedded memory, and was resolved by reducing
tion of foundry fabs has resulted in significant challenges to achieve the oxygen content of the incoming silicon. This problem could not
competitive yield at the introduction of new technologies and for fast have been identified without the raw IDDQ data. Figure 4 shows an
ramp to volume manufacturing. Time-to-market and quality goals are across-wafer variation of minimum working voltage for a 1.8 V func-
increasingly hard to meet due to the growing product complexity and tional core. Even though the core is not failing at the test voltage of
gate count. This section highlights the immense added value of test 1.8 V, the raw data identified a marginality caused by a process de-
data in attempts to overcome these challenges and meet the market and fect. Early identification and fix of this defect was critical to the yield
profitability requirements. learning for this product.

2.1 Process Yield Improvement

Process and yield engineers have traditionally relied on the pass/fail
‘bin’ data from wafer sort and package testing to monitor the capabil-
ity of their process technology and to improve the defect density and
parametric performance. Bit fail signature data has long been a yield
improvement method for discrete and embedded memory manufactur-
ers [6, 7, 8], but for logic products, raw test data has recently become
a critical part of the yield engineer’s tool set. This has significantly
increased the added value of testing to the manufacturing world.

Figure 4: Intrinsic minimum voltage variation across the wafer.

2.2 Quality and Reliability Improvement

Quality and reliability engineers are also utilizing raw test signatures,
particularly IDDQ (Figure 5) and Min-VDD (Figure 6), to understand
the latent defectivity of the silicon process and the potential for quality
and reliability improvements by screening die with abnormal signa-
tures (or statistical outliers) [9, 10]. The more recent trend is to utilize
the raw test results to predict the intrinsic (defect-free) behavior based
Figure 3: A bi-modal IDDQ distribution due to silicon ingot defects. on neighborhood or deltas and reduce the variance such that defective
outliers can be clearly identified and eliminated for quality improve-
Figures 3 and 4 show examples of how raw ATE data is analyzed for ment [11]. Statistical post-processing methods have been developed
yield learning and process improvement. In Figure 3, IDDQ data is which move the pass/fail decision making step from on-tester to off-
shown to have a bi-model distribution, even though only a small per- tester (see Figure 7). This allows much improved identification of the
centage fail the test limit. The cause of the bi-modal behavior was gate outlier die and has been shown to result in 40–60% improvements in
oxide defects due to incoming silicon stacking faults from one silicon Early Fail Rate (EFR) and customer-return Defects-Per-Million (DPM)
vendor causing 5–10% yield loss on logic ASICs and 50–60% yield [12, 13].
 2.3 Failure Analysis
Failure analysis continues to provide immense value to the yield ramp
and quality and reliability improvement. Test data is contributing
significantly to this continued success through mapping of defects
to structural test datalogs such as scan or IDDQ to in-line defects
[14, 15, 16]. Figure 8 shows how the ATE failure datalog is combined
with the design files to identify the failing nets and isolate the defect
causing the failure. The defect cause in this case was a metal bridge,
which would be almost impossible to identify using traditional failure
analysis techniques.

Figure 5: IDDQ data from two silicon lots from the same process. Note
outlier die from both lots which cannot be efficiently screened with the
on-tester limit.

Figure 8: A bridging defect identified by the scan datalog diagnosis method.

Figure 6: Min-VDD vs. device speed for two different lots, clearly
showing Min-VDD outliers and lot-to-lot intrinsic variation. 2.4 Test Cost Reduction/Adaptive Testing
Test engineers have always utilized raw test data to isolate correlation
or repeatability issues in the test program or hardware. Recent trends,
however, have been towards collection and analysis of large volumes of
test data over longer periods of time. Test times can be reduced through
elimination of unnecessary or redundant tests or vectors and adaptive
test methods can be introduced where the results of certain tests can
determine the need for more extensive testing based on probability of
failure. More recent trends towards foundry wafer manufacturing has
led to the importance of adaptive testing due to the potentially variable
quality of silicon coming from the fabs. Test time improvements of
26% have been reported with adaptive test methods while also improv-
ing product quality [17].

2.5 Conclusion
ATE testing and the raw data results provide ever-increasing value in
the manufacturing of complex integrated circuits. No longer are the
raw data results ignored in favor of pass/fail ‘bin’ results, rather the
results are a critical part of the yield learning, quality and reliability
Figure 7: Statistical Post-Processing (SPP) data flow showing the use improvement and cost reduction process in all areas of manufacturing
of raw parametric ATE data in off-tester pass/fail decision making and and process or product development.
inkless re-binning.

3 Value for End Customers: Highly Reliable Systems

Michael Kessler & Michael Müller – IBM Deutschland
The heart of a zSeries 900 system (S/390) consists of a Multi-Chip clock distribution. The test techniques were developed and improved
Module (MCM) and a number of surrounding support chips and units. from generation to generation to fulfill the quality expectations of the
The 2000 design generation MCM, operating at 1 GHz, contains 20 customers. Business customers with mission-critical applications are
Central Processors (CP), 2 Cache Controllers (SCC), 8 Cache Chips highly dependent on the premium quality and reliability of the ma-
(SCD), 4 Memory Bus Adapters (MBA), and a Clock Chip (CLK) for chine, 365 days a year, 24 hours a day.
The goal is to minimize all possibilities for malfunction and to im- 3.2 Usage of Built-in Test Equipment in the Field
prove reliability by removing all early life problems by stressing the
components and the complete system. You also want to be cost effec-
tive overall (from wafer to system) by generating highest quality. This The zSeries z900 is an example of a system which uses instantaneous
is not a contradiction, but a necessary prerequisite. error detection on each CPU and on each I/O operation while the sys-
tem is executing the customer’s workload. Instantaneous detection is
Many components are necessary, to guarantee the reliability targets the detection of an error in the ongoing operation prior to committing
for such a machine. First of all, perfection is needed during testing the result to any other functional unit [21]. All arrays (L1-I-Cache,
and stressing before shipment. From the system view a consequent L1-D-Cache, TLB, BHT, L2-Cache, L3-Memory) and all buses use
system design for Reliability, Availability and Serviceability (RAS) error-correcting codes to detect and correct errors. The state machines
is necessary, which includes redundancy, no Single Point of Failure are implemented with redundancy in the state encoding, invalid state-
(SPOF), fault-tolerance, recoverability, traceability, and diagnosability detection, and sequence checking. The checking in the PU chips for
after shipment. example is implemented by duplicating the Execution Units (Instruc-
tion Unit, Floating-Point Unit, Fixed-Point Unit) and performing a re-
3.1 Testing and Stressing sult compare before committing the result to the self-checked Recovery
Unit (R-Unit) [22].
Design-for-Test
The base for test is a structural test approach of the silicon with highest Usage of LBIST/ABIST for Maintenance
possible DC and AC fault coverage. Logic Built-In Self Test (LBIST) At system power-on or whenever new hardware, either for upgrade or
and Array BIST (ABIST) are perfectly suitable for the following rea- repair, is added to the system, the LBIST and ABIST are executed to
sons. The tester resource requirements are minimal. Only initializa- ensure the new hardware including the instantaneous error detection
tion and measurement of the pre-calculated signature are necessary. circuitry is working before the component joins the configuration. The
The LBIST can be applied at-speed and beyond (for margin testing) server executes ABIST to find failures in the large arrays and repairs
through on-chip clock generators. The LBIST is capable of applying the failure using an extension to the fuse-programmable array-line-
pseudo-random and programmable weighted pseudo-random patterns. relocate method used in manufacturing to increase the yield. In the
The design is made random testable for highest possible test coverage, rare case of larger damage, when the failure cannot be self-healed, sin-
e.g., “99% AC test coverage using LBIST only” [18]. The test time is gle array lines, quadrants of the large arrays, and up to complete chips
kept low, by means of the STUMPS architecture [19] with many short can be de-configured to allow for an emergency operation in degraded
STUMPS channels. mode, until the scheduled repair can be performed at the customer’s
convenience.
Test
The LBIST/ABIST are applied through several packaging levels from Error Reporting, Containment, Recovery
wafer, to single chip, to MCM, to the various system configurations There are two major error-reporting-methods in the z900 system. For
and during power-on at the customer site. It is also used for BurnIn ‘clock-running’ errors, used for less severe errors where the unit con-
and RunIn at chip-level and system-level. The wafer test is applied tinues to function through the error, the reporting is done in-band. For
through a Reduced-Pin-Count tester interface and consists of paramet- ‘clock-stop’ errors, used for severe errors, where the unit is no longer
ric tests, Flush/Scan, LBIST/ABIST, and supplemental stored patterns. functioning, the reporting is done out-of-band to the service subsystem
The single-chip test uses the same tests again plus the external I/O tests. by scanning out the SRL chain. In both cases the error information is
MCM test reuses the LBIST/ABISTs and at-speed interconnect tests. collected to determine the amount of damage, to trigger the appropriate
recovery, and to perform fault isolation. The error information together
Above tests are applied to guarantee functionality at all voltage, tem- with the result of the recovery is stored as First-Failure-Data-Capture
perature, pattern, and cycle time corners. LBIST/ABISTs are used as (FFDC). The information collected from the detection circuitry identi-
sorting criteria together with other speed indicators. fies the offending unit and the scope of the error.
Due to the nature of semiconductor chips, the difference between worst Recovery is attempted and will be successful in case of a transient fault.
case (slow) and best case (fast) is fairly high. During wafer and single- If the error is caused by a frequently occurring intermittent fault and
chip test, the Flush-Delay through a Shift-Register-Latch (SRL) chain thus exceeds a certain threshold, it is considered permanent [23]. For
is used as speed indicator. A Performance-Screening-Ring-Oscilator a permanent fault recovery will activate an alternate path, a spare el-
(PSRO) could be used as well. A given chip must not only fulfill its ement, or, if none available, inform the operating system about the
raw flat cycle time limit (e.g., 1 GHz), but must perform according to its exact point of interruption and the precise amount of damage to the
predicted cycle time calculated from its own Flush-Delay [20]. Chips interrupted operation. This allows the operating system to associate
that perform outside of a narrow performance distribution are not put the failure with the impacted application and preserve the unaffected
into a slower sort bucket, but get discarded. Any outliers get removed, applications.
they are suspect to fail in the future. Tests are applied at very low and
at very high voltages (outside of the functional window) to accelerate Fault Isolation and Repair
and detect certain fault behaviors. The captured failure data allow effective automatic isolation down to
the Field Replaceable Unit (FRU). The server generates a call-home
BurnIn, RunIn to the maintenance provider that includes the failed FRU, the current
LBIST/ABIST is used to operate the chips at elevated temperatures and system status, FFDC, and the scope of the repair action, such that the
voltages to accelerate any early-life failures that do not cause failures service personnel can schedule the repair at a convenient point in time
initially, but later (possibly in the customer’s application) so-called ‘re- with the customer. The service personnel does not need to run any di-
liability failures’. RunIn is used to stress the chips at and beyond the agnostics to reproduce the failure, but has the spare part right at hand to
target cycle time, again to improve the reliability. Later, after assembly replace the defective part in a concurrent repair on-line. This reduces
of the machine, extended stress tests use again LBIST/ABISTs.
the repair time dramatically. designated spare, which begins a “self-initiated brain transplant”. The
spare has then the identity of the clock-stopped PU and resumes ex-
DRAM Sparing and Cache Line Relocate
ecution where the failed PU left off by retrying the same instruction
Accumulation of soft-errors in seldom accessed storage can be avoided
[21]. Dynamic CPU sparing permits the system to be restored to full
by continuously scrubbing the complete storage to correct single bit
capacity in less than a second as opposed to hours.
errors. Scrubbing uses the error syndrome to count the errors in each
DRAM module. When the count of errors exceeds a specified thresh-
old, a spare DRAM module is activated. The content of the faulty 3.3 Conclusion
module is copied into the spare module. Any store operation stores the Built-in test equipment identifies defect chips. In combination with
data in both modules. When copying is completed, the faulty module BurnIn, RunIn, and stress tests with higher guard-band conditions, it
is replaced by the spare module. The self-repair using a spare DRAM sorts out even potentially defect chips. Removing these chips as early
avoids downtime for memory card replacement [21]. Similar moni- as possible in the production cycle minimizes overall costs from pro-
toring is applied to the large caches. When a cache line exceeds a duction to warranty and service and furthermore protects the customer
certain threshold for single-bit error-correction-events, the cache line from outages. Since the BISTs clearly separate technology and man-
is marked unusable and scheduled for relocation to a spare cache line ufacturing failures from logic design flaws it speeds up bring-up, ties
at the next power-on [24]. less capital to bring-up hardware and improves time-to-market. Check-
CPU Instruction Recovery and Sparing ing logic protects integrity of customer data, identifies the fault of a unit
The failing current instruction is retried when the R-Unit detects a mis- and is thus the base for error containment, transparent recovery, activa-
match, using the correct committed results of the previous instructions tion of alternate paths and spare parts to maximize system availability,
contained in the R-Unit. The PU chip is fenced and its clocks are to completely avoid repair or at least defer to scheduled repair. The
stopped in case retry was not successful. The clock-stop event trig- data collected at the first occurance of a failure lay the foundation for
gers the Service Subsystem of the z900 server to scan out the R-Unit automatic fault isolation down to the field replaceable unit, instead of
SRL chain. This last valid checkpoint is sent to the remaining host PUs relying on failure reproduction through diagnostics, and to call-home
which determine the target spare. The R-Unit contents is passed to the for the correct spare part in order to reduce the repair time and cost.

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