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ADS58J63
SBAS717A – JUNE 2015 – REVISED JUNE 2015
ADS58J63 Quad-Channel, 14-Bit, 500-MSPS Telecom Receiver Device

1 Features 3 Description
•
1 Quad Channel The ADS58J63 is a low-power, wide-bandwidth, 14-
bit, 500-MSPS, quad-channel, telecom receiver
• 14-Bit Resolution device. The ADS58J63 supports a JESD204B serial
• Maximum Clock Rate: 500 MSPS interface with data rates up to 10 Gbps with one lane
• Input Bandwidth (3 dB): 900 MHz per channel. The buffered analog input provides
• On-Chip Dither uniform input impedance across a wide frequency
range and minimizes sample-and-hold glitch energy.
• Analog Input Buffer with High-Impedance Input The ADS58J63 provides excellent spurious-free
• Output Options: dynamic range (SFDR) over a large input frequency
– Rx: Decimate-by-2 and -4 Options with Low- range with very low power consumption. The digital
Pass Filter signal processing block includes complex mixers
followed by low-pass filters with decimate-by-2 and -4
– 200-MHz Complex Bandwidth or 100-MHz options supporting up to 200-MHz receive bandwidth.
Real Bandwidth Support The ADS58J63 also supports a 14-bit, 500-MSPS
– DPD FB: Burst Mode with 14-Bit Output output in burst-mode making the device suitable for a
• 1.9-VPP Differential Full-Scale Input DPD observation receiver.
• JESD204B Interface: The JESD204B interface reduces the number of
interface lines, thus allowing high system integration
– Subclass 1 Support
density. An internal phase locked loop (PLL)
– 1 Lane per ADC Up to 10 Gbps multiplies the incoming analog-to-digital converter
– Dedicated SYNC pin for pair of channels (ADC) sampling clock to derive the bit clock, which is
• Support for Multi-Chip Synchronization used to serialize the 14-bit data from each channel.
• 72-Pin VQFN Package (10 mm × 10 mm) Device Information(1)
• Key Specifications: PART NUMBER PACKAGE BODY SIZE (NOM)
– Power Dissipation: 675 mW/ch ADS58J63 VQFN (72) 10.00 mm x 10.00 mm
– Spectral Performance (Un-decimated) (1) For all available packages, see the orderable addendum at
– fIN = 190 MHz IF at –1 dBFS: the end of the data sheet.
– SNR: 70.4 dBFS

– NSD: –154.4 dBFS/Hz Simplified Block Diagram
– SFDR: 86 dBc (HD2, HD3), 14bit
Digital Block 2x
INAP/M Interleaving DAP/M
95 dBFS (non HD2, HD3) ADC
Correction
FS/4
4x
JESD204B
– fIN = 370 MHz IF at –3 dBFS: INBP/M

14bit
Digital Block
Interleaving
K*FS/16
2x
FS/8
DBP/M
ADC
Correction Burst Mode
– SNR: 68.5 dBFS TRIGAB
– NSD: –152.5 dBFS/Hz TRIGCD
TRDYAB
– SFDR: 81 dBc (HD2, HD3), SYSREFP/M
TRDYCD
86 dBFS (non HD2, HD3) PLL SYNCbAB

CLKINP/M
x10/x20
SYNCbCD
2 Applications 14bit
Digital Block Burst Mode
INCP/M Interleaving DCP/M
ADC
• Multi-Carrier GSM Cellular Infrastructure Base Correction
FS/4
2x
JESD204B
Stations INDP/M
14bit
Digital Block
Interleaving
4x
DDP/M
ADC 2x
Correction K*FS/16
• Multi-Carrier Multi-Mode Cellular Infrastructure FS/8
Configuration
Base Stations Registers
• Telecommunications Receiver
SDIN
SDOUT
SEN
SCAN_EN
SCLK
RESET
• Telecom DPD Observation Receiver
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS58J63
SBAS717A – JUNE 2015 – REVISED JUNE 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.2 Functional Block Diagram ....................................... 21
2 Applications ........................................................... 1 7.3 Feature Description................................................. 22
3 Description ............................................................. 1 7.4 Device Functional Modes........................................ 23
7.5 Programming .......................................................... 34
4 Revision History..................................................... 2
7.6 Register Maps ......................................................... 45
5 Pin Configuration and Functions ......................... 3
8 Application and Implementation ........................ 71
6 Specifications......................................................... 5
8.1 Application Information............................................ 71
6.1 Absolute Maximum Ratings ...................................... 5
8.2 Typical Application .................................................. 75
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5 9 Power Supply Recommendations...................... 76
6.4 Thermal Information .................................................. 6 10 Layout................................................................... 77
6.5 Electrical Characteristics........................................... 6 10.1 Layout Guidelines ................................................. 77
6.6 AC Performance ...................................................... 7 10.2 Layout Example .................................................... 77
6.7 Digital Characteristics ............................................. 10 11 Device and Documentation Support ................. 78
6.8 Timing Characteristics............................................. 11 11.1 Community Resources.......................................... 78
6.9 Typical Characteristics: 14-Bit Burst Mode ............. 12 11.2 Trademarks ........................................................... 78
6.10 Typical Characteristics: Mode 2............................ 19 11.3 Electrostatic Discharge Caution ............................ 78
6.11 Typical Characteristics: Mode 0............................ 20 11.4 Glossary ................................................................ 78
7 Detailed Description ............................................ 21 12 Mechanical, Packaging, and Orderable
7.1 Overview ................................................................. 21 Information ........................................................... 78
4 Revision History
Changes from Original (June 2015) to Revision A Page
• Changed From Product Preview To Production datasheet ................................................................................................... 1
2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ADS58J63

ADS58J63
www.ti.com SBAS717A – JUNE 2015 – REVISED JUNE 2015
5 Pin Configuration and Functions
RMP Package
VQFN-72
Top View
SYNCbCDM
SYNCbABM
SYNCbCDP
SYNCbABP
IOVDD
IOVDD
IOVDD
DGND
DGND
DGND
DDM
DCM
DBM
DAM
DDP
DCP
DBP
DAP
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
TRDYCD 1 54 TRDYAB
TRIGCD 2 53 TRIGAB
DGND 3 52 DGND
IOVDD 4 51 IOVDD
SDIN 5 50 PDN
SCLK 6 49 RES
SEN 7 48 RESET
DVDD 8 47 DVDD
AVDD 9 46 AVDD
AVDD3V 10
ADS58J63 45 AVDD3V
SDOUT 11 44 AVDD
GND PAD (backside)
AVDD 12 43 AVDD
INDP 13 42 INAP
INDM 14 41 INAM
AVDD 15 40 AVDD
AVDD3V 16 39 AVDD3V
AVDD 17 38 AVDD
INCM 18 37 INBM
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
INCP
AVDD
AGND
NC
NC
AVDD
INBP
AVDD3V
AVDD
AGND
CLKINP
CLKINM
AGND
AVDD
AVDD3V
AGND
SYSREFP
SYSREFM
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3

ADS58J63
Pin Functions
PIN
I/O DESCRIPTION
NAME NUMBER
INPUT/REFERENCE
INAP/M 42, 41 I Differential analog input for channel A
INBP/M 36, 37 I Differential analog input for channel B
INCP/M 19, 18 I Differential analog input for channel C
INDP/M 13, 14 I Differential analog input for channel D
CLOCK/SYNC
CLKINP/M 27, 28 I Differential clock input for ADC
SYSREFP/M 33, 34 I External sync input
CONTROL/SERIAL
RESET 48 I Hardware reset. Active high. This pin has an internal 150-kΩ pull-down resistor.
SCLK 6 I Serial interface clock input
SDIN 5 I Serial interface data input.
SEN 7 I Serial interface enable
SDOUT 11 O Serial interface data output.
PDN 50 I/O Power down. Can be configured via SPI register setting.
RES 49 – Reserve Pin. Connect to GND
NC 22, 23 – No connect
Trigger ready output for burst mode for channel A,B. Can be configured via SPI to TRDY signal
TRDYAB 54 O
for all four channels in burst mode. Can be left open if not used.
Manual burst mode trigger input channel A,B. Can be configured via SPI to manual trigger input
TRIGAB 53 I
signal for all four channels in burst mode. Can be connected to GND if not used.
Trigger ready output for burst mode for channel C,D. Can be configured via SPI to TRDY signal
TRDYCD 1 O
for all four channels in burst mode. Can be left open if not used.
Manual burst mode trigger input channel C,D. Can be configured via SPI to manual trigger input
TRIGCD 2 I
signal for all four channels in burst mode. Can be connected to GND if not used.
DATA INTERFACE
DAP/M 58, 59 O JESD204B Serial data output for channel A
DBP/M 61, 62 O JESD204B Serial data output for channel B
DCP/M 66, 65 O JESD204B Serial data output for channel C
DDP/M 69, 68 O JESD204B Serial data output for channel D
Synchronization input for JESD204B port channel A,B. Can be configured via SPI to SYNCb
SYNCbABP/M 55, 56 I
signal for all four channels. Needs external termination.
Synchronization input for JESD204B port channel C,D. Can be configured via SPI to SYNCb
SYNCbCDP/M 72, 71 I
signal for all four channels. Needs external termination.
POWER SUPPLY
10, 16, 24, 31,
AVDD3V I Analog 3 V for analog buffer
39, 45
9, 12, 15, 17,
20, 25, 30, 35,
AVDD I Analog 1.9-V power supply
38, 40, 43, 44,
46
DVDD 8, 47 I Digital 1.9-V power supply
4, 51, 57, 64,
IOVDD I Digital 1.15-V power supply for the JESD204B transmitter
70
AGND 21, 26, 29, 32 I Analog ground
3, 52, 60, 63,
DGND I Digital ground
67

ADS58J63
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
AVDD3V –0.3 3.6 V
AVDD –0.3 2.1 V
Supply voltage range:
DVDD –0.3 2.1 V
IOVDD –0.2 1.4 V
Voltage between AGND and DGND –0.3 0.3 V
INA/BP, INA/BM, INC/DP, INC/DM –0.3 3 V
CLKINP, CLKINM –0.3 AVDD + 0.3 V
Voltage applied to input pins SYSREFP, SYSREFM, TRIGAB, TRIGCD –0.3 AVDD + 0.3 V
SCLK, SEN, SDIN, RESET, SPI_MODE,
–0.2 2 V
SYNCbABP/M, SYNCbCDP/M, PDN
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1 kV
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD3V 2.85 3 3.6 V
AVDD 1.8 1.9 2 V
Supply voltage range:
DVDD 1.8 1.9 2 V
IOVDD 1.1 1.15 1.2 V
Differential input voltage range 1.9 VPP
Analog inputs:
Input common-mode voltage VCM ± 0.025 V
Input clock frequency, device clock frequency 250 500 MHz
Sine wave, ac-coupled 1.5 VPP
Input clock amplitude differential
Clock inputs: LVPECL, ac-coupled 1.6 VPP
(VCLKP – VCLKM)
LVDS, ac-coupled 0.7 VPP
Input device clock duty cycle, default after reset 45% 50% 55%
Operating free-air, TA –40 85 ºC
Temperature:
Operating junction, TJ 105 (2) 125 ºC
(1) SYSREF needs to be applied for the device bring up.

(2) Prolonged use above this junction temperature can increase the device failure-in-time (FIT) rate.

ADS58J63
6.4 Thermal Information

ADS58J63
THERMAL METRIC (1) RMP (VQFNP) UNIT
72 PINS
RθJA Junction-to-ambient thermal resistance 22.3
RθJC(top) Junction-to-case (top) thermal resistance 5.1
RθJB Junction-to-board thermal resistance 2.4
°C/W
ψJT Junction-to-top characterization parameter 0.1
ψJB Junction-to-board characterization parameter 2.3
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics

Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC Sampling Frequency = 500
Msps, 50% clock duty cycle, AVDD3V = 3 V, AVDD/DVDD = 1.9 V, IOVDD = 1.15 V, –1 -dBFS differential input for IF ≤ 250
MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC Sampling Rate 500 MSPS
Resolution 14 Bits
POWER SUPPLY
AVDD3V 2.85 3 3.6 V
AVDD 1.8 1.9 2 V
DVDD 1.8 1.9 2 V
IOVDD 1.1 1.15 1.2 V
IAVDD3V 3-V analog supply current 340 mA
IAVDD 1.9-V analog supply current 365 mA
2x Decimation (4 ch) 190 mA
IDVDD 1.9-V digital supply current
184 mA
370-MHz, full-scale
1.15-V SERDES supply Burst Mode (4 ch)
IIOVDD input on all four 533 mA
current channels
2x Decimation (4 ch) 2.68 W
Pdis Total power dissipation
Burst Mode (4 ch) 2.67 W
Global power-down power
250 mW
dissipation
ANALOG INPUTS
Differential input full-scale
1.9 VPP
voltage
VCM ±
Input common-mode voltage V
0.025
Diffrential input resistance at fIN =370MHz 0.5 kΩ
Differential input capacitance at fIN =370MHz 2.5 pF
Analog input bandwidth (3 dB) 900 MHz

ADS58J63
Electrical Characteristics (continued)

Msps, 50% clock duty cycle, AVDD3V = 3 V, AVDD/DVDD = 1.9 V, IOVDD = 1.15 V, –1 -dBFS differential input for IF ≤ 250
MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISOLATION
fIN = 10 MHz 105 dBFS
Isolation between near fIN = 100 MHz 104 dBFS
channels
(CHA and CHB are near to fIN = 170 MHz 96 dBFS
each other. fIN = 270 MHz 97 dBFS
CHC and CHD are near to
each other) fIN = 370 MHz 93 dBFS
Crosstalk fIN = 470 MHz 85 dBFS
(1)
Isolation between far channels f = 170 MHz 96 dBFS
IN
(for CHA and CHB, CHC and
CHD are far channels) fIN = 270 MHz 97 dBFS
CLOCK INPUT
CLKINP and CLKINM pins are connected to
Internal clock biasing 1.15 V
internal biasing voltage through 400 Ω
(1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on the victim channel.
6.6 AC Performance
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
14-Bit Burst Mode Decimate-by-2 Filter
(DDC Mode 8) (DDC Mode 2)
fIN = 10 MHz 70.8 74.1
fIN = 70 MHz 70.5 74
AIN = – 1 dBFS 69.5 73.2
fIN = 190 MHz
AIN = – 3 dBFS 65.6 70.3 73.6
SNR Signal-to-noise ratio dBFS
fIN = 300 MHz 69 72.6
fIN = 350 MHz 68.7 72
fIN = 370 MHz 64.6 68.4
fIN = 470 MHz 67.5 70.7
fIN = 10 MHz 154.8 154.8
fIN = 70 MHz 154.5 154.5
AIN = – 1 dBFS 153.5 153.5
fIN = 190 MHz
AIN = – 3 dBFS 149.5 154.3 154.3 dBFS/
NSD Noise spectral density
fIN = 300 MHz 153 153.0 Hz
fIN = 350 MHz 152.7 152.7
fIN = 370 MHz 148.5 152.4 152.4
fIN = 470 MHz 151.5 151.5

ADS58J63
AC Performance (continued)
fIN = 10 MHz 70.7 73.9
fIN = 70 MHz 70.4 73.9
AIN = – 1 dBFS 69.4 73.1
fIN = 190 MHz
Signal-to-noise and AIN = – 3 dBFS 70.2 73.5
SINAD dBFS
distortion ratio fIN = 300 MHz 68.9 72.5
fIN = 350 MHz 68.6 71.7
fIN = 370 MHz 68.2
fIN = 470 MHz 66.9 69.7
fIN = 10 MHz 89 88
fIN = 70 MHz 87 95
AIN = – 1 dBFS 86 97
fIN = 190 MHz
Spurious-free dynamic AIN = – 3 dBFS 78 88 96
SFDR dBc
range fIN = 300 MHz 82 94
fIN = 350 MHz 82 82
fIN = 370 MHz 75 81
fIN = 470 MHz 73 74
fIN = 10 MHz 89 91
fIN = 70 MHz 94 103
AIN = – 1 dBFS 86 101
fIN = 190 MHz
Second harmonic AIN = – 3 dBFS 78 88 101
HD2 dBc
distortion fIN = 300 MHz 82 97
fIN = 350 MHz 82 82
fIN = 370 MHz 75 81
fIN = 470 MHz 73 74
fIN = 10 MHz 93 88
fIN = 70 MHz 87 99
AIN = – 1 dBFS 98 100
fIN = 190 MHz
AIN = – 3 dBFS 78 97 98
HD3 Third harmonic distortion dBc
fIN = 300 MHz 95 100
fIN = 350 MHz 90 96
fIN = 370 MHz 75 85
fIN = 470 MHz 83 83
fIN = 10 MHz 94 98
fIN = 70 MHz 94 95
AIN = – 1 dBFS 93 97
fIN = 190 MHz
Non Spurious-free dynamic AIN = – 3 dBFS 87 93 96
HD2, range (excluding HD2, dBc
HD3 HD3) fIN = 300 MHz 92 94
fIN = 350 MHz 91 94
fIN = 370 MHz 80 90
fIN = 470 MHz 87 93

ADS58J63
AC Performance (continued)
fIN = 10 MHz 88 86
fIN = 70 MHz 85 92
AIN = – 1 dBFS 85 92
fIN = 190 MHz
AIN = – 3 dBFS 86 91
THD Total harmonic distortion dBc
fIN = 300 MHz 81 89
fIN = 350 MHz 79 82
fIN = 370 MHz 78
fIN = 470 MHz 72 73
fIN = 185 MHz, fIN =
AIN = – 7 dBFS 89
190 MHz
Third-tone intermodulation fIN = 365 MHz, fIN =
IMD3 AIN = – 7 dBFS 82 dBFS
distortion 370 MHz
fIN = 465 MHz, fIN =
AIN = – 7 dBFS 77
470 MHz

ADS58J63
6.7 Digital Characteristics

Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500
MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
(1)
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN)
VIH High-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels 0.8 V
VIL Low-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels 0.4 V
SEN 0 µA
IIH High-level input current
RESET, SCLK, SDIN, PDN 100 µA
SEN 50 µA
IIL Low-level input current
RESET, SCLK, SDIN, PDN 0 µA
DIGITAL INPUTS (SYSREFP, SYSREFM, SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP)
VD Differential Input Voltage 0.35 0.45 1.4 V
V(CM_DIG) Common-mode voltage for SYSREF 1.3 V
DIGITAL OUTPUTS (SDOUT, PDN)
DVDD –
VOH High-level output voltage DVDD V
0.1
VOL Low-level output voltage 0.1 V
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM) (2)
VOD Output differential voltage With default swing setting. 700 mVPP
VOC Output common-mode voltage 450 mV
Transmitter pins shorted to any voltage between
Transmitter short-circuit current –100 100 mA
–0.25 V and 1.45 V
zos Single-ended output impedance 50 Ω
Output capacitance inside the device,
Output capacitance 2 pF
from either output to ground
(1) The RESET, SCLK, SDATA, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ
(typical) pull up resistor to IOVDD.
(2) 50-Ω, single-ended external termination to IOVDD.

ADS58J63
6.8 Timing Characteristics

Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500
MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input,
unless otherwise noted.
MIN TYP MAX UNITS
SAMPLE TIMING CHARACTERISTICS
Aperture delay 0.75 1.6 ns
Aperture delay matching between two channels on the same device ±70 ps
Aperture delay matching between two devices at the same temperature and supply voltage ±270 ps
Aperture jitter 135 fS rms
Wake-up time to valid data after coming out of global power-down 150 µs
Input
Data Latency (1) ADC sample to digital output 77 Clock
Cycles
Input
OVR Latency ADC sample to OVR bit 44 Clock
Cycles
Input clock rising edge cross-over to output clock rising edge
tPDI Clock propagation delay 4 ns
cross-over
tSU_SYSREF Setup time for SYSREF, referenced to input clock rising edge 300 900 ps
tH_SYSREF Hold time for SYSREF, referenced to input clock rising edge 100 ps
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
Unit interval 100 400 ps
Serial output data rate 2.5 10 Gbps
Total jitter for BER of 1E-15 and lane rate = 10 Gbps 26 ps
Random jitter for BER of 1E-15 and lane rate = 10 Gbps 0.75 ps rms
Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps 12 ps, pk-pk
Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output
tR, tF 35 ps
waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps
(1) Overall ADC Latency = Data Latency + tPDI
N+1 N+2
N
SAMPLE
Data Latency: 77 Clock Cycles TPD
CLKINP
CLKINM
DAP/M
DBP/M D D D
DCP/M 20 1 20
DDP/M
SAMPLE N-1 SAMPLE N SAMPLE N+1
Figure 1. Latency Timing Diagram

ADS58J63
6.9 Typical Characteristics: 14-Bit Burst Mode

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15
V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.
0 0
-20 -20
Amplitude (dBFS)
Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
0 50 100 150 200 250 0 50 100 150 200 250
Input Frequency (MHz) D001
FIN = 10 MHz , AIN = –1 dBFS FIN = 140 MHz , AIN = –1 dBFS
SNR = 71 dBFS, SFDR = 89 dBc, SFDR = 89 dBc (Non23) SNR = 70 dBFS, SFDR = 88 dBc, SFDR = 91 dBc (Non23)
Figure 2. FFT for 10-MHz Input Signal Figure 3. FFT for 140-MHz Input Signal
0 0
-20 -20
Amplitude (dBFS)
Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
0 50 100 150 200 250 0 50 100 150 200 250
SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (Non23) SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (Non23)
0 0
-20 -20
Amplitude (dBFS)
Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
0 50 100 150 200 250 0 50 100 150 200 250
FIN = 300 MHz , AIN = - 3 dBFS FIN = 370 MHz , AIN = - 3 dBFS

ADS58J63
Typical Characteristics: 14-Bit Burst Mode (continued)

0 0
-20 -20
Amplitude (dBFS)
Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
0 50 100 150 200 250 0 50 100 150 200 250
FIN = 470 MHz , AIN = - 3 dBFS FIN1 = 185 MHz, FIN2 = 190 MHz, IMD = 89 dBFS
SNR = 67.4 dBFS, SFDR = 73 dBc, SFDR = 80 dBc (Non23) Each tone at -7 dBFS
Figure 8. FFT for 470-MHz Input Signal Figure 9. FFT for Two-Tone Input Signal
0 0
-20 -20
Amplitude (dBFS)
Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
0 50 100 150 200 250 0 50 100 150 200 250
FIN1 = 185 MHz, FIN2 = 190 MHz, IMD = 103 dBFS FIN1 = 370 MHz, FIN2 = 365 MHz, IMD = 81.7 dBFS
Each tone at -36 dBFS Each tone at -7 dBFS
Figure 10. FFT for Two-Tone Input Signal Figure 11. FFT for Two-Tone Input Signal
0 0
-20 -20
Amplitude (dBFS)
Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
0 50 100 150 200 250 0 50 100 150 200 250
FIN1 = 370 MHz, FIN2 = 365 MHz, IMD = 102 dBFS FIN1 = 470 MHz, FIN2 = 465 MHz, IMD = 76.7 dBFS
Each tone at -36 dBFS Each tone at -7 dBFS
Figure 12. FFT for Two-Tone Input Signal Figure 13. FFT for Two-Tone Input Signal

ADS58J63

0 -88
-90
-20
-92
Amplitude (dBFS)
-40
-94
IMD (dBFS)
-60 -96
-98
-80
-100
-100
-102
-120 -104
0 50 100 150 200 250 -35 -31 -27 -23 -19 -15 -11 -7
Each Tone Amplitude (dBFS) D014
FIN1 = 470 MHz, FIN2 = 465 MHz, IMD = 98.8 dBFS FIN1 = 185 MHz, FIN2 = 190 MHz
Each tone at -36 dBFS
Figure 14. FFT for Two-Tone Input Signal Figure 15. Intermodulation Distortion Vs Input Amplitude
-80 -74
-84
-80
-88
IMD (dBFS)
IMD (dBFS)
-86
-92
-92
-96
-98
-100
-104 -104
-35 -31 -27 -23 -19 -15 -11 -7 -35 -31 -27 -23 -19 -15 -11 -7
FIN1 = 365 MHz, FIN2 = 370 MHz FIN1 = 465 MHz, FIN2 = 470 MHz
Figure 16. Intermodulation Distortion Vs Input Amplitude Figure 17. Intermodulation Distortion Vs Input Amplitude
96 96
Ain = -1 dBFS
Ain = -3 dBFS
92 93
Interleaving Spur (dBc)
88 90
SFDR (dBc)
84 87
80 84
76 81
72 78
0 40 80 120 160 200 240 280 320 360 400 440 480 0 40 80 120 160 200 240 280 320 360 400 440 480
Figure 18. Spurious-Free Dynamic Range vs Input Figure 19. IL Spur Vs Input Frequency
Frequency

ADS58J63

71.5 72
AIN = -1 dBFS AVDD = 1.8 V AVDD = 1.95 V
AIN = -3 dBFS AVDD = 1.85 V AVDD = 2 V
70.5 71.2 AVDD = 1.9 V
SNR (dBFS)
SNR (dBFS)
69.5 70.4
68.5 69.6
67.5 68.8
66.5 68
0 40 80 120 160 200 240 280 320 360 400 440 480 -40 -15 10 35 60 85
Temperature (°C) D020
FIN = 190 MHz, AIN = – 1 dBFS
Figure 20. Signal-to-Noise Ratio vs Input Frequency Figure 21. Signal-to-Noise Ratio vs AVDD Supply and
Temperature
93 72
AVDD = 1.8 V AVDD = 1.95 V AVDD = 1.8 V AVDD = 1.95 V
AVDD = 1.85 V AVDD = 2 V AVDD = 1.85 V AVDD = 2 V
AVDD = 1.9 V 71 AVDD = 1.9 V
91
70
SNR (dBFS)
SFDR (dBc)
89 69
68
87
67
85 66
-40 -15 10 35 60 85 -40 -15 10 35 60 85
FIN = 190 MHz, AIN = – 1 dBFS FIN = 370 MHz, AIN = – 3 dBFS
Figure 22. Spurious-Free Dynamic Range vs AVDD Supply Figure 23. Signal-to-Noise Ratio vs AVDD Supply and
and Temperature Temperature
84 71.4
AVDD = 1.8 V AVDD = 1.95 V DVDD = 1.75 V DVDD = 1.9 V
AVDD = 1.85 V AVDD = 2 V DVDD = 1.8 V DVDD = 1.95 V
AVDD = 1.9 V 71 DVDD = 1.85 V DVDD = 2 V
83
SNR (dBFS)
SFDR (dBc)
70.6
82
70.2
81
69.8
80 69.4
-40 -15 10 35 60 85 -40 -15 10 35 60 85
Figure 24. Spurious-Free Dynamic Range vs AVDD Supply Figure 25. Signal-to-Noise Ratio vs DVDD Supply and

ADS58J63

92 71
DVDD = 1.75 V DVDD = 1.9 V DVDD = 1.75 V DVDD = 1.9 V
DVDD = 1.8 V DVDD = 1.95 V DVDD = 1.8 V DVDD = 1.95 V
91 DVDD = 1.85 V DVDD = 2 V DVDD = 1.85 V DVDD = 2 V
70
90
SNR (dBFS)
SFDR (dBc)
89 69
88
68
87
86 67
-40 -15 10 35 60 85 -40 -15 10 35 60 85
Figure 26. Spurious-Free Dynamic Range vs DVDD Supply Figure 27. Signal-to-Noise Ratio vs DVDD Supply and
84 72.2
DVDD = 1.75 V DVDD = 1.9 V AVDD3V = 2.85 V AVDD3V = 3.3 V
DVDD = 1.8 V DVDD = 1.95 V AVDD3V = 3 V AVDD3V = 3.4 V
DVDD = 1.85 V DVDD = 2 V 71.7 AVDD3V = 3.1 V AVDD3V = 3.5 V
83 AVDD3V = 3.2 V AVDD3V = 3.6 V
71.2
SNR (dBFS)
SFDR (dBc)
82 70.7
70.2
81
69.7
80 69.2
-40 -15 10 35 60 85 -40 -15 10 35 60 85
Figure 28. Spurious-Free Dynamic Range vs DVDD Supply Figure 29. Signal-to-Noise Ratio vs AVDD3V Supply and
92 73
AVDD3V = 2.85 V AVDD3V = 3.3 V AVDD3V = 2.85 V AVDD3V = 3.3 V
AVDD3V = 3 V AVDD3V = 3.4 V AVDD3V = 3 V AVDD3V = 3.4 V
91 AVDD3V = 3.1 V AVDD3V = 3.5 V 72 AVDD3V = 3.1 V AVDD3V = 3.5 V
AVDD3V = 3.2 V AVDD3V = 3.6 V AVDD3V = 3.2 V AVDD3V = 3.6 V
90 71
SNR (dBFS)
SFDR (dBc)
89 70
88 69
87 68
86 67
-40 -15 10 35 60 85 -40 -15 10 35 60 85
Figure 30. Spurious-Free Dynamic Range vs AVDD3V Figure 31. Signal-to-Noise Ratio vs AVDD3V Supply and
Supply and Temperature Temperature

ADS58J63

84 74 150
AVDD3V = 2.85 V AVDD3V = 3.3 V SNR (dBFS)
AVDD3V = 3 V AVDD3V = 3.4 V SFDR (dBc)
AVDD3V = 3.1 V AVDD3V = 3.5 V 72 SFDR (dBFS) 125
83 AVDD3V = 3.2 V AVDD3V = 3.6 V
SFDR (dBc,dBFS)
SNR (dBFS)
SFDR (dBc)
70 100
82
68 75
81
66 50
80 64 25
-40 -15 10 35 60 85 -70 -60 -50 -40 -30 -20 -10 0
Amplitude (dBFS) D032
FIN = 370 MHz, AIN = – 3 dBFS FIN = 190 MHz
Figure 32. Spurious-Free Dynamic Range vs AVDD3V Figure 33. Performance vs Amplitude
Supply and Temperature
74 180 75 110
SNR (dBFS) SNR
SFDR (dBc) SFDR
72.5 SFDR (dBFS) 150 73 100
SFDR (dBc,dBFS)
71 120
SNR (dBFS)
SNR (dBFS)
SFDR (dBc)
71 90
69.5 90
69 80
68 60
67 70
66.5 30
65 0 65 60
-70 -60 -50 -40 -30 -20 -10 0 0.2 0.6 1 1.4 1.8 2.2
Amplitude (dBFS) D033
Differential Clock Amplitude (Vpp) D034
FIN = 370 MHz FIN = 190 MHz, AIN = – 1 dBFS
Figure 34. Performance vs Amplitude Figure 35. Performance vs Clock Amplitude

75 125 73 95
SNR SNR
SFDR SFDR
72 100 72 90
SNR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR (dBc)
69 75 71 85
66 50 70 80
63 25 69 75
60 0 68 70
0.2 0.6 1 1.4 1.8 2.2 30 35 40 45 50 55 60 65 70
Differential Clock Amplitude (Vpp) D035
Input Clock Duty Cycle (%) D036
Figure 36. Performance vs Clock Amplitude Figure 37. Performance vs Clock Duty Cycle

ADS58J63

72 90 0
SNR
71 SFDR 87
-20
70 84
Amplitude (dBFS)
-40
SNR (dBFS)
SFDR (dBc)
69 81
-60
68 78
-80
67 75
66 72 -100
65 69 -120
30 35 40 45 50 55 60 65 70 0 50 100 150 200 250
Input Clock Duty Cycle (%) D037
FIN = 370 MHz, AIN = – 3 dBFS FIN = 190 MHz , AIN = –1 dBFS
SFDR = 49 dBc, fPSRR = 5 MHz, APSRR = 50 mVPP
Figure 38. Performance vs Clock Duty Cycle Figure 39. Power-Supply Rejection Ratio FFT for test signal
on AVDD Supply
-10 0
PSRR with 50-mVPP Signal on AVDD
-15 PSRR with 50-mVPP Signal on AVDD3V
-20
-20
Amplitude (dBFS)
-25 -40
PSRR (dB)
-30
-60
-35
-40 -80
-45
-100
-50
-55 -120
0 50 100 150 200 250 300 0 50 100 150 200 250
Frequency of Signal on Supply (MHz) D039
FIN = 190 MHz, AIN = – 1 dBFS FIN = 190 MHz , AIN = – 1 dBFS
SFDR = 81 , fCMRR = 5 MHz, ACMRR = 50 mVPP
Figure 40. Power-Supply Rejection Ratio vs Supplies Figure 41. Common-Mode Rejection Ratio FFT
-20 4
AVDD_Power (W) IOVDD_Power (W)
-25 DVDD_Power (W) TotalPower (W)
3.2 AVDD3V_Power (W)
Power Consumption (W)
-30
-35
CMRR (dB)
2.4
-40
-45 1.6
-50
0.8
-55
-60 0
0 50 100 150 200 250 300 250 300 350 400 450 500
Frequency of Input Common-Mode Signal (MHz) D041
Sampling Speed (MSPS) D042
FIN = 190 MHz, AIN= – 1dBFS
50-mVPP test-Signal on input common mode
Figure 42. Common-Mode Rejection Ratio Figure 43. Power vs Chip Clock

ADS58J63
6.10 Typical Characteristics: Mode 2

Low pass or high pass decimation-by-2 filter selected as per input frequency. Typical values are at TA = 25°C, full
temperature range is from TMIN = –40°C to TMAX = 85°C, ADC Sampling Frequency = 500 Msps, 14-bit Resolution, No
Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input
for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.
0 0
-20 -20
Amplitude (dBFS)
Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
0 25 50 75 100 125 0 25 50 75 100 125
FIN = 100 MHz , AIN = – 1 dBFS FIN = 150 MHz , AIN = – 1 dBFS
0 0
-20 -20
Amplitude (dBFS)
Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
0 25 50 75 100 125 0 25 50 75 100 125

ADS58J63
6.11 Typical Characteristics: Mode 0

Low-pass decimation-by-2 filter selected, Complex FFT plotted,mixer frequency 125 MHz. Typical values are at TA = 25°C,
full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC Sampling Frequency = 500 Msps, 14-bit Resolution, No
Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input
for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.
0 0
-20 -20
Amplitude (dBFS)
Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
-125 -75 -25 25 75 125 -125 -75 -25 25 75 125
0
-20
Amplitude (dBFS)
-40
-60
-80
-100
-120
-125 -75 -25 25 75 125
FIN = 470 MHz , AIN = – 3 dBFS
SNR = 66.3 dBFS, SFDR = 75 dBc, SFDR = 75 dBc (Non23)
Figure 50. FFT for 470-MHz Input Signal

ADS58J63
7 Detailed Description
7.1 Overview
The ADS58J63 is a low power, wide bandwidth 14-bit 500 MSPS quad channel telecom receiver IC. It supports
the JESD204B serial interface with data rates up to 10 Gbps supporting 1 lane per channel. The buffered analog
input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch
energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency
range with very low power consumption. Its digital block includes a 2x and 4x decimation low pass filter with FS/4
and k×FS/16 mixers to support a receive bandwidth up to 200 MHz and a output burst mode for use as DPD
observation receiver.
The JESD204B interface reduces the number of interface lines allowing high system integration density. An
internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock which is used
to serialize the 14bit data from each channel.
7.2 Functional Block Diagram
Digital Block 2x
14bit
INAP/M Interleaving FS/4 DAP/M
ADC
Correction
4x
JESD204B
Digital Block 2x
14bit K*FS/16
Interleaving FS/8
INBP/M DBP/M
ADC
Correction Burst Mode
TRIGAB
TRIGCD
TRDYAB
SYSREFP/M
TRDYCD
PLL SYNCbAB
CLKINP/M
x10/x20
SYNCbCD
Digital Block Burst Mode

14bit
INCP/M Interleaving DCP/M
ADC 2x
Correction
FS/4 JESD204B
Digital Block 4x
14bit
INDP/M Interleaving DDP/M
ADC 2x
Correction K*FS/16
FS/8
Configuration
Registers
SDIN
SDOUT
SEN
SCAN_EN
SCLK
RESET

ADS58J63
7.3 Feature Description

7.3.1 Analog Inputs
The ADS58J63 analog signal inputs are designed to be driven differentially. The analog input pins have internal
analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high
impedance input across a very wide frequency range to the external driving source which enables great flexibility
in the external analog filter design as well as excellent 50 Ω matching for RF applications. The buffer also helps
to isolate the external driving circuit from the internal switching currents of the sampling circuit which results in a
more constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to 1.9 V using 600-Ω resistors which allows
for AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +
0.475 V) and (VCM – 0.475 V), resulting in a 1.9-Vpp (default) differential input swing. The input sampling circuit
has a 3-dB bandwidth that extends up to 900 MHz.
7.3.2 Recommended Input Circuitry

In order to achieve optimum AC performance the following circuitry is recommended at the analog inputs.
T1 T2 0.1uF
10
0.1uF INxP
25 25
0.1uF
3.3 pF Rin Cin

25
25
INxM
1:1 1:1 0.1uF
10
Device
Figure 51. Analog Input Driving Circuit

ADS58J63
7.4 Device Functional Modes

7.4.1 Digital Features
The ADS58J63 supports decimation by 2 and 4 and burst mode output. The 4 channels can be configured as
pairs (A and B and C and D) to either burst or decimation mode (must be same decimation mode for all 4
channels).
Table 1. Overview of Operating Modes

MAX
OPERATING DIGITAL BANDWIDTH BANDWIDTH OUTPUT
DESCRIPTION DECIMATION OUTPUT
MODE MIXER AT 491Msps AT 368Msps FORMAT
RATE
0 ±FS/4 2 200 MHz 150 MHz Complex 250 Msps
2 – 2 100 MHz 75 MHz Real 250 Msps
4 N×Fs/16 2 100 MHz 75 MHz Real 250 Msps
Decimation
5 N×Fs/16 2 200 MHz 150 MHz Complex 250 Msps
6 N×Fs/16 4 100 MHz 75 MHz Complex 125 Msps
7 N×Fs/16 2 100 MHz 75 MHz Real 500 Msps
8 Burst Mode – – 245.76 MHz 184.32 MHz Real 500 Msps
Figure 52 shows signal processing in Digital Down-Conversion (DDC) Block in ADS58J63.
I data
Filter N
Real data 0
IL 500MSPS cos(2nfmix1/fS ) cos(2nfmix2/fS ) 2
E
data, x(n) 4
n
CH x g 2 5
i Upscaled 6 To JESD
n sin(2nfmix1/fS ) Zero- 7
e
sin(2nfmix2/fS ) Encoder
padded 8
data
Filter N
Q data
14-bit
Burst Mode 14/9-bit Burst Mode data
Mode
Selection
Figure 52. Digital Down-Conversion (DDC) Block
Table 2 shows characteristics of different blocks of DDC signal processing blocks active in different modes.
Table 2. Features of DDC Block in Different Modes

Mode fmix1 Filter and Decimation fmix 2 Output
0 fS/4 LPF cut off freq at fS/4, decimation by 2 not used I, Q data at 250 MSPS each is given out
2 not used LPF or HPF cut off at fS/4, decimation by 2 not used Straight 250 MSPS data is given out
4 k fS/16 LPF cutoff at fS/8, decimation by 2 fS/8 Real data at 250 MSPS is given out
5 k fS/16 LPF cutoff at fS/8, decimation by 2 not used I, Q data at 250 MSPS each is given out
6 k fS/16 LPF cutoff at fS/8, decimation by 4 not used I, Q data at 125 MSPS each is given out
Real data is up-scaled, zero-padded and given out
7 k fS/16 LPF cutoff at fS8, decimation by 2 fS/8
at 500 MSPS
8 not used not used not used Straight 500 MSPS Burst mode data is given out

ADS58J63
7.4.2 Mode 0 – Decimation by 2 with IQ Outputs for up to 220 MHz of IQ Bandwidth

In this configuration, the DDC block includes a fixed frequency ±Fs/4 complex digital mixer preceding the digital
filter – so the IQ passband is ± ~110 MHz (3 dB) centered at Fs/4. Mixing with +FS/4 inverts the spectrum. The
stop band attenuation is approximately 90 dB and the passband flatness is ±0.1 dB. Figure 53 shows mixing
operation in DDC Mode 0.
± Fs/4
500 Msps IQ: 500 Msps

14-bit
2x IQ: 250 Msps
ADC
FS/4
FS/2 FS/4
Figure 53. Mixing in Mode 0
Table 3. Filter Specification Details – Mode 0

CORNERS LOW PASS
–0.1 dB 0.204 × Fs
–0.5 dB 0.211 × Fs
–1 dB 0.216 × Fs
–3 dB 0.226 × Fs
20 0.5
0 0
-20 -0.5
Magnitude (dB)
Magnitude (dB)
-40 -1
-60 -1.5
-80 -2
-100 -2.5
-120 -3
0 0.1 0.2 0.3 0.4 0.5 0 0.05 0.1 0.15 0.2 0.25
Frequency Response D052
Figure 54. Frequency Response of Filter in Mode 0 Figure 55. Zoomed view of Frequency Response

ADS58J63
7.4.3 Mode 2 – Decimation by 2 for up to 110 MHz of Real Bandwidth

In this configuration, the DDC block only includes a 2x decimation filter (high pass or low pass) with real outputs.
The passband is ~110 MHz (3 dB). Figure 56 shows filtering operation in DDC Mode 2.
500 Msps
14-bit
2x 250 Msps
ADC
FS/4
FS/2 FS/4
Figure 56. Filtering in Mode 2

CORNERS LOW PASS HIGH PASS
–0.1 dB 0.204 × Fs 0.296 × Fs
–0.5 dB 0.211 × Fs 0.290 × Fs
–1 dB 0.216 × Fs 0.284 × Fs
–3 dB 0.226 × Fs 0.274 × Fs
20 0.5
0 0
-20 -0.5
Magnitude (dB)
Magnitude (dB)
-40 -1
-60 -1.5
-80 -2
-100 -2.5
-120 -3
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.05 0.1 0.15 0.2 0.25
Figure 57. Frequency Response for Decimate-by-2 Low Figure 58. Zoomed View of Frequency Response
Pass and High Pass Filter (in Mode 2)

ADS58J63
7.4.4 Mode 4/7 – Decimation by 2 with Real Outputs for up to 110 MHz of Bandwidth
In this configuration, the DDC block includes a selectable N×Fs/16 complex digital mixer (N from –8 to +7)
preceding the decimation by 2 digital filter also with an IQ passband of ± ~55 MHz (3 dB) centered at N×Fs/16. A
positive value for N inverts the spectrum. In addition a Fs/8 complex digital mixer is added after the decimation
filter transforming the output back to real format while centering the output spectrum within the Nyquist zone.
In addition the ADS58J63 supports a 0-pad feature where a sample with value = 0 gets added after each
sample. In that way the output data rate gets interpolated to 500 Msps (real) with a 2nd image inverted at Fs/2-
Fin.
The stop band attenuation is approximately 90 dB for in-band aliases from negative frequencies and ~55 dB for
out of band aliases. The passband flatness is ±0.1 dB.
FS/8 2nd Image
N*Fs/16 Fs/8
0 Pad Real: 500 Msps
500 Msps IQ: 500 Msps IQ: 250 Msps

14-bit
2x Real: 250 Msps
ADC
FS/4 FS/2
Example:
N= -4
FS/8
FS/4 FS/2 0 FS/8 FS/4 FS/4
Figure 59. Mixing and Filtering in Mode 4/7
Table 5. Filter Specification Details – Mode 4/7

CORNERS LOW PASS
–0.1 dB 0.102 × Fs
–0.5 dB 0.105 × Fs
–1 dB 0.108 × Fs
–3 dB 0.113 × Fs
20 0.5
0 0
-20 -0.5
Magnitude (dB)
Magnitude (dB)
-40 -1
-60 -1.5
-80 -2
-100 -2.5
-120 -3
0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25
Figure 60. Frequency Response for Decimate-by-2 Low- Figure 61. Zoomed View of Frequency Response
Pass Filter (in Mode 4 and Mode 7)

ADS58J63

In this configuration, the DDC block includes a selectable N×Fs/16 complex digital mixer (N from –8 to +7)
preceding the decimation by 2 digital filter – so the IQ passband is ± ~55 MHz (3 dB) centered at N×Fs/16. A
positive value for N inverts the spectrum.
The stop band attenuation is approximately 90 dB for in-band aliases from negative frequencies. The passband
flatness is ±0.1 dB.
N*Fs/16

14-bit
2x IQ: 250 Msps
ADC
Example:
N= -4
FS/4 FS/2 FS/8 FS/4
Figure 62. Mixing and Filtering in Mode 5

CORNERS LOW PASS
–0.1 dB 0.102 × Fs
–0.5 dB 0.105 × Fs
–1 dB 0.108 × Fs
–3 dB 0.113 × Fs
20 0.5
0 0
-20 -0.5
Magnitude (dB)
Magnitude (dB)
-40 -1
-60 -1.5
-80 -2
-100 -2.5
-120 -3
0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25
Pass Filter (in Mode 5)

ADS58J63

In this configuration, the DDC block includes a selectable n×Fs/16 complex digital mixer (n from –8 to +7)
preceding the decimation by 4 digital filter – so the IQ passband is ± ~55 MHz (3 dB) centered at n×Fs/16. A
positive value for N inverts the spectrum. The decimaiton by 4 filter is a cascade of two decimation by 2 filters
with frequency response shown in Figure 66.
The stop band attenuation is approximately 90 dB for in-band aliases from negative frequencies and ~55 dB for
out of band aliases. The passband flatness is ±0.1 dB.
N*Fs/16

14-bit IQ: 250 Msps IQ: 125 Msps
2x 2x
ADC
Example:
N= -6
3FS/8
FS/4 FS/2 FS/8 FS/4
Figure 65. Mixing and Filtering in Mode 6

CORNERS LOW PASS
–0.1 dB 0.102 × Fs
–0.5 dB 0.105 × Fs
–1 dB 0.108 × Fs
–3 dB 0.113 × Fs
20 0.5
0 0
-20 -0.5
Magnitude (dB)
Magnitude (dB)
-40 -1
-60 -1.5
-80 -2
-100 -2.5
-120 -3
0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25
Pass Filter (in Mode 6)

ADS58J63
7.4.7 Mode 8 – Burst Mode

In burst mode the output data is alternated between low resolution (L, 9-bit) and high resolution (H, 14-bit)
output. The burst mode can be configured via SPI register writes independently for channel A/B and channel
C/D.
The high resolution output is 14 bit and the number (#) of high and low resolution samples is set with two user
programmable counters – one for high resolution (HC) and one for low resolution (LC). There is one counter pair
(HC, LC) for channel A/B and one pair for channel C/D. The internal logic checks if the maximum duty cycle is
exceeded and if necessary resets the counters to its default values.
Each output cycle starts with a low resolution and the counter values can be reconfigured for the next cycle
during prior to the start of the next cycle.
Enable
Burst Mode New cycle
L times out
starts again
DA
DB L H L H
DC
DD
Update Counter Values
HRES
14-bit high resolution
9-bit low resolution
D D D D D D D D D D D D D D
OVR HR
13 12 11 10 9 8 7 6 5 4 3 2 1 0
16-bit data going into 8b/10b encoder
Figure 68. Timing Diagram for 14-bit Burst Mode (DDC Mode 8)
The counter values for high and low resolution can be programmed to:
High resolution counter (HC): 1 to 225
Low resolution counter (LC); 1 to 228
The output duty cycle limit is illustrated in Table 8.
Table 8. Output Duty Cycle Limit

HIGH RESOLUTION LOW RESOLUTION MAXIMUM ALLOWED DUTY CYCLE DEFAULT VALUE DEFAULT VALUE
OUTPUT OUTPUT (high : low resolution output) HC LC
14 bit 9 bit 1/3 1 3

ADS58J63
7.4.8 Trigger Input

The burst mode can be operated in auto trigger or manual trigger mode. In manual trigger mode the TRIGGER
input (TRIGAB, TRIGCD) is used to release the high resolution data (HC) burst after the low resolution data
counter LC has timed out. In auto trigger mode the high resolution data is released immediately after completion
of the last low resolution sample.
Using SPI control the ADS58J63 can be configured to use TRIGAB or TRIGCD as the manual trigger input.
7.4.9 Manual Trigger Mode

Upon enabling manual trigger mode, the ADS58J63 starts transmission of low resolution data. As soon as the LC
counter is finished, the manual trigger is unlocked, the trigger ready flag (TRDY) is raised and the high resolution
output H can be triggered. Once the low resolution counter LC is finished, the next high resolution output or burst
mode sequence can be triggered again. The HRES flag is embedded in the JESD204B output data stream. The
counter values can be updated until a new burst mode cycles starts with transmission of low resolution samples.
Example of burst mode with manual trigger:
Enable LC times out
Trigger Event New cycle
Burst Mode Ready for trigger
starts again
DA
DB L H L H
DC
DD
TRDYAB/CD
TRIGAB/CD
HRES
14 bit high resolution
9 bit low resolution
OVR HR
13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 bit data going into 8b/10b encoder
Figure 69. Timing Diagram for Manual Trigger Mode

ADS58J63
7.4.10 Auto Trigger Mode

Upon enabling auto trigger mode, the ADS58J63 starts transmission of low resolution data. As soon as the low
resolution samples counter (LC) is finished, the ADS58J63 immediately begins transmitting the high resolution
output H. The HRES flag can also be embedded in the JESD204B output data stream. The counter values can
be updated until a new burst mode cycles starts with transmission of low resolution samples. Any input on the
trigger input pins is ignored.
Example of burst mode with automatic trigger:
Enable
Burst Mode New cycle
LC times out
starts again
DA
DB L H L H
DC
DD
HRES
14-bit high resolution
9-bit low resolution
OVR HR
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 70. Timing Diagram for Auto Trigger Mode

ADS58J63
7.4.11 Over-range Indication

The ADS58J63 provides a fast over-range indication (FOVR) which can be presented in the digital output data
stream via SPI configuration. When the FOVR indication is embedded in the output data stream, it replaces the
LSB (normal 0) of the 16 bit going to the 8b/10b encoder.
One threshold is set per channel pair A/B and C/D.
14-bit data output
0/
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
OVR
Figure 71. Timing Diagram for FOVR
The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and it gets
presented after just 44 input clock cycles enabling a quicker reaction to an overrange event.
The input voltage level at which the overload is detected is referred to as the threshold. It is programmable using
the FOVR THRESHOLD bits.
The input voltage level at which fast OVR is triggered is:
Full-scale × [the decimal value of the FOVR Threshold bits] / 255)
The default threshold is E3h (227) which corresponds to a threshold of –1 dBFS.
In terms of full scale input, the fast OVR threshold can be calculated as shown in Equation 1:
20 × log (<FOVR Threshold>/255). (1)
Following is an example register write to set the FOVR threshold for all 4 channels:
Table 9. Register Sequence for FOVR Configuration

ADDRESS DATA COMMENT
11h 80h Go to Master page
59h 20h Enable FOVR
11h FFh Go to ADC page
5Fh FFh Set FOVR threshold for chCD to 255
4004h 68h
Go to main digital page
4003h 00h
60ABh 01h Enable bit D0 overwrite
60ADh 03h Select FOVR to replace bit D0
6000h 01h
Issue and clear digital reset
6000h 00h

ADS58J63
7.4.12 Power-Down Mode

The ADS58J63 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN
pin or SPI register writes.
A power-down mask can be configured, which allows a trade-off between wake-up time and power consumption
in power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2 as shown
in Table 10. See the master page registers in Table 15 for further details.
Table 10. Register Address for Power-Down Modes

REGISTER
REGISTER DATA
ADDRESS COMMENT
A[7:0] (Hex) 7 6 5 4 3 2 1 0
MASTER PAGE (80h)
20 PDN ADC CHAB PDN ADC CHCD
MASK 1
21 PDN BUFFER CHCD PDN BUFFER CHAB 0 0 0 0
MASK 2
GLOBAL OVERRIDE PDN MASK
26 CONFIG 0 0 0 0 0
PDN PDN PIN SEL
MASK
53 0 0 0 0 0 0 0
SYSREF
55 0 0 0 PDN MASK 0 0 0 0
To save power, the device can be put in complete power down by using the GLOBAL PDN register bit. However,
when JESD link must remain up while putting the device in power down, the ADC and analog buffer can be
powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK
register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 11
shows power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx
register bits.
Table 11. Power Consumption in Different Power-Down Settings

TOTAL
IAVDD3V IAVDD IDVDD IIOVDD POWER
REGISTER BIT COMMENT (mA) (mA) (mA) (mA) (W)
After reset, with a full-scale input signal to
Default 0.340 0.365 0.184 0.533 2.675
both channels
The device is in complete power-down
GBL PDN = 1 0.002 0.006 0.012 0.181 0.247
state
GBL PDN = 0,
The ADCs of one pair of channels are
PDN ADC CHx = 1 0.277 0.225 0.123 0.496 2.063
powered down
(x = AB or CD)
GBL PDN = 0,
The input buffers of one pair of channels
PDN BUFF CHx = 1 0.266 0.361 0.187 0.527 2.445
iarepowered down
(x = AB or CD)
GBL PDN = 0,
PDN ADC CHx = 1, The ADCs and input buffers of one pair of
0.200 0.224 0.126 0.492 1.830
PDN BUFF CHx = 1 channels are powered down
(x = AB or CD)
GBL PDN = 0,
PDN ADC CHx = 1, The ADCs and input buffers of all channels
0.060 0.080 0.060 0.448 0.960
PDN BUFF CHx = 1 are powered down
(x = AB and CD)

ADS58J63
7.5 Programming
7.5.1 Device Configuration

The ADS58J63 can be configured using a serial programming interface, as described below. In addition, the
device has one dedicated parallel pin (PDN) for controlling the power down modes. The ADS58J63 supports a
24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see detailed register map info) to access all
register bits.
7.5.1.1 Details of Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock) and SDIN (serial interface data) pins. Serial shift of bits into the
device is enabled when SEN is low. Serial data on SDIN are latched at every SCLK rising edge when SEN is
active (low). The interface can work with SCLK frequencies from 5 MHz down to very low speeds (of a few hertz)
and also with non-50% SCLK duty cycle.
Register Address[11:0] Register Data[7:0]
SDIN R/W M P CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
tDH
tSCLK tDSU
SCLK
tSLOADS tSLOADH
SEN
RESET
Figure 72. Serial Interface Timing Diagram
Table 12. Programing Details of Serial Interface

SPI BITS DESCRIPTION OPTIONS
0 = SPI write
R/W Read/write bit
1 = SPI read back
0 = Analog SPI bank (Master and ADC page)
M SPI bank access 1 = JDigital SPI bank (Main Digital, Analog JESD, and
Digital JESD pages)
0 = Page access
P JESD page selection bit
1 = Register access
0 = Channel AB
SPI access for a specific channel of the digital SPI
CH 1 = Channel CD
bank
By default, both channels are being addressed.
ADDR [11:0] SPI address bits —
DATA [7:0] SPI data bits —

ADS58J63
7.5.1.2 Serial Register Write: Analog Bank

The analog SPI bank contains of two pages (the master and ADC page). The internal register of the ADS58J63
analog SPI bank can be programmed by:
1. Drive the SEN pin low.
2. Initiate a serial interface cycle specifying the page address of the register whose content must be written.
– Master page: write address 0011h with 80h.
– ADC page: write address 0011h with 0Fh.
3. Write the register content as shown in Figure 73. When a page is selected, multiple writes into the same
page can be done.
0 0 0 0
SCLK
SEN
RESET
Figure 73. Serial Register Write Timing Diagram
7.5.1.3 Serial Register Readout: Analog Bank

The content from one of the two analog banks can be read out by:
2. Select the page address of the register whose content must be read.
– Master page: write address 0011h with 80h.
– ADC page: write address 0011h with 0Fh.
3. Set the R/W bit to 1 and write the address to be read back.
4. Read back the register content on the SDOUT pin, as shown in Figure 74. When a page is selected, multiple
read backs from the same page can be done.
Register Address[11:0] Register Data[7:0] = XX
1 0 0 0
SCLK
SEN
RESET
SDOUT D7 D6 D5 D4 D3 D2 D1 D0
SDOUT[7:0]
Figure 74. Serial Register Read Timing Diagram

ADS58J63
7.5.1.4 JESD Bank SPI Page Selection

The JESD SPI bank contains four pages (main digital, interleaving engine, digital, and analog JESD pages). The
individual pages can be selected by:
2. Set the M bit to 1 and specify the page with two register writes. Note that the P bit must be set to 0, as
shown in Figure 75.
– Write address 4003h with 00h (LSB byte of page address).
– Write address 4004h with the MSB byte of the page address.
– For Main digital page: write address 4004h with 68h.
– For Digital JESD page: write address 4004h with 69h.
– For Analog JESD page: write address 4004h with 6Ah.
– For Interleaving engine page: write address 4004h with 61h.
0 1 0 0
SCLK
SEN
RESET
Figure 75. SPI Page Selection
7.5.1.5 Serial Register Write: Analog Bank

The analog SPI bank contains two pages (Master and ADC page). The internal register of the ADS58J63 analog
SPI bank can be programmed following these steps:
2. Initiate a serial interface cycle specifying the page address of the register whose content has to be written
– Master page: write address 11h with 80h
– ADC page: write address 11h with 0Fh
3. Write register content. Once a page is selected, multiple writes into the same page can be done.
0 1 1 0
SCLK
SEN
RESET

ADS58J63
7.5.1.6 Serial Register Readout: Analog Bank

SPI read out of content in one of the two analog banks can be accomplished with the following steps:
2. Select the page address of the register which content has to be read.
– Master page: write Address = 11h with 80h
– ADC page: write Address 11h with 0Fh.
3. Set the R/W bit to '1' and write the address to be read back.
4. Read back register content on the SDOUT pin. Once a page is selected, multiple read backs from the same
page can be done.
Register Address[11:0] Register Data[7:0] = XX
1 1 1 0
SCLK
SEN
RESET
SDOUT[7:0]
7.5.1.7 Digital Bank SPI Page Selection

The Digital SPI bank contains five pages (Main digital, Interleaving Engine, Decimation filter, JESD digital, and
JESD analog). The individual pages can be selected following these steps:
2. Set the M bit to ‘1’ and specify the page with two register writes (Note: P bit set to 0)
– Write address 4003h with 00h (LSB byte of page address)
– Write address 4004h MSB byte of page address
spacer
– Main digital page: write Address = 4004h with 68h (default)
– Digital JESD page: write Address = 4004h with 69h
– Analog JESD page: write Address = 4004h with 6Ah
– Interleaving Engine page: write Address = 4004h with 61h
– Decimation Filter page: write Address = 4004h with 61h and 4003h with 41h
Register Address <11:0> Register Data <7:0>
0 1 0 0
SCLK
SEN
RESET
Figure 78. SPI Timing Diagram for Digital Bank Page Selection

ADS58J63
7.5.1.8 Serial Register Write – Digital Bank

The ADS58J63 is a quad channel device and the JESD204B portion is configured individually for 2 channel (A/B
and C/D) using the CH bit. Note the P bit needs to be set to 1 for register writes.
2. Select the digital bank page (Note: M bit = 1, P bit = 0)
– Write address 4003h with 00h
– Main digital page: write Address = 4004h with 68h (default)
3. Set M and P bit to 1 and select ChAB (CH=0) or ChCD (CH=1) and write register content. Once a page is
selected, multiple writes into the same page can be done.
By default, register writes are applied to both channel pairs (broadcast mode). To disable broadcast mode
and enable individual channel writes, write address 4005h with 01h (default is 00h).
Register Address <11:0> Register Data <7:0>
0 1 1 0
SCLK
SEN
RESET
7.5.1.9 Individual Channel Programming

By default, register writes are applied to both channels. To enable individual channel writes, write address 4005h
with 01h (default is 00h).
7.5.1.10 Serial Register Readout – Digital Bank

SPI read out of content in one of the three digital banks can be accomplished with the following steps:
2. Select the digital bank page (Note: M bit = 1, P bit = 0)
– Write address 4003h with 00h
– Main digital page: write Address = 4004h with 68h
3. Set the R/W bit, M and P bit to '1' and select ChAB) or ChCD and write the address to be read back.
4. Read back register content on the SDOUT pin. Once a page is selected, multiple read backs from the same
page can be done.

ADS58J63
Register Address <11:0> Register Data <7:0> = XX

1 1 1 0
SCLK
SEN
RESET
SDOUT <7:0>

ADS58J63
7.5.2 JESD204B Interface

The ADS58J63 supports device subclass 1 with a maximum output data rate of 10 Gbps for each serial
transmitter.
An external SYSREF signal is used to align all internal clock phases and the local multi frame clock to a specific
sampling clock edge. This allows synchronization of multiple devices in a system and minimizes timing and
alignment uncertainty. The ADS58J63 supports single (for all 4 JESD links) or dual (for channel A/B and C/D)
SYNCb inputs and can be configured via SPI.
JESD204B Block
Transport Layer Link Layer

Frame Data 8b/10b
Mapping encoding
Scrambler
1+x14+x15 DX
Comma characters
Test Patterns Initial lane alignment
SYNCb
Figure 81. JESD Interface Block Diagram
Depending on the ADC sampling rate, the JESD204B output interface can be operated with 1 lane per channel.
The JESD204B setup and configuration of the frame assembly parameters is handled via SPI interface.
The JESD204B transmitter block consists of the transport layer, the data scrambler and the link layer. The
transport layer maps the ADC output data into the selected JESD204B frame data format and manages if the
ADC output data or test patterns are being transmitted. The link layer performs the 8b/10b data encoding as well
as the synchronization and initial lane alignment using the SYNC input signal. Optionally data from the transport
layer can be scrambled.
SYSREF SYNCbAB
JESD JESD204B
INA 204B DA
JESD JESD204B
INB 204B DB
JESD JESD204B
INC 204B DC
JESD JESD204B
IND 204B DD
Sample SYNCbCD
Clock
Figure 82. JESD204B Transmitter Block

ADS58J63
7.5.2.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started by the receiving device by de-asserting the SYNCb signal. Upon
detecting a logic low on the SYNC input pins, the ADS58J63 starts transmitting comma (K28.5) characters to
establish code group synchronization.
Once synchronization is completed the receiving device re-asserts the SYNCb signal and the ADS58J63 starts
the initial lane alignment sequence with the next local multi frame clock boundary. The ADS58J63 transmits 4
multi-frames each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame
start and end symbols and the 2nd multi-frame also contains the JESD204 link configuration data.
SYSREF
LMFC Clock
LMFC Boundary
Multi Frame
SYNCb
Transmit Data xxx K28.5 K28.5 ILA ILA DATA DATA

Code Group Initial Lane
Data Transmission
Synchronization Alignment
Figure 83. ILA Sequence
7.5.2.2 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:
• L is the number of lanes per link.
• M is the number of converters per device.
• F is the number of octets per frame clock period.
• S is the number of samples per frame.
Table 13 lists the available JESD204B formats and valid ranges for the ADS58J63. The ranges are limited by the
Serdes line rate and the maximum ADC sample frequency.
Table 13. Available JESD204B Formats and Valid Ranges for the ADS58J63
JESD JESD PLL MAX ADC
OPERATING OUTPUT MAX fSERDES
L M F S DIGITAL MODE MODE MODE OUTPUT
MODE FORMAT (Gbps)
(69h, 01h) (6Ah, 01h6) RATE (Msps)
4 8 4 1 0,5 2x Decimation Complex 40 x 40 x 250 10.0
4 4 2 1 2,4 2x Decimation Real 20 x 20 x 250 5.0
2 4 4 1 2,4 2x Decimation Real 40 x 40 x 250 10.0
4 8 4 1 6 4x Decimation Complex 40 x 20 x 125 5.0
2 8 8 1 6 4x Decimation Complex 80 x 40 x 125 10.0
4 4 2 1 7 2x Decimation with Real 20 x 40 x 500 10.0
‘0-Pad’
4 4 2 1 8 Burst Mode Real 20 x 40 x 500 10.0

ADS58J63
The detailed frame assembly is shown in Table 14.
Table 14. Detailed Frame Assembly

LMFS = 4841 LMFS = 4421 LMFS = 4421 (0-Pad)
DA AI0[15:8] AI0[7:0] AQ0[15:8 AQ0[7:0] A0[15:8] A0[7:0] A1[15:8] A1[7:0] A0[15:8] A0[7:0] 0000 0000
] 0000 0000
DB BI0[15:8] BI0[7:0] BQ0[15:8 BQ0[7:0] B0[15:8] B0[7:0] B1[15:8] B1[7:0] B0[15:8] B0[7:0] 0000 0000
] 0000 0000
DC CI0[15:8] CI0[7:0] CQ0[15:8 CQ0[7:0] C0[15:8] C0[7:0] C1[15:8] C1[7:0] C0[15:8] C0[7:0] 0000 0000
] 0000 0000
DD DI0[15:8] DI0[7:0] DQ0[15:8 DQ0[7:0] D0[15:8] D0[7:0] D1[15:8] D1[7:0] D0[15:8] D0[7:0] 0000 0000
] 0000 0000
LMFS = 2441 LMFS = 2881

DB A0[15:8] A0[7:0] B0[15:8] B0[7:0] AI0[15:8] AI0[7:0] AQ0[15:8] AQ0[7:0] BI0[15:8] BI0[7:0] BQ0[15:8] BQ0[7:0]
DC C0[15:8] C0[7:0] D0[15:8] D0[7:0] CI0[15:8] CI0[7:0] CQ0[15:8] CQ0[7:0] DI0[15:8] DI0[7:0] DQ0[15:8] DQ0[7:0]

ADS58J63
7.5.2.3 JESD Output Switch

The ADS58J63 provides a digital cross point switch in the JESD204B block which allows internal routing of any
output of the 2 ADCs within one channel pair to any of the 2 JESD204B serial transmitters in order to ease layout
constraints. The cross point switch routing is configured via SPI (address 21h in JESD digital page).
JESD SWITCH
ADCA DAP/M
ADCB DBP/M
JESD SWITCH
ADCC DCP/M
ADCD DDP/M
Figure 84. Switching the Output Lanes
7.5.2.3.1 Serdes Transmitter Interface

Each of the 10 Gbps serdes transmitter outputs requires AC coupling between transmitter and receiver. The
differential pair should be terminated with 100 Ω as close to the receiving device as possible to avoid unwanted
reflections and signal degradation.
0.1 uF
DA/B/C/DP
Rt= ZO
Transmission Line
VCM Receiver
Zo
Rt= ZO
DA/B/C/DM
0.1 uF
Figure 85. Serdes Transmitter Connection to Receiver
7.5.2.3.2 SYNCb Interface

The ADS58J63 supports single (either SYNCb input controls all 4 JESD204B links) or dual (1 SYNCb input
controls 2 JESD204B lanes (DA/DB and DC/DD) SYNCb control. When using single SYNCb control, the unused
input should be connected to differential logic low (SYNCbxxP = 0 V, SYNCbxxM = IOVDD).

ADS58J63
7.5.2.3.3 Eye Diagram

Figure 86 to Figure 89 show the serial output eye diagrams of the ADS58J63 at 5 Gbps and 10 Gbps with default
and increased output voltage swing against the JESD204B mask.
Figure 86. Eye at 5-Gbps Bit Rate with Figure 87. Eye at 5-Gbps Bit Rate with
Default Output Swing Increased Output Swing
Figure 88. Eye at 10-Gbps Bit Rate with Figure 89. Eye at 10-Gbps Bit Rate with
Default Output Swing Increased Output Swing

ADS58J63
7.6 Register Maps

The conceptual diagram of Serial Registers is shown in Figure 90.
SPI CYCLE Initiated
M, P, CH, Bits Decoder
M=0 M=1
Analog Page Selection JESD Bank Page Address
Value 6800h Value 6100h Value 6141h Value 6900h Value 6900h
Addr 20h Addr 74h Addr 0h Addr 18h Addr 00h Addr 0h Addr 12h
ADC Page Main Decimation Filter

JESD Analog Page
Master Page [Test Patterns Digital Page IL Engine Page Page JESD Digital
[PLL configuration,
[PDN, OVR, DC and [Nyquist Zone, [Engine bypass, [Signal Processing Page
Output Swing,
Coupling] Fast OVR] OVR Select] DC Correction] Modes 0 to 8] [JESD config]
Pre-emphasis]
Addr 59h Addr 78h Addr F7h Addr 68h Addr 02h Addr 22h Addr 1Bh
Figure 90. Serial Interface Registers
7.6.1 Detailed Register Info

The ADS58J63 contains two main SPI banks. The analog SPI bank gives access to the ADC cores while the digital SPI bank controls the serial interface.
The analog SPI bank is divided into two pages (MASTER and ADC) while the digital SPI bank is divided into five pages (Main digital, Interleaving Engine,
Decimation filter, JESD digital, and JESD analog).
Table 15. Register Map

Register Address Register Data
A7-A0 in hex D7 D6 D5 D4 D3 D2 D1 D0
0 RESET 0 0 0 0 0 0 RESET
3 JESD BANK PAGE SEL [7:0]
5 0 0 0 0 0 0 0 DIS BROADCAST

ADS58J63
Register Maps (continued)

Table 15. Register Map (continued)
11 ANALOG PAGE SELECTION [7:0]
MASTER PAGE (80h)
26 GLOBAL PDN OVERRIDE PDN PIN PDN MASK SEL 0 0 0 0 0
3A 0 BUFFER CURR 0 0 0 0 0 0
INCREASE
39 ALWAYS WRITE 1 0 0 0 0 0 0
53 CLK DIV MASK SYSREF 0 0 0 0 0 0
55 0 0 0 PDN MASK 0 0 0 0
56 0 0 0 0 INPUT BUFF CURR EN 0 0 0
59 0 0 ALWAYS WRITE 1 0 0 0 0 0
ADC PAGE (0Fh)
5F FOVR CHCD THRESH
60 0 0 0 PULSE BIT CHC 0 0 0 0
61 0 0 0 HD3 NYQ2 CHCD 0 0 0 PULSE BIT CHD
6C 0 0 0 PULSE_BIT_CHA 0 0 0 0
6D 0 0 0 HD3_NYQ2_CHAB 0 0 0 PULSE BIT CHB
74 TEST PATTERN ON CHANNEL 0 0 0 0
75 CUSTOM PATTERN 1 [13:6]
76 CUSTOM PATTERN 1 [5:0] 0 0
77 CUSTOM PATTERN 2 [13:6]
78 CUSTOM PATTERN 2 [5:0] 0 0
INTERLEAVING ENGINE PAGE (6100h)
18 0 0 0 0 0 0 IL BYPASS
68 0 0 0 0 0 DC CORR DIS 0
DECIMATION FILTER PAGE (6141h)
0 CHB/C FINE MIX DDC MODE
1 0 0 0 0 DDC MODE6 EN1 ALWAYS WRITE 1 CHB/C HPF EN CHB/C COARSE MIX
2 0 0 CHA/D HPF EN CHA/D COARSE MIX CHA/D FINE MIX
MAIN DIGITAL PAGE (6800h)
0 0 0 0 0 0 0 0 IL RESET
42 0 0 0 0 0 NYQUIST ZONE
4E CTRL NYQUIST ZONE 0 0 0 0 0 0 0
AB 0 0 0 0 0 0 0 OVR EN
AD 0 0 0 0 OVR ON LSB

ADS58J63
Register Maps (continued)

Table 15. Register Map (continued)
F7 0 0 0 0 0 0 0 DIG RESET
JESD DIGITAL PAGE (6900h)
0 CTRL K JESD MODE EN DDC MODE6 EN2 TESTMODE EN 0 LANE ALIGN FRAME ALIGN TX LINK DIS
1 SYNC REG SYNC REG EN SYNCB SEL AB/CD 0 DDC MODE6 EN3 0 JESD MODE
2 LINK LAYER TESTMODE LINK LAYER RPAT LMFC MASK RESET 0 0 0
3 FORCE LMFC COUNT LMFC COUNT INIT RELEASE ILANE SEQ
5 SCRAMBLE EN 0 0 0 0 0 0 0
6 0 0 0 FRAMES PER MULTI FRAME (K)
17 HIRES FLAG ON LSB 0 TRIG SET AB/CD AUTO TRIG EN 0 RATIO INVALID 0
19 0 0 0 0 LC [27:24]
1A LC [23:16]
1B LC [15:8]
1C LC [7:0]
1D 0 0 0 0 HC [27:24]
1E HC [23:16]
1F HC [15:8]
20 HC [7:0]
21 OUPUT CHA MUX SEL OUTPUT CHB MUX SEL OUTPUT CHC MUX SEL OUTPUT CHD MUX SEL
22 0 0 0 0 OUT CHA INV OUT CHB INV OUT CHC INV OUT CHD INV
JESD ANALOG PAGE (6A00h)
12 SEL EMP LANE A/D 0 0
13 SEL EMP LANE B/C 0 0
16 0 0 0 0 0 0 JESD PLL MODE
1B JESD SWING 0 0 0 0 0

ADS58J63
7.6.2 Example Register Writes

Global Power Down

11h 80h Set Master Page
00h26 80h Set Global Power Down
Change decimation mode 0 (default) to mode 4 adjusting both the LMFS configuration (LMFS = 4841 to 4421) as
well as serial output data rate (10 Gbps to 5 Gbps).

4004h 69h Select digital JESD page
4003h 00h
6000h 40h Enables JESD mode overwrite
6001h 01h Select digital to 20x mode
4004h 6Ah Select analog JESD page
6016h 00h Set serdes PLL to 20x mode
4004h 61h Select decimation filter page
4003h 41h
6000h CCh Select mode 4
Digital mixer for chAB set to –4 (FS/4)
6002h 0Ch Digital mixer for chCD set to –4 (FS/4)

ADS58J63
7.6.3 Register Descriptions
7.6.3.1 Register 0h (offset = 0h) [reset = 0h]

Figure 91. Register 0h
A7-A0 in Hex 7 6 5 4 3 2 1 0
0 RESET 0 0 0 0 0 0 RESET
LEGEND: W = Write only; -n = value after reset
Table 16. Register 0h Field Description

(1)
Bit Name Type Reset Description
0 = Normal operation
D7 RESET R/W 0
1 = Internal software reset, clears back to 0
D0 RESET R/W 0
1 = Internal software reset, clears back to 0
(1) Both bits (D7, D0) must be set simultaneously to exercise reset
7.6.3.2 Register 3h/4h (offset = 3h/4h) [reset = 0h]

Figure 92. Register 3h/4h
A7-A0 in Hex 7 6 5 4 3 2 1 0
Table 17. Register 3h/4h Field Description

Program these bits to access desired page in JESD Bank
6100h = Interleaving Engine Page selected
6141h = Decimation Filter Page Selected
D7 - D0 JESD BANK PAGE SEL R/W 0
6800h = Main Digital Page Selected
6900h = JESD Digtial Page selected
6A00h = JESD Analog Page selected

A7-A0 in Hex 7 6 5 4 3 2 1 0
DIS
5 0 0 0 0 0 0 0
BROADCAST
Table 18. Register 5h Field Description

0 = Normal operation. Channel A and B are programmed as a pair. Channel
C and D are programmed as a pair.
D0 DIS BROADCAST R/W 0 1 = channel A and B can be individually programmed based on bit 'CH'.
Similarly channel C and D can be individually programmed based on bit
'CH'.

ADS58J63

A7-A0 in Hex 7 6 5 4 3 2 1 0
11 ANALOG PAGE SELECTION [7:0]
LEGEND: R/W = Read/Write; -n = value after reset
Table 19. Register 11h Field Descriptions

Register page (only one page at a time can be addressed).
Master page = 80h
ANALOG PAGE ADC page = 0Fh
D7-D0 R/W 0
SELECTION [7:0] The 5 digital pages (Main digital, Interleaving Engine, Analog JESD, Digital
JESD, and Decimation filter) are selected via the M bit. See Serial Interface
Read/Write section for more details.
7.6.3.5 Master Page (80h)
7.6.3.5.1 Register 20h (address = 20h) [reset = 0h] , Master Page (080h)

A7-A0 in Hex 7 6 5 4 3 2 1 0
PDN ADC CHAB PDN ADC CHCD
R/W-0h R/W-0h
Table 20. Registers 20h Field Descriptions

Bit Field Type Reset Description
7-4 PDN ADC CHAB R/W 0h There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register bit 5 in address 26h.
3-0 PDN ADC CHCD R/W 0h Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
See Power-Down Mode for details.

ADS58J63

A7-A0 in Hex 7 6 5 4 3 2 1 0
PDN BUFFER CHCD PDN BUFFER CHAB 0 0 0 0
R/W-0h R/W-0h W-0h R/W-0h R/W-0h W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

7-6 PDN BUFFER CHCD R/W 0h There are two power-down masks that are controlled via the
5-4 PDN BUFFER CHAB R/W 0h
or mask 2 are selected via register address 26h, bit 5.
3 0 W 0h Power-down mask 2: addresses 23h and 24h.
2-0 0 W 0h Must write 0.
7.6.3.5.3 Register 23h (address = 23h), Master Page (080h)

A7-A0 in Hex 7 6 5 4 3 2 1 0
PDN BUFFER CHAB PDN BUFFER CHCD
R/W-0h R/W-0h W-0h R/W-0h R/W-0h W-0h

7-4 PDN ADC CHAB R/W 0h There are two power-down masks that are controlled via the
or mask 2 are selected via register bit 5 in address 26h.
3-0 PDN ADC CHCD R/W 0h Power-down mask 1: addresses 20h and 21h.

ADS58J63

A7-A0 in Hex 7 6 5 4 3 2 1 0
PDN BUFFER CHCD PDN BUFFER CHAB 0 0 0 0
R/W-0h R/W-0h W-0h R/W-0h R/W-0h R/W-0h

7-6 PDN BUFFER CHCD R/W 0h There are two power-down masks that are controlled via the
5-4 PDN BUFFER CHAB R/W 0h
or mask 2 are selected via register address 26h, bit 5.
3 0 W 0h Power-down mask 2: addresses 23h and 24h.
2-0 0 W 0h Must write 0.
7.6.3.5.5 Register 26h (address = 26h), Master Page (080h)

A7-A0 in Hex 7 6 5 4 3 2 1 0
GLOBAL OVERRIDE PDN MASK 0 0 0 0 0
PDN PDN PIN SEL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be
programmed.
7 GLOBAL PDN R/W 0h
1 = Global power-down via the SPI
This bit ignores the power-down pin control.
6 OVERRIDE PDN PIN R/W 0h 0 = Normal operation
1 = Ignores inputs on the power-down pin
This bit selects power-down mask 1 or mask 2.
5 PDN MASK SEL R/W 0h 0 = Power-down mask 1
1 = Power-down mask 2
4-0 0 R/W 0h Must write 0

ADS58J63
7.6.3.5.6 Register 3Ah (address = 3Ah) [reset = 0h] , Master Page (80h)
Figure 100. Register 3Ah

A7-A0 in Hex 7 6 5 4 3 2 1 0
MASTER PAGE (80h)
3Ah 0 BUFFER 0 0 0 0 0 0
CURR
INCREASE
Table 25. Register 3Ah Field Descriptions

7, [5-0] 0 W 0h Must write 0
0 = normal operation
BUFFER CURR 1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for second
6 R/W 0h
INCREASE Nyquist application. Ensure that regiset bit INPUT BUF CUR EN is also set to
1.

A7-A0 in Hex 7 6 5 4 3 2 1 0
MASTER PAGE (80h)
39h ALWAYS WRITE 1 0 0 0 0 0 0

[7:5] ALWAYS WRITE 1 R/W 0h Always set these bits to 11.
[5-0] 0 W 0h Must write 0
Figure 102. Register 53h Register

A7-A0 in Hex 7 6 5 4 3 2 1 0
MASTER PAGE (80h)
53h CLK DIV MASK 0 0 0 0 0 0
SYSREF

Configures input clock divider
7 CLK DIV R/W 0 0 = Divide by 4
1= Divide by 2 (must be enabled for proper operation of ADS58J63)
6 MASK SYSREF R/W 0
1 = ignores SYSREF input

ADS58J63

A7-A0 in Hex 7 6 5 4 3 2 1 0
MASTER PAGE (80h)
55h 0 0 0 PDN MASK 0 0 0 0

4 PDN MASK R/W 0 Power down via register bit
1 = power down enabled powering down internal blocks specified in the
selected power down mask

A7-A0 in Hex 7 6 5 4 3 2 1 0
MASTER PAGE (80h)
56h 0 0 0 0 INPUT BUFF 0 0 0
CURR EN

3 INPUT BUFF CURR EN R/W 0 0 = normal operation
1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for
second Nyquist application. Ensure that regiset bit BUFFER CURR
INCREASE is also set to 1.

A7-A0 in Hex 7 6 5 4 3 2 1 0
MASTER PAGE (80h)
39h 0 0 ALWAYS 0 0 0 0 0
WRITE 1

5 ALWAYS WRITE 1 R/W 0h Always set these bits to 1.

ADS58J63
7.6.3.6 ADC Page (0Fh)
7.6.3.6.1 Register 5Fh (address = 5Fh) [reset = 0h] , ADC Page (0Fh)
Figure 106. Register 5Fh

A7-A0 in Hex 7 6 5 4 3 2 1 0
ADC Page (0Fh)
5Fh FOVR CHCD THRESH
Table 31. Register 5Fh Field Descriptions

Controls the location of FAST OVR threshold for channel C and D. Refer to
D [7:0] FOVR CHCD THRESH R/W 0h
Over-range Indication.
7.6.3.6.2 Register 60h (address = 60h) [reset = 0h] , ADC Page (0Fh)

A7-A0 in Hex 7 6 5 4 3 2 1 0
ADC Page (0Fh)
60Fh 0 0 0 PULSE BIT 0 0 0 0
CHC

Pulse (1) this bit to improve HD3 for 2nd Nyquist frequiencies (fIN > 250 MHz)
4 PULSE BIT CHC R/W 0h for channel C.
Before pulsing this bit, register bit HD3 NYQ2 CHCD must be set to 1.
(1) Pulsing = Set the bit to 1 and then reset to 0.
7.6.3.6.3 Register 60h (address = 61h) [reset = 0h], ADC Page (0Fh)

A7-A0 in Hex 7 6 5 4 3 2 1 0
ADC Page (0Fh)
61Fh 0 0 0 HD3 NYQ2 0 0 0 PULSE BIT
CHCD CHD

Se this bit to improve HD3 for 2nd Nyquist frequiencies (fIN > 250 MHz) for
4 HD3 NYQ2 CHCD R/W 0h channel C and D. Once this bit is set, it is required to pulse the PULSE BIT
CHx register bits to see the improvement in corresponding channels.
0 PULSE BIT CHD R/W 0h for channel D.
Before pulsing this bit, register bit HD3 NYQ2 CHCD must be set to 1.

ADS58J63
7.6.3.6.4 Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)
Figure 109. Register 6Ch

A7-A0 in Hex 7 6 5 4 3 2 1 0
ADC Page (0Fh)
6Ch 0 0 0 PULSE BIT 0 0 0 0
CHA
Table 34. Register 6Ch Field Descriptions

4 PULSE BIT CHA R/W 0h for channel A.
Before pulsing this bit, register bit HD3 NYQ2 CHCAB must be set to 1.
7.6.3.6.5 Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)
Figure 110. Register 6Dh

A7-A0 in Hex 7 6 5 4 3 2 1 0
ADC Page (0Fh)
6Dh 0 0 0 HD3 NYQ2 0 0 0 PULSE BIT
CHAB CHB
Table 35. Register 6Dh Field Descriptions

Se this bit to improve HD3 for 2nd Nyquist frequiencies (fIN > 250 MHz) for
4 HD3 NYQ2 CHAB R/W 0h channel A and B. Once this bit is set, it is required to pulse the PULSE BIT
CHx register bits to see the improvement in corresponding channels.
0 PULSE BIT CHB R/W 0h for channel B.
Before pulsing this bit, register bit HD3 NYQ2 CHAB must be set to 1.

ADS58J63
7.6.3.6.6 Register 74h(address = 74h) [reset = 0h], ADC Page (0Fh)

A7-A0 in Hex D7 D6 D5 D4 D3 D2 D1 D0
ADC Page (0Fh)
74 TEST PATTERN ON CHANNEL 0 0 0 0

Test pattern output on channel A and B
0000 Normal Operation using ADC output data
0001 Outputs all 0s
0010 Outputs all 1s
0011 Outputs toggle pattern: Output data are an alternating sequence of
101010101010 and 010101010101
TEST PATTERN ON 0100 Output digital ramp: output data increments by one LSB every clock
D7-D4 R/W 0000
CHANNEL cycle from code 0 to 16384
0110 Single pattern: output data is custom pattern 1 (75h and 76h)
0111 Double pattern: output data alternates between custom patter 1 and
custom pattern 2
1000 Deskew pattern: output data is 2AAAh
1001 SYNC pattern: output data is 3FFFh
See ADC Test Pattern for more details.
7.6.3.6.7 Register 75h/76h/77h/78h (address = 75h/76h/77h/78h) [reset = 0h], ADC Page (0Fh)
Figure 112. Register 75h/76h/77h/78h

A7-A0 in Hex D7 D6 D5 D4 D3 D2 D1 D0
ADC Page (0Fh)
75 CUSTOM PATTERN 1[13:6]
76 CUSTOM PATTERN 1[ 5:0] 0 0
77 CUSTOM PATTERN 2[13:6]
78 CUSTOM PATTERN 2[ 5:0] 0 0
LEGEND: R/78W = Read/Write; -n = value after reset
Table 37. Register 75h/76h/77h/78h Field Descriptions

7-0 CUSTOM PATTERN R/W 0 Address 75/76/77/78
Sets the custom pattern (13:6, 5:0) for all channels.
See ADC Test Pattern for more details.

ADS58J63
7.6.3.7 Interleaving Engine Page (6100h)
7.6.3.7.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)

18 0 0 0 0 0 0 IL BYPASS

Allows bypassing of the interleaving correction. To be used when ADC
test patterns are enabled.
D1-D0 IL BYPASS R/W 00
00 = interleaving correction enabled
11= interleaving correction bypassed
7.6.3.7.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)

68 0 0 0 0 0 DC CORR DIS 0

Enables DC offset correction loop.
00 = DC offset correction enabled
D2 DC CORR DIS R/W 0
11 = DC offset correction disabled
Others = Do not use

ADS58J63
7.6.3.8 Decimation Filter Page (6141h) Registers
7.6.3.8.1 Register 0h (address = 0h) [reset = 0h]

0 CHB/C FINE MIX DDC MODE
Table 40. 0h Field Descriptions

Selects fine mixing frequency for N × fS/16 mixer where N is a 2's complement number
varynig from -8 to 7.
0000 = N is 0
0001 = N is 1
0010 = N is 2
D7-D4 CHB/C FINE MIX R/W 0000
...
0111 = N is 7
1000 = N is -8
...
1111 = N is -1
Selects the DDC Mode for all channels
SETTING MODE DESCRIPTION
000 0 fS/4 mixing with decimation by 2, complex output
001 – N/A
010 2 Decimation by 2, high or low pass filter, real output
011 – N/A
D3-D0 DDC MODE R/W 0h 100 4 Decimation by 2, N × fS/16 mixer, real output
101 5 Decimation by 2, N × fS/16 mixer, complex output
6 Decimation by 4, N × fS/16 mixer, complex output.
110 Ensure that register bits DDC MODE 6 EN [3:1 ] are
also set to '111'.
111 7 Decimation by 2, N × fS/16 mixer, insert 0, real output
1000 8 14-bit burst mode selected.
Others – Do not use

ADS58J63

1 0 0 0 0 DDC MODE6 ALWAYS CHB/C HPF CHB/C
EN1 WRITE 1 EN COARSE MIX

D7-D4 0 W 0
Set this bit aong with register bits DDC MODE6 EN2 and DDC
MODE6 EN3 for proper operation of Mode 6.
D3 DDC MODE6 EN1 R/W 0
0 = Default
1 = Use for proper operation of DDC Mode 6.
D2 ALWAYS WRITE 1 R/W 0 Always write this bit to 1.
Enables high pass filter for DDC Mode 2 for channel B and C.
D1 CHB/C HPF EN R/W 0 0 = Low pass filter enabled
1 = High pass filter enabled
Selects fS/4 mixer phase for DDC Mode 0 for channel B and C.
D0 CHB/C COARSE MIX R/W 0 0 = Mix with +fS/4
1 = Mix with –fS/4

2 0 0 CHA/D HPF CHA/D CHA/D FINE MIX
EN COARSE
MIX

D7-D6 0
CHA/D HPF EN Enables high pass filter for DDC Mode 2 for channel A and D.
D5 R/W 0 0 = Low pass filter enabled
1 = High pass filter enabled
CHA/D COARSE MIX Selects fS/4 mixer phase for DDC Mode 0 for channel A and D.
D4 R/W 0 0 = Mix with +fS/4
1 = Mix with –fS/4
Selects fine mixing frequency for N × fS/16 mixer where N is a
2's complement number varynig from -8 to 7.
0000 = N is 0
0001 = N is 1
0010 = N is 2
D3-D0 CHA/D FINE MIX R/W 0000
...
0111 = N is 7
1000 = N is -8
...
1111 = N is -1

ADS58J63
7.6.3.9 Main Digital Page (6800h) Registers
7.6.3.9.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)

0 0 0 0 0 0 0 0 IL RESET

Resets the interleaving engine. This bit is not a self-clearing bit
and must be pulsed (1).
Any register bit in Main Digital Page (6800h) takes effect only
D0 IL RESET R/W 0 after this bit is pulsed. Also, note that pulsing this bit clears
registers in interleaving page (6100h).
0 → 1 → 0 = interleaving engine reset.
7.6.3.9.2 Register 42h(address = 42h) [reset = 0h], Main Digital Page (6800h)

42 0 0 0 0 0 NYQUIST ZONE

Provide Nyquist zone information to IL engine. Ensure that register bit CTRL
NYQUIST is set to 1.
000 = 1st Nyquist zone (input frequencies between 0 to fS/2)
NYQUIST
D2-D0 R/W 000 001 = 2nd Nyquist zone (input frequencies between fS/2 to fS)
ZONE
010 = 3rd Nyquist zone (input frequencies between fS to 3fS/2)
...
111 = 8th Nyquist zone (input frequencies between 7fS/2 to 4fS)
7.6.3.9.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)
Figure 120. Register 4Eh

4E CTRL 0 0 0 0 0 0 0
NYQUIST
Table 45. Register 4Eh Field Descriptions

Enables Nyquist zone control using register bits NYQUIST ZONE.
D7 CTRL NYQUIST R/W 0 0 = Selection disabled
1 = Selection enabled

ADS58J63
7.6.3.9.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)
Figure 121. Register ABh

AB 0 0 0 0 0 0 0 OVR EN
Table 46. Register ABh Field Descriptions

Set this bit to enable register bit OVR ON LSB.
D0 OVR EN R/W 0 0 = normal operation
1 = OVR ON LSB enabled
7.6.3.9.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)
Figure 122. Register ADh

AD 0 0 0 0 OVR ON LSB
Table 47. Register ADh Field Descriptions

Set this bit to bring OVR on two LSBs of 16-bit output. Ensure that register bit OVR
EN is set to 1
0000 = Bits D0 and D1 of 16-bit data are noise bits
D0 OVR EN R/W 0
0011 = OVR comes on bit D0 of 16-bit data
1100 = OVR comes on bit D1 of 16-bit data
1111 = OVR comes on both D0 and D1 bits of 16-bit data
7.6.3.9.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)
Figure 123. Register F7h

F7 0 0 0 0 0 0 0 DIG RESET
Table 48. Register F7h Field Descriptions

Self clearing reset for the digital block. Does not include the interleaving correction.
D0 DIG RESET R/W 0 0 = normal operation
1 = digital reset

ADS58J63
7.6.3.10 JESD Digital Page (6900h) Registers
7.6.3.10.1 Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)

0 CTRL K JESD MODE DDC MODE6 TESTMODE 0 LANE ALIGN FRAME TX LINK DIS
EN EN2 EN ALIGN

Enable bit for a number of frames per multi frame.
D7 CTRL K R/W 0 0 = Default is 5 frames per multi frame
1 = Frames per multi frame can be set in register 06h
Allows changing the JESD MODE setting in register 01h (D1-D0)
JESD MODE
D6 R/W 0 0 = Disabled
EN
1 = Enables changing the JESD MODE setting
Set this bit aong with register bits DDC MODE6 EN1 and DDC MODE6 EN3 for
DDC MODE6 proper operation of Mode 6.
D5 R/W 0
EN2 0 = Default
This bit generates the long transport layer test pattern mode, as per section 5.1.6.3 of
the JESD204B specification.
D4 TESTMODE EN R/W 0
0 = Test mode disabled
1 = Test mode enabled
This bit inserts the lane alignment character (K28.3) for the receiver to align to lane
boundary, as per section 5.3.3.5 of the JESD204B specification.
D2 LANE ALIGN R/W 0
1 = Inserts lane alignment characters
This bit inserts the lane alignment character (K28.7) for the receiver to align to lane
boundary, as per section 5.3.3.5 of the JESD204B specification.
D1 FRAME ALIGN R/W 0
1 = Inserts frame alignment characters
This bit disables sending the initial link alignment (ILA) sequence when SYNC is de-
asserted.
D0 TX LINK DIS R/W 0
1 = ILA disabled

ADS58J63

1 SYNC REG SYNC REG SYNCB SEL 0 DDC MODE6 0 JESD MODE
EN AB/CD EN3

SYNC Register (Bit D6 must be enabled)
D7 SYNC REG R/W 0 0 = Normal operation
1 = ADC output data are replaced with K28.5 characters.
Enables bit for SYNC operation
D6 SYNC REG EN R/W 0 0 = Normal operation
1 = ADC output data over-write enabled
Selects which SYNCb input controls the JESD interface. Needs to be configured for
SYNCB SEL chAB and chCD
D5 R/W 0
AB/CD 0 = SYLNCbAB
1 = SYNCbCD
Set this bit aong with register bits DDC MODE6 EN1 and DDC MODE6 EN2 for
DDC MODE6 proper operation of Mode 6.
D5 R/W 0
EN3 0 = Default
Selects number of serial JESD output lanes per ADC. Also need to set the JESD
MODE EN (00h) and JESD PLL MODE register (JESD ANALOG page, register 16h)
accordingly.
D1-D0 JESD MODE R/W 0 01 = 20x mode
10 = 40x mode
11 = 80x mode
All others = Not used

2 LINK LAYER TESTMODE LINK LAYER LMFC MASK 0 0 0
RPAT RESET

These bits generate a pattern according to clause 5.3.3.8.2 of
the JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
D7-D5 LINK LAYER TESTMODE R/W 000
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character
and continuously repeats lane alignment sequences)
100 = 12 octet RPAT jitter pattern
This bit changes the running disparity in the modified RPAT
pattern test mode (only when the link layer test mode = 100).
D4 LINK LAYER RPAT R/W 0
1 = Changes disparity
0 = Default
D3 LMFC MASK RESET R/W 0
1 = Resets LMFC mask

ADS58J63

3 FORCE LMFC COUNT INIT RELEASE ILANE SEQ
LMFC
COUNT

Force LMFC count.
D7 FORCE LMFC COUNT R/W 0
1 = Enables using a different starting value for the LMFC
counter
SYSREF coming to the digital block will reset the LMFC count to
0 and K28.5 will stop coming when the LMFC count reaches 31.
The initial value to which LMFC count resets to can be set using
D6-D2 LMFC COUNT INIT R/W 00000
LMFC COUNT INIT. This way the Rx can get synchronized early
since it will get the LANE ALIGNMENT SEQUENCE early.
Register bit FORCE LMFC COUNT must be enabled.
Delays the generation of lane alignment sequence by 0, 1, 2, or
3 multi frames after code group synchronization.
00 = 0
D1-D0 RELEASE ILANE SEQ R/W 00
01 = 1
10 = 2
11 = 3

5h SCRAMBLE 0 0 0 0 0 0 0
EN

Scramble enable bit in the JESD204B interface.
D7 SCRAMBLE EN R/W 0 = Scrambling disabled
1 = Scrambling enabled

ADS58J63

6 0 0 0 FRAMES PER MULTI FRAME (K)

D7-D5
FRAMES PER MULTI set the number of multi frames.
D4-D0 R/W 00000
FRAME (K) Actual K is the value in hex + 1 (that is, 0Fh is K = 16).

17 HIRES FLAG ON LSB 0 TRIG SET AUTO TRIG 0 RATIO 0
AB/CD EN INVALID

Applicable only in 14-bit Burst mode. Program two LSBs of 16-bit data as flag
for 14-bit high resolution samples. Flag is '1' when the sample belongs to 14-
bit resolution.
D7 - D6 HIRES FLAG ON LSB R/W 0 00 = LSB Bits D0 and D1 of 16-bit data noise bits.
01 = Bit D0 carries high-resolution flag.
10 = Bit D1 carries high-resolution flag.
11 = Both bits D0 and D1 carry high-resolution flag.
TRIG SET AB/CD Determines if triggerAB or triggerCD pin is used for burst mode. Needs to be
configured individually for chAB and chCD with paging.
D4 R/W 0
0 = uses TRIGGERAB pin
1 = uses TRIGGERCD pin
Enables automatic trigger in burst mode (ignores TRIGGERAB/CD inputs)
D3 AUTO TRIG EN R/W 0 0 = auto trigger disabled
1= auto trigger enabled
RATIO INVALID Alarm flag when duty cycle ratio between high and low resolution counter is
D1 R/W 0
set incorrectly.

ADS58J63
7.6.3.10.8 Register 19h/1Ah/1Bh/1Ch (address = 19h/1Ah/1Bh/1Ch) [reset = 0h], JESD Digital Page (6900h)
Figure 131. Register 19h/1Ah/1Bh/1Ch

19 0 0 0 0 LC[27:24]
1A LC[23:16]
1B LC[15:8]
1C LC[7:0]
Table 56. 19h/1Ah/1Bh/1Ch Field Descriptions

LC [xx:xx] Sets the low resolution counter value. While programming LC[27:0], first
D7-D0 R/W 0 program LC[7:0], then LC[15:8], then LC[23:16], and then LC[27:24] in the
same order.
7.6.3.10.8.1 Register 1Dh/1Eh/1Fh/20h (address = 1Dh/1Eh/1Fh/20h) [reset = 0h], JESD Digital Page (6900h)
Figure 132. Register 1Dh/1Eh/1Fh/20h

1D 0 0 0 0 HC[27:24]
1E HC[23:16]
1F HC[15:8]
20 HC[7:0]
Table 57. 1Dh/1Eh/1Fh/20h Field Descriptions

HC [xx:xx] Sets the high resolution counter value. While programming HC[27:0], first
D7-D0 R/W 0 program HC[7:0], then HC[15:8], then HC[23:16], and then HC[27:24] in
the same order.

ADS58J63
7.6.3.10.8.2 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)

21 OUTPUT CHA MUX SEL OUTPUT CHB MUX SEL OUTPUT CHC MUX SEL OUTPUT CHD MUX SEL

Serdes lane swap with chB
00 = ChA is output on lane DA
D7-D6 OUTPUT CHA MUX SEL R/W 00
10 = ChA is output on lane DB
01/11 = Do not use
Serdes lane swap with chA
00 = ChB is output on lane DB
D5-D4 OUTPUT CHB MUX SEL R/W 00
10 = ChB is output on lane DA
01/11 = Do not use
Serdes lane swap with chD
00 = ChC is output on lane DC
D3-D2 OUTPUT CHC MUX SEL R/W 00
10 = ChC is output on lane DD
01/11 = Do not use
Serdes lane swap with chC
00 = ChD is output on lane DD
D1-D0 OUTPUT CHD MUX SEL R/W 00
10 = ChD is output on lane DC
01/11 = Do not use

ADS58J63
7.6.3.10.8.3 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)

22 0 0 0 0 OUT CHA OUT CHB OUT CHC OUT CHD INV
INV INV INV

D7-D4 0
Polarity inversion of JESD output of chA
D3 OUT CHA INV R/W 0 0 = normal operation
1 = output polarity inverted
Polarity inversion of JESD output of chB
D2 OUT CHB INV R/W 0 0 = normal operation
Polarity inversion of JESD output of chC
D1 OUT CHC INV R/W 0 0 = normal operation
Polarity inversion of JESD output of chD
D0 OUT CHD INV R/W 0 0 = normal operation
7.6.3.11 JESD Analog Page (6A00h) Register
7.6.3.11.1 Register 12h/13h (address 12h/13h) [reset = 0h], JESD Analog Page (6Ah)
Figure 135. Register 12h/13h

12 SEL EMP LANE DA/DD 0 0
13 SEL EMP LANE DB/DC 0 0
Table 60. 12h/13h Field Descriptions

Selects the amount of de-emphasis for the JESD output transmitter. The
de-emphasis value in dB is measured as the ratio between the peak
value after the signal transition to the settled value of the voltage in one
bit period.
SEL EMP LANE DA/DD 0 = 0 dB
D7-D2 R/W 000000 1 = –1 dB
SEL EMP LANE DB/DC 3 = –2 dB
7 = –4.1 dB
15 = –6.2 dB
31 = –8.2 dB
63 = –11.5 dB

ADS58J63
7.6.3.11.2 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)

16 0 0 0 0 0 0 JESD PLL MODE

D7-D1
Selects the JESD PLL multiplication factor
D0 JESD PLL MODE R/W 0 0 = 20x mode
1 = 40x mode
7.6.3.11.3 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6Ah)
Figure 137. Register 1Bh

JESD ANALOG PAGE (6Ah)
1B JESD SWING 0 0 0 0 0
Table 62. 1Bh Field Descriptions

Programs SERDES output swing
0 = 860 mVPP
1 = 810 mVPP
2 = 770 mVPP
D7-D5 JESD SWING R/W 000 3 = 745 mVPP
4 = 960 mVPP
5 = 930 mVPP
6 = 905 mVPP
7 = 880 mVPP
D4-D3 0

ADS58J63
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

8.1.1 Start-Up Sequence
The following steps are recommended as the power up sequence with the ADS58J63 in 2x complex decimation
mode (DDC Mode 0) with LMFS = 4841 (shown in Table 63).
Table 63. Recommended Power-Up Sequence

REGISTER REGISTE
STEP DESCRIPTION COMMENT
ADDRESS R DATA
1 Supply all supply voltages. There is no — — —
required power supply sequence for the 1.15-
V supply, 1.9-V supply and 3-V supply, and
these may be supplied in any order.
2 Pulse a hardware reset (low to high to low) on — — —
pin 48.
Alternatively it can be reset with: 00h 81h
Analog reset and Digital reset 4004h 68h
4003h 00h
4002h 00h
4001h 00h
60F7h 01h
3 Set input clock divider 11h 80h Select master page
53h 80h Set clock divider to /2
4 Reset interleaving correction engine. Register 6000h 01h Channel AB (and channel CD since device
access default into page 68h 6000h 00h is in broadcast mode)
5 Default registers for JESD analog page 4003h 00h Select JESD analog page
4004h 6Ah m
6016h 02h PLL mode 40x for Channel AB and CD
6 Default registers for JESD digital page 4003h 00h Select JESD digital page
4004h 69h m
6000h 80h Set CTRL K for channel AB and CD
6006h 0Fh Set K to 16
7 Enable single SYNCb input (SYNCAB) 4005h 01h Disable broadcast mode
7001h 22h Use SYNCAB for channel C/D
8 Pulse SYNCb (pin 55/56) from low to high to — — —
transmit data from k28.5 sync mode

ADS58J63
8.1.2 Hardware Reset
Power Supplies
t1
RESET
t2 t3
SEN
Figure 138. Hardware Reset Timing Diagram
Table 64. Timing Requirements for Figure 138

MIN TYP MAX UNIT
t1 Power-on delay Delay from power up to active high RESET pulse 1 ms
t2 Reset pulse duration Active high RESET pulse duration 10 ns
t3 Register write delay Delay from RESET disable to SEN active 100 ns
8.1.3 SNR and Clock Jitter

The signal to noise ratio of the ADC is limited by three different factors: the quantization noise is typically not
noticeable in pipeline converters and is 84 dB for a 14-bit ADC. The thermal noise limits the SNR at low input
frequencies while the clock jitter sets the SNR for higher input frequencies.
(2)
The SNR limitation resulting from sample clock jitter can be calculated following:
(3)
The total clock jitter (TJitter) has two components – the internal aperture jitter (120 fs for ADS58J63) which is set
by the noise of the clock input buffer and the external clock jitter. It can be calculated as following:
(4)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input while a faster clock slew rate also improves the ADC aperture jitter.
The ADS58J63 has a thermal noise of approximately 72 dBFS and an internal aperture jitter of 120 fs.

ADS58J63
8.1.4 ADC Test Pattern

The ADS58J63 provides several different options to output test patterns instead of the actual output data of the
ADC in order to simplify bring up of the JESD204B digital interface link. The output data path is shown in
Figure 139
ADC Section Transport Layer Link Layer PHY Layer
DDC
ADC Data Mapping
Frame 8b/10b
Interleaving Construction
Burst encoding
Correction Scrambler
Mode
1+x14+x15 Serializer
ADC Test JESD204B Long
JESD204B
Pattern Transport Layer
Link Layer
Test Pattern
Test Pattern
Figure 139. ADC Test Pattern
8.1.4.1 ADC Section

The ADC test pattern replaces the actual output data of the ADC. The following test patterns are available in
register 74h. In order to get the test pattern output propoerly, the interleaving correction needs to be disabled
(6100h, address 18h) and burst mode enabled (DDC disabled).
Burst mode only supports LMFS = 4421 (DDC Modes have different configurations) and test pattern switches
between 9-bit (low resolution) and 14-bit (high resolution) output. See Table 65
Table 65. ADC Test Pattern Settings

Bit Name Default Description
Test pattern output on channel A and B
0000 Normal Operation using ADC output data
0001 Outputs all 0s
0010 Outputs all 1s
0011 Outputs toggle pattern: Output data are an
alternating sequence of 101010101010 and
010101010101
D7-D4 TEST PATTERN 0000 0100 Output digital ramp: output data increments by
one LSB every clock cycle from code 0 to 16384
0110 Single pattern: output data is custom pattern 1
(75h and 76h)
0111 Double pattern: output data alternates between
custom patter 1 and custom pattern 2
1000 Deskew pattern: output data is 2AAAh
1001 SYNC pattern: output data is 3FFFh
8.1.4.2 Transport Layer Pattern

The Transport Layer maps the ADC output data into 8bit octets and constructs the JESD204B frames using the
LMFS parameters. Tail bits or ‘0’s are added when needed. Alternatively the JESD204B long transport layer test
pattern can be substituted as shown in Table 66 .
Table 66. Transport Layer Test-mode

Generates long transport layer test pattern mode
according to clause 5.1.6.3 of JESD204B specification
D4 TESTMODE EN 0
0 = test mode disabled
1 = test mode enabled

ADS58J63
8.1.4.3 Link Layer Pattern

The Link Layer contains the scrambler and the 8b/10b encoding of any data passed on from the Transport Layer.
Additionally it also handles the initial lane alignment sequence which can be manually restarted. The Link Layer
test patterns are intended for testing the quality of the link (jitter testing etec). The test patterns do not pass
through the 8b/10b encoder and contain the options shown in Table 67.
Table 67. Link Layer Test-mode

Generates pattern according to clause 5.3.3.8.2 of the
JESD204B document
000 normal ADC data
001 D21.5 (high frequency jitter pattern)
D7-D5 LINK LAYER TESTMODE 000 010 K28.5 (mixed frequency jitter pattern)
011 Repeat initial lane alignment (generates K28.5
character and repeat lane alignment sequences
continuously)
100 12 octet RPAT jitter pattern
Furthermore a 215 PRBS can be enabled by setting up a custom test pattern (AAAA) in the ADC section and
running that through the 8b/10b encoder with scrambling enabled.

ADS58J63
8.2 Typical Application

The ADS58J63 is designed for wideband receiver applications demanding excellent dynamic range over a large
input frequency range. A typical schematic for an AC coupled dual receiver (dual FPGA with dual SYNC) is
shown below.
DVDD
25 25 10 k
0.1 uF
Driver 0.1 uF 3.3 pF
25 GND
5 25 SPI Master
GND
GND 0.1 uF IOVDD GND
0.1 uF 0.1 uF
AVDD3V 0.1 uF
AVDD
AVDD
5 AVDD3V DVDD
AVDD3V
TRDYCD
TRIGCD
AVDD3V
IOVDD
SDOUT
25 25
DGND
DVDD
AVDD
AVDD
AVDD
AVDD
SCLK
INCM
INDM
INDP
SDIN
SEN
0.1 uF
Driver 0.1 uF 3.3 pF 100 Differential
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
25 5 25
GND INCP SYNCbCDP
19 72
50
Vterm=1.2 V
AVDD SYNCbCDM 50
AVDD 20 71
0.1 uF
GND
AGND
21 70
IOVDD IOVDD FPGA
10 nF 10 nF
NC DDP GND
22 69
NC DDM
GND 23 68
0.1 uF
AVDD3V DGND
AVDD3V 24 67
GND 10 nF
AVDD DCP
AVDD 25 66
0.1 uF
AGND DCM
GND 26 65
10 nF
CLKINP IOVDD IOVDD
27 64
100
CLKINM
28
ADS58J63 63
DGND
0.1 uF
GND
AGND DBM
GND 29 62
GND PAD (backside)
Low Jitter 0.1 uF
AVDD
AVDD
30 61
DBP
Clock AVDD3V DGND

AVDD3V 31 60 10 nF
Generator 0.1 uF
DAM
GND
AGND
GND 32 59
SYSREFP DAP
33 58
100 IOVDD
SYSREFM IOVDD 10 nF
34 57
AVDD 10 nF
AVDD SYNCbABM GND
35 56
50
5 INBP
36 55
SYNCbABP 50 Vterm=1.2 V
FPGA
25 25
0.1 uF 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
0.1 uF 100 Differential
Driver 3.3 pF
INBM
AVDD
AVDD3V
AVDD
INAM
INAP
AVDD
AVDD
AVDD3V
AVDD
DVDD
RESET
SCAN_EN
PDN
IOVDD
DGND
TRIGAB
TRDYAB
25 5 25
GND
AVDD3V
AVDD DVDD
AVDD
AVDD3V 0.1 uF
GND GND
0.1 uF IOVDD GND
0.1 uF
GND
5
25 25
0.1 uF
Driver 0.1 uF 3.3 pF
25 GND 25
5
GND = AGND + DGND connected in Layout
NOTE: GND = AGND and DGND connected in the PCB layout.
Figure 140. Application Diagram ADS58J63
8.2.1 Design Requirements

By using the simple drive circuit of Figure 140 (when AMP drives ADC) or Figure 51 (when transformers drive
ADC), uniform performance can be obtained over a wide frequency range. The buffers present at the analog
inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.
8.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves the
common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with
each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 140.

ADS58J63
Typical Application (continued)

8.2.3 Application Curves
Figure 141 and Figure 142 show the typical performance at 190 MHz and 230 MHz, respectively.
0 0
-20 -20
Amplitude (dBFS)
Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
-100 -100
-120 -120
0 50 100 150 200 250 0 50 100 150 200 250
9 Power Supply Recommendations

The device requires a 1.9-V nominal supply for DVDD, a 1.9-V nominal supply for AVDD, and a 3-V nominal
supply for AVDD3V. There is no specific sequence for power-supply requirements during device power-up.
AVDD, DVDD, and AVDD3V can power-up in any order.

ADS58J63
10 Layout
10.1 Layout Guidelines

The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A
layout diagram of the EVM top layer is provided in Figure 143. Complete layout of EVM is available at
ADS58J63's EVM folder. Some important points to remember during board layout are:
• Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package
level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as shown
in the reference layout of Figure 143 as much as possible.
• In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of Figure 143
as much as possible.
• Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output
traces must not be kept parallel to the analog input traces because this configuration can result in coupling
from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver
[such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be
matched in length to avoid skew among outputs.
• At each power-supply pin (AVDD, DVDD, or AVDDD3V), keep a 0.1-µF decoupling capacitor close to the
device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF
capacitors can be kept close to the supply source.
10.2 Layout Example
Figure 143. ADS58J63 EVM Layout

ADS58J63
11 Device and Documentation Support
11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 23-Aug-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
ADS58J63IRMPR ACTIVE VQFN RMP 72 1500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ58J63
& no Sb/Br)
ADS58J63IRMPT ACTIVE VQFN RMP 72 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ58J63
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 23-Aug-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Feb-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS58J63IRMPR VQFN RMP 72 1500 330.0 24.4 10.25 10.25 2.25 16.0 24.0 Q2
ADS58J63IRMPT VQFN RMP 72 250 180.0 24.4 10.25 10.25 2.25 16.0 24.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Feb-2017
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS58J63IRMPR VQFN RMP 72 1500 336.6 336.6 31.8
ADS58J63IRMPT VQFN RMP 72 250 213.0 191.0 55.0
Pack Materials-Page 2
PACKAGE OUTLINE
RMP0072A SCALE 1.700
VQFN - 0.9 mm max height
VQFN
10.1 A
B
9.9
PIN 1 ID
10.1
9.9
0.9 MAX
0.05
0.00 C
SEATING PLANE
0.08 C
(0.2)
4X (45 X0.42)
19 36
18 37
4X SYMM
8.5 0.1
8.5
PIN 1 ID
(R0.2)
1 54
0.30
68X 0.5 72 55 72X
0.18
SYMM 0.5 0.1 C B A
72X
0.3 0.05 C
4221047/B 02/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RMP0072A VQFN - 0.9 mm max height
VQFN
( 8.5)
SYMM
72X (0.6)
SEE DETAILS
72 55
1
54
72X (0.24)
(0.25) TYP
(9.8)
SYMM
(1.315) TYP
68X (0.5)
( 0.2) TYP
VIA
18 37
19 36
(1.315) TYP
(9.8)
LAND PATTERN EXAMPLE

SCALE:8X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
METAL SOLDER MASK
OPENING
SOLDER MASK
OPENING METAL
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4221047/B 02/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RMP0072A VQFN - 0.9 mm max height
VQFN
(9.8)
72X (0.6) (1.315) TYP

72 55
1
54
72X (0.24)
(1.315)
TYP
(0.25) TYP
SYMM
(9.8)
(1.315)
TYP
68X (0.5)
METAL
TYP
18 37
( 0.2) TYP
VIA 19 36
36X ( 1.115)
(1.315) TYP
SYMM
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
62% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
4221047/B 02/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
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TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
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Copyright © 2017, Texas Instruments Incorporated

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ADS58J63 Quad-Channel, 14-Bit, 500-MSPS Telecom Receiver Device

– SNR: 70.4 dBFS

– fIN = 370 MHz IF at –3 dBFS: INBP/M

– NSD: –152.5 dBFS/Hz TRIGCD

86 dBFS (non HD2, HD3) PLL SYNCbAB

• Telecom DPD Observation Receiver

• Changed From Product Preview To Production datasheet ................................................................................................... 1

2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: ADS58J63

5 Pin Configuration and Functions

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3

4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: ADS58J63

6.2 ESD Ratings

6.3 Recommended Operating Conditions (1)

(1) SYSREF needs to be applied for the device bring up.

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5

6.4 Thermal Information

6.5 Electrical Characteristics

6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: ADS58J63

Electrical Characteristics (continued)

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7

8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: ADS58J63

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 9

6.7 Digital Characteristics

10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: ADS58J63

6.8 Timing Characteristics

(1) Overall ADC Latency = Data Latency + tPDI

Data Latency: 77 Clock Cycles TPD

SAMPLE N-1 SAMPLE N SAMPLE N+1

Figure 1. Latency Timing Diagram

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11

6.9 Typical Characteristics: 14-Bit Burst Mode

12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: ADS58J63

Typical Characteristics: 14-Bit Burst Mode (continued)

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 13

Typical Characteristics: 14-Bit Burst Mode (continued)

14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: ADS58J63

Typical Characteristics: 14-Bit Burst Mode (continued)

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Typical Characteristics: 14-Bit Burst Mode (continued)

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Typical Characteristics: 14-Bit Burst Mode (continued)

Figure 34. Performance vs Amplitude Figure 35. Performance vs Clock Amplitude

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Typical Characteristics: 14-Bit Burst Mode (continued)

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6.10 Typical Characteristics: Mode 2

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6.11 Typical Characteristics: Mode 0