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The document contains Verilog code that implements a 4-digit 7-segment display controller. It includes a clock divider module that generates a slower clock from a 100MHz clock. It also contains code for a BCD to 7-segment decoder, multiplexing the anode signals to light up each digit, and incrementing the display counter every second. A test bench is provided to test the clock divider module.

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77 views9 pages

VPP

The document contains Verilog code that implements a 4-digit 7-segment display controller. It includes a clock divider module that generates a slower clock from a 100MHz clock. It also contains code for a BCD to 7-segment decoder, multiplexing the anode signals to light up each digit, and incrementing the display counter every second. A test bench is provided to test the clock divider module.

Uploaded by

waqas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Verilog Code:

module Clock_divider(clock_in,clock_out);

input clock_in;

output clock_out; reg[27:0] counter=28'd0;

parameter DIVISOR = 28'd2;

always @(posedge clock_in)

begin

counter <= counter + 28'd1;

if(counter>=(DIVISOR-1))

counter <= 28'd0;

end

assign clock_out = (counter<DIVISOR/2)?1'b0:1'b1;

endmodule

process(LED_BCD)

begin

case LED_BCD is

when "0000" => LED_out <= "0000001"; -- "0"

when "0001" => LED_out <= "1001111"; -- "1"

when "0010" => LED_out <= "0010010"; -- "2"

when "0011" => LED_out <= "0000110"; -- "3"

when "0100" => LED_out <= "1001100"; -- "4"

when "0101" => LED_out <= "0100100"; -- "5"

when "0110" => LED_out <= "0100000"; -- "6"


when "0111" => LED_out <= "0001111"; -- "7"

when "1000" => LED_out <= "0000000"; -- "8"

when "1001" => LED_out <= "0000100"; -- "9"

when "1010" => LED_out <= "0000010"; -- a

when "1011" => LED_out <= "1100000"; -- b

when "1100" => LED_out <= "0110001"; -- C

when "1101" => LED_out <= "1000010"; -- d

when "1110" => LED_out <= "0110000"; -- E

when "1111" => LED_out <= "0111000"; -- F

end case;

end process;

process(clock_100Mhz,reset)

begin

if(reset='1') then

refresh_counter <= (others => '0');

elsif(rising_edge(clock_100Mhz)) then

refresh_counter <= refresh_counter + 1;

end if;

end process;

LED_activating_counter <= refresh_counter(19 downto 18);

-- 4-to-1 MUX to generate anode activating signals for 4 LEDs

process(LED_activating_counter)

begin
case LED_activating_counter is

when "00" =>

Anode_Activate <= "0111";

-- activate LED1 and Deactivate LED2, LED3, LED4

LED_BCD <= displayed_number(15 downto 12);

-- the first hex digit of the 16-bit number

when "01" =>

Anode_Activate <= "1011";

-- activate LED2 and Deactivate LED1, LED3, LED4

LED_BCD <= displayed_number(11 downto 8);

-- the second hex digit of the 16-bit number

when "10" =>

Anode_Activate <= "1101";

-- activate LED3 and Deactivate LED2, LED1, LED4

LED_BCD <= displayed_number(7 downto 4);

-- the third hex digit of the 16-bit number

when "11" =>

Anode_Activate <= "1110";

-- activate LED4 and Deactivate LED2, LED3, LED1

LED_BCD <= displayed_number(3 downto 0);

-- the fourth hex digit of the 16-bit number

end case;

end process;
entity seven_segment_display_VHDL is

Port ( clock_100Mhz : in STD_LOGIC;-- 100Mhz clock on Basys 3 FPGA board

reset : in STD_LOGIC; -- reset

Anode_Activate : out STD_LOGIC_VECTOR (3 downto 0);-- 4 Anode signals

LED_out : out STD_LOGIC_VECTOR (6 downto 0));-- Cathode patterns of 7-segment


display

end seven_segment_display_VHDL;

architecture Behavioral of seven_segment_display_VHDL is

signal one_second_counter: STD_LOGIC_VECTOR (27 downto 0);

-- counter for generating 1-second clock enable

signal one_second_enable: std_logic;

-- one second enable for counting numbers

signal displayed_number: STD_LOGIC_VECTOR (15 downto 0);

-- counting decimal number to be displayed on 4-digit 7-segment display

signal LED_BCD: STD_LOGIC_VECTOR (3 downto 0);

signal refresh_counter: STD_LOGIC_VECTOR (19 downto 0);

-- creating 10.5ms refresh period

signal LED_activating_counter: std_logic_vector(1 downto 0);

-- the other 2-bit for creating 4 LED-activating signals

-- count 0 -> 1 -> 2 -> 3

-- activates LED1 LED2 LED3 LED4

-- and repeat

begin
-- VHDL code for BCD to 7-segment decoder

-- Cathode patterns of the 7-segment LED display

process(LED_BCD)

begin

case LED_BCD is

when "0000" => LED_out <= "0000001"; -- "0"

when "0001" => LED_out <= "1001111"; -- "1"

when "0010" => LED_out <= "0010010"; -- "2"

when "0011" => LED_out <= "0000110"; -- "3"

when "0100" => LED_out <= "1001100"; -- "4"

when "0101" => LED_out <= "0100100"; -- "5"

when "0110" => LED_out <= "0100000"; -- "6"

when "0111" => LED_out <= "0001111"; -- "7"

when "1000" => LED_out <= "0000000"; -- "8"

when "1001" => LED_out <= "0000100"; -- "9"

when "1010" => LED_out <= "0000010"; -- a

when "1011" => LED_out <= "1100000"; -- b

when "1100" => LED_out <= "0110001"; -- C

when "1101" => LED_out <= "1000010"; -- d

when "1110" => LED_out <= "0110000"; -- E

when "1111" => LED_out <= "0111000"; -- F

end case;

end process;

-- 7-segment display controller


-- generate refresh period of 10.5ms

process(clock_100Mhz,reset)

begin

if(reset='1') then

refresh_counter <= (others => '0');

elsif(rising_edge(clock_100Mhz)) then

refresh_counter <= refresh_counter + 1;

end if;

end process;

LED_activating_counter <= refresh_counter(19 downto 18);

-- 4-to-1 MUX to generate anode activating signals for 4 LEDs

process(LED_activating_counter)

begin

case LED_activating_counter is

when "00" =>

Anode_Activate <= "0111";

-- activate LED1 and Deactivate LED2, LED3, LED4

LED_BCD <= displayed_number(15 downto 12);

-- the first hex digit of the 16-bit number

when "01" =>

Anode_Activate <= "1011";

-- activate LED2 and Deactivate LED1, LED3, LED4

LED_BCD <= displayed_number(11 downto 8);

-- the second hex digit of the 16-bit number


when "10" =>

Anode_Activate <= "1101";

-- activate LED3 and Deactivate LED2, LED1, LED4

LED_BCD <= displayed_number(7 downto 4);

-- the third hex digit of the 16-bit number

when "11" =>

Anode_Activate <= "1110";

-- activate LED4 and Deactivate LED2, LED3, LED1

LED_BCD <= displayed_number(3 downto 0);

-- the fourth hex digit of the 16-bit number

end case;

end process;

-- Counting the number to be displayed on 4-digit 7-segment Display

-- on Basys 3 FPGA board

process(clock_100Mhz, reset)

begin

if(reset='1') then

one_second_counter <= (others => '0');

elsif(rising_edge(clock_100Mhz)) then

if(one_second_counter>=x"5F5E0FF") then

one_second_counter <= (others => '0');

else

one_second_counter <= one_second_counter + "0000001";

end if;
end if;

end process;

one_second_enable <= '1' when one_second_counter=x"5F5E0FF" else '0';

process(clock_100Mhz, reset)

begin

if(reset='1') then

displayed_number <= (others => '0');

elsif(rising_edge(clock_100Mhz)) then

if(one_second_enable='1') then

displayed_number <= displayed_number + x"0001";

end if;

end if;

end process;

end Behavioral;

Test Bench for Verilog:


module tb_clock_divider;

// Inputs

reg clock_in;

// Outputs

wire clock_out;

// Instantiate the Unit Under Test (UUT)

// Test the clock divider in Verilog

Clock_divider uut (

.clock_in(clock_in),
.clock_out(clock_out)

);

initial begin

// Initialize Inputs

clock_in = 0;

// create input clock 50MHz

forever #10 clock_in = ~clock_in;

end

endmodule

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