Verilog Language: Lexical Conventions Examples
Verilog Language: Lexical Conventions Examples
Examples:
Conventions
• Keywords, e. g., module, are reserved and in all lower case • 549 // decimal number
letters. Verilog is case sensitive • 'h 8FF // hex number
• Spaces are important in that they delimit tokens in the • 'o765 // octal number
language.
• 4'b11 // 4-bit binary number 0011
• Numbers are specified in the traditional form of a series of
digits with or without a sign but also in the following form: • 3'b10x // 3-bit binary number with least significant bit
unknown
• <size><base format><number>
• 5'd3 // 5-bit decimal number
– <size>: number of bits (optional)
– <base format>: is the single character ' followed by one of the • -4'b11 // 4-bit two's complement of 0011 or 1101
following characters b, d, o and h, which stand for binary, decimal,
octal and hex, respectively.
– <number>: contains digits which are legal for the <base format>
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• Here is a structural specification of a module AND – This module has two instances of the NAND module called
NAND1 and NAND2 connected together by an internal wire w1.
obtained by connecting the output of one NAND to both
inputs of another one.
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module test_AND;
Stimulus Block:
Instance • The following module is a
// High level module to test the two other modules
reg a, b;
wire out1, out2;
high level module which
• The general form to invoke an instance of a module is : sets some test data and sets initial begin // Test data
a = 0; b = 0;
<module name> <parameter list> <instance name> (<port list>); up the monitoring of #1 a = 1;
endmodule
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• Notice that we need to hold the values a and b over time. Therefore,
we had to use 1-bit registers. reg variables store the last value that was
Output.
procedurally assigned to them (just like variables in traditional
imperative programming languages). wires have no storage capacity. Time=0 a=0 b=0 out1=1 out2=0
They can be continuously driven, e. g., with a continuous assign
Time=1 a=1 b=0 out1=1 out2=0
statement or by the output of a module, or if input wires are left
unconnected, they get the special value of x for unknown. Time=2 a=1 b=1 out1=0 out2=1
• Continuous assignments use the keyword assign whereas procedural Time=3 a=0 b=1 out1=1 out2=0
assignments have the form <reg variable> = <expression> where the
<reg variable> must be a register or memory. Procedural assignment
may only appear in initial and always constructs.
• The statements in the block of the first initial construct will be
executed sequentially, some of which are delayed by #1, i. e., one unit
of simulated time. The always construct behaves the same as the initial
construct except that it loops forever (until the simulation stops). The
initial and always constructs are used to model sequential logic (i. e.,
finite state automata).
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Procedural vs. Continuos Physical Data Types
Assignments • modeling registers (reg) and wires (wire).
• register variables store the last value that was procedurally
• Procedural assignment changes the state of a register assigned to them
– sequential logic • wire variables represent physical connections between
– Clock controlled structural entities such as gates
• Continuous statement is used to model combinational – does not store anything, only a label on a wire
logic. • The reg and wire data objects may have the following
– Continuous assignments drive wire variables and are evaluated and possible values:
updated whenever an input operand changes value. It is important 0 logical zero or false
to understand and remember the difference. 1 logical one or true
x unknown logical value
z high impedance of tristate gate
– reg variables are initialized to x at the start of the simulation. Any
– wire variable not connected to something has the x value.
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A = 3;
#1 A <= A + 1; // non-blocking procedural assignment
B <= A + 1;
#1 $display("Non-blocking: A= %b B= %b", A, B );
end
endmodule
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Timing Events
• If there is no timing control, simulation time does not
advance. Simulated time can only progress by one of the • The execution of a procedural statement can be triggered
following: with a value change on a wire or register, or the occurrence
of a named event. Some examples:
• 1. gate or wire delay, if specified. @r begin // controlled by any value change in
• 2. a delay control, introduced by the # symbol. A = B&C; // the register r
• 3. an event control, introduced by the @ symbol. end
• 4. the wait statement. @(posedge clock2) A = B&C; // controlled by positive edge of clock2
• The order of execution of events in the same clock time
may not be predictable. @(negedge clock3) A = B&C; // controlled by negative edge of clock3
• #10 A = A + 1;
forever @(negedge clock3) // controlled by negative edge of clock3
– specifies to delay 10 time units before executing the procedural
begin // This has the same effect as the previous statement
assignment statement. The # may be followed by an expression
with variables. A = B&C;
21 end 22
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