Power Electronics






Lecture 4: The MOSFET and the IGBT
Chapter 23 & 25: Mohan, Power Electronics

Erasmus Mundus Master Course in

Sustainable Transportation
and Electrical Power Systems
Dr. Giulio De Donato
Basic Structure of the Power Metal-Oxide-Semiconductor
Field Effect Transistor (1/2)
• The structure shown here is known as VDMOS,
meaning vertically diffused MOSFET.
• The doping at the source and drain is about 1019
cm-3. The doping in the p-type body is about 1016
cm-3. The doping in the drift region is about 1014
cm-3.
• The gate (aluminium or n+ polysilicon) is isolated
from the body by a 100 nm layer of SiO2
insulation.
• The application of a voltage that biases the gate
positive with respect to the source converts the
silicon surface in the p-body, beneath the oxide,
in an n-type channel. This allows current to flow
from the source to the drain.
• This structure is termed Enhancement mode n-
channel MOSFET. It is a normally-off device.

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Basic Structure of the Power Metal-Oxide-
Semiconductor Field Effect Transistor (2/2)

• The use of many small source regions (up to

250000 cells per mm2) maximizes the gate
width-to-length ratio. This in turn maximizes
the device’s gain, i.e. minimizes the on-state
resistance.
• Turn on of the parasitic npn BJT between
source and drain is avoided thanks to the
body-to-source short. As a result of this short,
there is a parasitic diode between the drain
and the source.
• Overlap of gate metallization has two
purposes:
- enhances the conductivity of the drift
region.
- acts as a field plate.

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I-V Power MOSFET Characteristics

• Output characteristics: drain current iD vs drain-to-source voltage vDS with gate-to-source

voltage VGS as a parameter.
• In switching applications, the MOSFET traverses the output characteristics from cutoff through
the active region to the ohmic region as the device turns on and back again when it turns off.
• The MOSFET is in cutoff when VGS<VGS(th). Breakdown occurs due to avalanche breakdown of
the drain-body junction.
• When the device is driven by a large VGS, it is driven into the ohmic region:

vGS VGS(th) > vDS > 0

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Inversion Layer and the Field Effect
• The gate region is composed of the gate
metallization, the SiO2 under the gate conductor
(gate oxide), and the silicon beneath the gate
oxide.
• If a small vGS is applied, a depletion region
forms at the interface between the gate oxide
and the silicon.
• As vGS is increased, the depletion layer widens
and the electric field at the oxide-silicon
interface begins to attract free electrons
(obtained by thermal ionization) as well as
repelling free holes. The free holes are pushed
into the bulk of the p-type body and are
neutralized by electrons attracted from the n+
source by the positive charge of the holes.

• For vGS ≥ VGS(th) a highly conductive electron channel at the interface, named the inversion
layer, is formed. This n-type layer connects the drain and source regions, thus allowing the flow
of current. The ability to modify the conductivity beneath the gate insulation by means of an
applied voltage is know as the field effect.

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Gate Control of Drain Current Flow

• For VGS> VGS(th) and VDS small the

MOSFET is in the ohmic region. ID is small
so the inversion layer has a uniform
thickness.
• For larger values of VDS (VGS constant) ID
increases and causes a voltage drop VCS(x)
along the channel.
• Oxide voltage:
Vox (x) = VGS VCS (x)
• The decrease in oxide voltage from source
to drain means that the thickness of the
inversion layer must also decrease from
source to drain.
• As the inversion layer thins out at the drain
end of the channel, its resistance increases
and the ID vs VDS curve begins to flatten out.

• For VDS>VGS-VGS(th), the inversion layer doesn’t reduce to zero at the drain end but maintains a
minimum thickness due to the locally large electric field that drives the current flow. The drift
velocity of the electrons saturate locally so the current remains constant for any VDS (active
region of the output characteristics).

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Circuit symbols

• The MOSFET is a majority carrier device.

• MOSFETs can have either n-channels or p-channels.
• The direction of the arrow on the lead that goes to the body region indicates the direction of the
current flow if the body-source pn-junction were forward biased by breaking the short between
the two and a forward bias voltage were applied.

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Inverse Operation
• In inverse operation, for VGS<VGS(th), the MOSFET
has a diode characteristic for caused by the
parasitic diode.
• The bipolar flow through this diode determines
the on-state behaviour of the MOSFET in reverse
direction when the channel is closed.
• Inverse operation is also possible for VGS>VGS(th),
i.e. with an open channel.
• If the channel is controlled while the inverse
diode is conducting, (VDS initially above the diode
threshold voltage), the injected charge carriers
diffuse laterally as well, thus increasing
conductivity and reducing inverse operation on-
state voltage (less than 0.1 V compared to 0.7 V).
• This technique is used in low voltage power
supplies to improve efficiency.

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Power MOSFET Cell with Parasitics

• CGS is the gate-source capacitance due to the

overlapping of gate and source metallization.
• CDS is the drain-source capacitance due to the
junction capacitance between the n- drift region
and the p body.
• CGD is the gate-drain capacitance generated by
the overlapping of the gate and drift region.
• RG is the internal resistance of the gate.
• RD is the resistance of the drift region (main part
of on-resistance).
• RW is the lateral resistance of the p-body.
• A parasitic NPN transistor is also present at the
gate side.
• RW and the base-to-collector connection of the
parasitic BJT form the inverse diode.

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Basic Structure of the Insulated Gate Bipolar
Transistor (1/2)

MOSFET IGBT
• The huge differences found in properties in the two devices results form the
different structure used with regard to the third electrode (drain for MOSFET and
collector for IGBT).
• As soon as electrons enter the p+ area of the collector region, holes will be
injected from the collector to the n- region. The injected holes will flow directly
from the drift region to the emitter-p-contact, as well as laterally below the
channel to the emitter. The drift region is flooded with holes (minority carriers).

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Basic Structure of the Insulated Gate Bipolar
Transistor (2/2)

MOSFET IGBT
• The holes conduct the biggest part of the collector current. The IGBT is a bipolar
device.
• The flood of minority carriers in the drift region causes conductivity modulation,
hence lower on-state voltage compared to MOSFETs. IGBTs can be designed for
much higher voltage and currents while having similar chip areas to MOSFETs.
• On the other hand, the minority carriers must be dissipated from the drift region
during turn-off so the switching losses are higher. Lower switching frequencies.

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I-V Power IGBT Characteristics
• Output characteristics: collector
current iC vs collector-to-emitter
voltage vCE with gate-to-emitter
voltage VGE as a parameter.
• In switching applications, the
MOSFET traverses the output
characteristics from forward-
blocking through the active
region to the saturation region
as the device turns on and back
again when it turns off.
• The IGBT is in forward blocking
when VGE<VGE(th). Breakdown
occurs due to avalanche
breakdown of the p+-well/n-drift-
area.
• When the device is driven by a
large VGE, it is driven into the
saturation region: diode-like
voltage drop VCE(sat).

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Power IGBT Cell with Parasitics
• CGE is the gate-emitter capacitance due to
the overlapping of gate and source
metallization.
• CCE is the collector-emitter capacitance due
to the junction capacitance between the n-
drift region and the p body.
• CGC is the gate-collector capacitance
generated by the overlapping of the gate and
drift region.
• RG is the internal resistance of the gate.
• RD is the resistance of the drift region .
• RW is the lateral resistance of the p-body.
• An ideal MOSFET is also present.
• A parasitic NPN transistor is also present at
the gate side.
• A parasitic PNP transistor is present, which in
combination with the NPN transistor forms a
thyristor circuit. Thyristor latch-up is avoided
by using appropriate design measures.

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Generic-Switch Switching Characteristics (1/2)
• The dc current source models the
effect of inductive energy storage that
is always present in power
electronics.
• An ideal diode is assumed.
• When the switch is on, the entire
current I0 flows through the switch
and the diode is reverse biased.
When the switch is off, I0 flows
through the diode and a voltage
equal to the input voltage Vd appears
across the switch.
• At turn-on, only after the current
flows entirely through the switch can
the diode become reverse biased
and the voltage across the switch
drop to the on-state voltage.
• At turn-off, only when the voltage
across the switch reaches its final
value Vd can the diode become
forward biased and begin to conduct
current.

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Generic-Switch Switching Characteristics (2/2)

• turn-on crossover interval: tc(on) = tri + tf v

!
• Energy dissipation during turn-on: Wc(on) = 0.5Vd I0 tc(on)
!
• Energy dissipated in on-state: Won = Von I0 ton
!
• Turn-off crossover interval: tc(of f ) = trv + tf i
!
• Energy dissipated during turn-off: Wc(of f ) = 0.5Vd I0 tc(of f )
!
• Switching power loss: Ps = 0.5Vd I0 (tc(on) + tc(of f ) )fs
!
ton
• On-state power loss: Pon = Von I0
! Ts
• Total power dissipation: PT = Ps + Pon

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Present Day Power Semiconductor Performance
Limitations

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