VLSI DESIGN2001

Fourteenth International Conference on VLSI Design

Cirrus Logic
ControlNet India Pvt. Ltd.
Delsoft India Pvt. Ltd.
Department of Electronics, Government of India
Future Techno Design Pvt. Ltd.
IBM Global Services, India
ICON Design Automation Pvt. Ltd
IKOS (I) Pvt. Ltd.
Intel Corporation
Interra Inc.
ISAT
NIIT & Mentor Graphics
Philips Software Centre Pvt. Ltd
Realchips Pvt. Ltd.
Silicon Interfaces Pvt. Ltd.
Spike Technologies India Pvt. Ltd
Synopsys (I) Pvt. Ltd.
Texas Instruments (I) Ltd
VLSI Society of India

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 About the Cover

The cover design shows an aerial photograph of the Indian Institute of Science:, the venue of this
conference. IISc was established by the late J. N. Tata, a highly successful Indian industrialist (1839-
1904). In his will he stipulated that two-thirds of his fortune was to be equally divided between his two
sons, and the remaining one-third was to be used to build a university. At his own request, the university
was not to carry his name. His dream was realized in 1911 when the Indian Institute of Science opened
its doors to students and researchers in Bangalore. Its faculty included renowned scholars such as Prof.
C.V. Raman and Prof. Max Born. The cover shows the main building of the “Tata Institute,” as it is
affectionately referred to by the people of Bangalore.

The papers in this Proceedings reflect the authors’ opinions and are published as presented and without change.
Their inclusion in this book does not necessarily constitute endorsement by the VLSI Design Conference
Committee.

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 VLSI DESIGN2001
Fourteenth International Conference on VLSI Design

3-7 JANUARY 2001

INDIA
BANGALORE,

A
IEEE
COMPUTER
SOCIETY

Los Alamitos, California

Washington . Brussels . Tokyo

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 Copyright 0 2001 by The Institute of Electrical and Electronics Engineers., Inc.
All rights reserved

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authors’ opinions and, in the interests of timely dissemination, are published as presented and without change. Their
inclusion in this publication does not necessarily constitute endorsement by the editors, the IEEE Computer Society, or
the Institute of Electrical and Electronics Engineers, Inc.

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SOCIETY

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 Table of Contents
~,
I , _..
&,,*,

General Chair's Message ........................................................................................................ xiii ...

Message from the Program Chairs ....................................................................................... xv
Conference Committee .......................................................................................................... xvii
Steering Committee................................................................................................................. xxi
VLSI Design2000 Conference Awards .............................................................................. xxiii
Reviewers.................................................................................................................................. xxv
Conference History ................................................................................................................ xxix
Program Committee .............................................................................................................. xxxi
Keynote Speakers ............................................................................................................... xxxiiil ....

I Optimization and Analysis Techniques for theTutorials

Deep Submicron Regime .................................. 3
Noel Menezes, Intel Corporation, USA
Sachin Sapatnekar, University of Minnesota, U S A

Embedded Memories in System Design: Technology, Application, Design and Tools ............... 5
Doris Keitel-Shulz, Infineon Inc., Germany
Norbert When, Kaiserslautern University, Germany
Francky Catthoor, IMEC and University of Leuven, Belgium
Preeti Ranjan Panda, Synopsys Inc., USA
Nikil Dutt, University of California, Irvine, U S A

Introduction to SystemC ................................................................................................................ 7

Sudipta Bhawmik

Low-Power Mobile Wireless Communication System Design: Protocols,

Architectures, and Design Methodologies .................................................................................... 9
Anand Raghunathan, NEC U S A C&C Research Labs, U S A
Sujit Dey, University of California, S a n Diego, U S A

IBMs Blue Logic Design Methodology-Circuits and Physical Design ...................................... 11

Ruchira Kamdar, IBM, India
Seetharam Gundurao, IBM, India
R. V. Joshi, IBM, U S A
N . S. Murty, IBM, India

Next Generation Network Processors ......................................................................................... 13

Deepak Kataria, Lucent Technologies Microelectronics, USA

Functional Verification of Programmable DSP Cores ............................................................... 16

Mahesh Mehendale, Texas Instruments (India) Ltd, India
Santhosh Kumar Amanna, Texas Instruments (India) Ltd, India

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 System Level Testability Issues of Core Based System-on-a-Chip............................................ 18
V. Ranganathan, Realchip, India
R. Sundar, Realchip, India

Tutorial: CMOS Analog Circuits for Wireless Communications ............................................. 18.1

R. Harjani, University of Minnesota
J . Harvey, University of Minnesota

Papers

Integrating Communication Cost Estimation in Embedded Systems Design:

A PCI Case Study ......................................................................................................................... 23
A. Rastogi, M. Balakrishnan, and A. Kumar
Evaluation of the Traffic-Performance Characteristics of System-on-Chip
Communication Architectures.. ................................................................................................... 29
K. Lahiri, A. Raghunathan, and S. Dey
Performance Considerations in Embedded DSP Based System-on-a-Chip Designs ............... 36
A. Gupte, M. Mehendale, R. Ramamritham, and D. Nair
Hardware Software Codesign of DSP System Using Grammar Based Approach ................... 42
A. K. Deb, A. Hemani, J . Oberg, A. Postula, and D. Lindqvist
A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging...........48
K. Danckaert, C. Kulkarni, F. Catthoor, H . De Man, and V.Tiwari

Battery Life Estimation of Mobile Embedded Systems ............................................................. 57

D. Panigrahi, C. Chiasserini, S. Dey, R. Rao, A. Raghunathan, and K. Lahiri
Power-Aware Multimedia Systems Using Run-Time Prediction .............................................. 64
P. Kumar and M. Srivastava
Processor-Memory CO-Exploration Driven by a Memory-Aware Architecture
Description Language .................................................................................................................. 70
P. Mishra, P. Grun, N. Dutt, a n d A . Nicolau
ASIP Design Methodologies: Survey and Issues ........................................................................ 76
M. K. Jain, M . Balakrishnan, and A. Kumar

ReDeEm-RTL: A Software Tool for Customizing Soft Cells for Embedded

Applications .................................................................................................................................. 85
G. Surendra, S. K. Nandy, and P. Sathya
The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis
of Design Processes ...................................................................................................................... 91
V. Sahula and C. P. Ravikumar

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 Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task
Layout Technique ......................................................................................................................... 97
A. Datta, S. Choudhury, A. Basu, H. Tomiyama, and N . Dutt
Error Diagnosis of Sequential Circuits Using Region-Based Model ....................................... 103
A. L. D’Souza and M. S. Hsiao

On Improving Static Test Compaction for Sequential Circuits .............................................. 111

R. Guo, I. Pomeranz, and S. M. Reddy
On Fault-Simulation through Embedded Memories on Large Industrial Designs ............... 117
S. Yadavalli and S. Kundu
A Novel Strategy to Test Core Based Designs .......................................................................... 122
D. Bagchi, D. R. Chowdhury, J . Mukherjee, and S. Chattopadhyay
Testable Design of Sequential Circuits with Improved Fault Efficiency ............................... 128
D. K. Das, B. B. Bhattacharya, S. Ohtake, and H. Fujiwara
Combination of Structural and State Analysis for Partial Scan ............................................. 134
S. Sharma and M. S. Hsiao

Combinational Test Generation for Acyclic Sequential Circuits Using

a Balanced ATPG Model ............................................................................................................ 143
Y. C. Kim, V. D. Agrawal, and K. K. Saluja
Synthesis of System-on-a-Chip for Testability ......................................................................... 149
S. Ravi and N, K. J h a
Timing Verification and Delay Test Generation for Hierarchical Designs ............................ 157
A. Krishnamachary, J . A. Abraham, and R. S. Tupuri
A Graph Traversal Based Framework for Sequential Logic Implication
with an Application to C-Cycle Redundancy Identification .................................................... 163
J.-K. Zhao, J . A. Newquist, and J . H. Pate1

Implementation of Read-k-times BDDs on Top of Standard BDD Packages ......................... 173

W. Giinther and R. Drechsler
Application of Esterel for Modelling and Verification of Cache Protocol
on CRF Memory Model .............................................................................................................. 179
S.,R. Phanse and R. K. Shyamasundar
Design Verification and Functional Testing of Finite State Machines. .................................. 189
M. W.Weiss, S. C. Seth, S. K. Mehta, and K. L. Einspahr
Design of Provably Correct Storage Arrays .............................................................................. 196
R. V. Joshi, W. Hwang, and A. Kuehlmann

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 Invited Paper: Low-Power Wireless Sensor Networks ............................................................ 205
R. Min, M . Bhardwaj, S.-W. Cho, E. Shih, A. Sinha, A. Wang,
and A. Chandrakasan
Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic ....................... 211
H. Soeleman, K. Roy, and B. Paul
Average Power in Digital CMOS Circuits using Least Square Estimation ............................ 215
A. K. Murugauel, N. Ranganathan, R. Chandramouli, and S. Chavali
Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces......................... 221
A. Sinha and A. P. Chandrakasan
Optimal Assignment of High Threshold Voltage for Synthesizing Dual
Threshold CMOS Circuits........................................................................................................... 227
N . Tripathi, A. Bhosle, D. Samanta, and A. Pal

Accurate Power Macro-Modeling Techniques for Complex RTL Circuits .............................. 235
N. R. Potlapally, A. Raghunathan, G. Lakshminarayana, M. S. Hsiao,
and S. T. Chakradhar
Architecture of a Reconfigurable Low Power Gigabit ATM Switch ........................................ 242
A. M. Lele and S. K. Nandy
Formulation and Validation of a n Energy Dissipation Model for the Clock
Generation Circuitry and Distribution Networks. ................................................................... 248
D. Duarte, V. Narayanan, M. J . Irwin, and M. Kandemir
Software Power Optimizations in a n Embedded System ........................................................ 254
V.Dalal and C.P. Ravikumar

Library Binding for High-Level Synthesis of Analog Systems................................................ 261

S. Ganesan and R. Vemuri
An Integrated Quadrature Mixer with Improved Image Rejection at Low Voltage .............. 269
J. Harvey and R. Harjani
A Code Transition Delay Model for ADC Test .......................................................................... 274
S. Mohan and M. L. Bushnell
Computing Phase Noise Eigenfunctions Directly from Harmonic
Balance/Shooting Matrices ........................................................................................................ 283
A. Demir, D. Long, and J. Roychowdhury

Logic Synthesis for CPLDs and FPGAs with PLA-Style Logic Blocks ................................... 291
K. Y a n

...
VI11

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 FPGA Hardware Synthesis from MATLAB.............................................................................. 299
M. Haldar, A. Nayak, N . Shenoy, A. Choudhary, and P. Banerjee
Efficient Synthesis of Array Intensive Computations onto FPGA Based
Accelerators ................................................................................................................................ 305
N. Shenoy, P. Banerjee, A. Choudhary, and M. Kandemir
Performance Driven Optimization for MUX Based FPGAs .................................................... 3 11
W.Gunther and R. Drechsler
Application Specific Macro Based Synthesis ............................................................................ 3 17
S. Sundararaman, S. Govindarajan, and R. Vemuri

Modeling of Nonuniform Interconnects by Using Differential Quadrature Method ............. 327

Q. Xu, P. Mazumder, and M . Bhattacharya
A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits ......................... 333
S. T. Zach'ariah and S. Chakravarty
How to Half Wire Lengths in the Layout of Cyclic Shifters .................................................... 339
M . A. Hillebrand, T. Schurger, and P.-M. Seidel
Partitioning Routing Area into Zones with Distinct Pins ....................................................... 345
K. Sinha, S. Sur-Kolay, P. S. Dasgupta, and B. B. Bhattacharya

Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative
Routing Strategies ...................................................................................................................... 353
S. Sengupta, S. Ramanathan, B. Chatterjee, and D. Goswami
Transmission Line Modeling by Modified Method of Characteristics .................................... 359
Q. Xu, P. Mazumder, and Z.-F. Li
Crosstalk Noise Verification in Digital Designs with Interconnect
Process Variations ...................................................................................................................... 365
Nagaraj,NS, P. Balsara, and C. Cantrell
Early Evaluation of Bus Interconnects Dependability for System-on-Chip
Designs ........................................................................................................................................ 371
M. Lajolo, M. S. Reorda, and M. Violante

An Efficient Parallel Transparent BIST Method for Multiplc Embedded

Memory Buffers ......................................................................................................................... 379
D. C. Huang, W. B. Jone, and S. R. Das
0bservability.RegisterArchitecture for Efficient Production Test
and Debug of.VLSI Circuits ....................................................................................................... 385
D. Bhavsar and R. Tan
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows ............................ 391
T. CZouqueur, 0.Ercevik, K. K. Saluja, and H. Takahashi

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 A Parallel Built-In Self-Diagnostic Method for Embedded Memory Buffers ......................... 397
D. C. Huang, W. B. Jone, and S. R. Das
Hierarchical Cellular Automata As an On-Chip Test Pattern Generator.............................. 403
B. K. Sikdar, P. Majumder, M. Mukherjee, N . Ganguly, D. K. Das,
and P. P. Chaudhuri

High Level Synthesis of Multi-Precision Data Flow Graphs .................................................. 41 1

V. Agrawal, A. Pande, and M. M. Mehendale
Multilevel Logic Minimization Using Functional Don't Cares................................................ 417
L. Wang and A. E. A. Almaini
Complexity of Minimum-Delay Gate Resizing ......................................................................... 425
S. Chakraborty and R. Murgai
Synthesis of Transparent Circuits for Hierarchical and System-on-a-Chip Test. ................ . 4 31
K. Chakrabarty, R. Mukherjee, and A. Exnicios

Scaling Up of Wave Pipelines ................... ..-............................................................................... 439

M. Fukase, T. Sato, R. Egawa, and T. Nakamura
VLSI Architectures for High-speed MAP Decoders................................................................. 446
A. Worm, H . Lamm, and N . Wehn
Design of Multiple Attractor GF(2') Cellular Automata for Diagnosis
of VLSI Circuits .......................................................................................................................... 454
B. K. Sikdar, N . Ganguly, P. Majumder, and P. P. Chaudhuri
Synthesizing a Long Latency Unit within VLIW Processor.................................................... 460
R. L. Gupta, A. Kumar, A. V a n Der Werf, and G. N . Busa

Invited Paper: Extending Resolution Limits of IC Fabrication Technology:

Demonstration by Device Fabrication and Circuit Performance ............................................ 469
0. Nalamasu, G. P. Watson, R. A. Cirelli, J . Bude, I. C. Kizilyalli, and R. Kohber
FD-TLM Electromagnetic Field Simulation of High-speed 111-V Heterojunction
Bipolar Transistor Digital Logic Gates ..................................................................................... 470
M. Bhattacharya, P. Mazumder, and R. J . Lomax
Performance Optimization of 60 nm Channel Length Vertical MOSFETs
Using Channel Engineering ...................................................................................................... 475
G. Shriuastav, S. Mahapatra, V. Ramgopal Rao, and J . Vasi
Effect of Fringing Capacitances in Sub 100 nm MOSFET's with High-K
Gate Dielectrics .......................................................................................................................... 479
N. R. Mohapatra, A. Dutta, M. P. Desai, and V. R. Rao

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 Degradation of NMOSFETs During High-Field Injection with Reverse Biased
Voltage at Source and Drain Junctions .................................................................................... 485
R. K. Jarwal and D. Misra
High Frequency Behaviour of Electron Transport in Silicon and Its Implication
for Drain Conductance of MOS Transistors ............................................................................. 491
B. Prasad, P. J . George, and C. Shekhar
An On-Chip Coupling Capacitance Measurement Technique ................................................. 495
P. A. Nair, A. Gupta, and M. P. Desai
Spectral Algorithm to Compute and Synthesize Reduced Order Passive Models
for Arbitrary RC Multiports ...................................................................................................... 500
S. H . Batterywala and H . Narayanan

Repeater Insertion to Minimise Delay in Coupled Interconnects ........................................... 513

D. Pamunuwa and H. Tenhunen
Integrated Crosstalk and Oxide Integrity Analysis in DSM Designs ..................................... 518
N . V. Arvind, P. R. Suresh, V. Sivakumar, C. Pal, and D. Das
Switching Noise Analysis Framework for High Speed Logic Families ................................... 524
M. Delaurenti, M. Graziano, G. Masera, G. Piccinini,
and M. Zamboni
Estimating Crosstalk from VLSI Layouts ................................................................................ 531
V. S. Subramanian and C. P. Ravikumar

Author Index ............................................................................................................................ 537

VLSI Design 2002 Call for Papers ....................................................................................... 540

5th IEEE VLSI Design & Test Workshops 2001 Call for Participation...................... 541

xi

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