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The RISC-V Processor: Control Unit

The document discusses the design of a RISC-V processor, including its datapath and control unit. It outlines the main components of the RISC-V datapath like the register file, instruction memory, and data memory. It also discusses instruction interpretation and execution as well as combinational control. Finally, it mentions that the assignment is to design the datapath and control unit using an HDL.

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70 views16 pages

The RISC-V Processor: Control Unit

The document discusses the design of a RISC-V processor, including its datapath and control unit. It outlines the main components of the RISC-V datapath like the register file, instruction memory, and data memory. It also discusses instruction interpretation and execution as well as combinational control. Finally, it mentions that the assignment is to design the datapath and control unit using an HDL.

Uploaded by

Secret Keeper
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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The RISC-V Processor

Control Unit
Module Outline
● RISC-V datapath implementation
– Register File, Instruction memory, Data memory
● Instruction interpretation and execution.
● Combinational control
● Assignment: Datapath design and Control Unit
design using HDL.
RISC-V Datapath and Control Lines
Control Unit

Branch
MemRead
MemtoReg
Instruction[6-0] ALUOp
CONTROL
CONTROL
MemWrite
ALUSrc
RegWrite
R-Type – Datapath, Control
R-Type – Datapath, Control

00

00

00 00
11

00

10
10
Load Instruction
Load Instruction

00

11

11 11

00

11

00
00
Branch-on-Equal Instruction
Branch-on-Equal Instruction

11

XX

00 00

00

00

01
01
The Main Control Unit
The Main Control Unit
The Main Control Unit
The Main Control Unit
Branch=f
Branch=f2⋅f 1⋅f 0
2⋅f 1⋅f 0

MemtoReg=f
MemtoReg=f2⋅f 1⋅f 0 MemRead=f
MemRead=f2⋅f 1⋅f 0 ALUOp
ALUOp0=f
0=f2⋅f 1⋅f 0
2⋅f 1⋅f 0 2⋅f 1⋅f 0 2⋅f 1⋅f 0

ALUSrc=f
ALUSrc=f2⋅f RegWrite=f
RegWrite=f22((f f1⋅f 0 + f 1⋅f 0)
ALUOp1=f
ALUOp1=f2⋅f 1⋅f 0
2⋅f 0 1⋅f 0 + f 1⋅f 0) 2⋅f 1⋅f 0
0

MemWrite=f
MemWrite=f2⋅f 1⋅f 0
2⋅f 1⋅f 0
Outline
● RISC-V datapath implementation
– Register File, Instruction memory, Data memory
● Instruction interpretation and execution.
● Combinatinal control
● Datapath and Control Unit design using HDL
Control Unit Truth Table

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