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Structural Level Modeling: - : Fulladd Fa3 (Sum (3), Carry - Out, A (3), x4, c3)

The document describes the structural, dataflow, and behavioral modeling of a 4-bit adder/subtractor circuit. It includes the Verilog code for each level of modeling, a test bench to simulate the circuit, and the results of the simulation which show the input, output, and time values.

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Satyam Govila
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82 views6 pages

Structural Level Modeling: - : Fulladd Fa3 (Sum (3), Carry - Out, A (3), x4, c3)

The document describes the structural, dataflow, and behavioral modeling of a 4-bit adder/subtractor circuit. It includes the Verilog code for each level of modeling, a test bench to simulate the circuit, and the results of the simulation which show the input, output, and time values.

Uploaded by

Satyam Govila
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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(1) STRUCTURAL LEVEL MODELING : -

`timescale 1ns / 1ps

module add_sub_4(a, b, sum, carry_out, select_input);

input [3:0] a;

input [3:0] b;

output [3:0] sum;

output carry_out;

input select_input;

wire c1,c2,c3,x1,x2,x3,x4;

fulladd fa0 (sum[0],c1,a[0],x1,select_input);

fulladd fa1 (sum[1],c2,a[1],x2,c1);

fulladd fa2 (sum[2],c3,a[2],x3,c2);

fulladd fa3 (sum[3],carry_out,a[3],x4,c3);

xor xor1(x1,select_input,b[0]);

xor xor2(x2,select_input,b[1]);

xor xor3(x3,select_input,b[2]);

xor xor4(x4,select_input,b[3]);

endmodule

// 1 bit full adder module

module fulladd(sum, carry_out, a, b, c_in);

output sum;

output carry_out;

input a;

input b;

input c_in;

wire s1,s2,s3;

xor x1(s1,a,b);
xor x2(sum,s1,c_in);

and a1(s2,a,b);

and a2(s3,c_in,s1);

or o1(carry_out,s3,s2);

endmodule

(2) DATAFLOW LEVEL MODELING : -


`timescale 1ns / 1ps

module add_sub_4(a, b, sum, carry_out, select_input);

input [3:0] a;

input [3:0] b;

output [3:0] sum;

output carry_out;

input select_input;

assign

{carry_out,sum}=a+{b[3]^select_input,b[2]^select_input,b[1]^sel

ect_input,b[0]^select_input}+select_input; endmodule

(3) BEHAVIORAL LEVEL MODELING : -


`timescale 1ns / 1ps

module add_sub_4(sum,carry_out,a,b,select_input);

input [3:0]a,b;

input select_input;

output [3:0]sum;

output carry_out;

reg carry_out;

reg [3:0]sum;

reg [4:0]temp;

always @(a or b or select_input)


begin
if (select_input==0)

begin

temp=a+b;

sum=temp[3:0];

carry_out=temp[4];

end

else if (select_input==1)

begin

temp=a-b;

sum=temp[3:0];

carry_out=temp[4];

end

end

endmodule

TEST BENCH OF 4-BIT ADDER/SUBTRACTOR: -


module stimulus_add_sub_4;

reg select_input;

reg [3:0]a;

reg [3:0]b;

wire [3:0]sum;

wire carry_out;

adder_sub_4 a1(sum,carry_out,a,b,select_input);

initial

begin

#0 a=4'b0001; b=4'b0010; select_input=1'b0;

#10 a=4'b0110; b=4'b0111; select_input=1'b0;

#10 a=4'b1000; b=4'b1011; select_input=1'b0;

#10 a=4'b1111; b=4'b1010; select_input=1'b1;

#10 a=4'b0101; b=4'b0101; select_input=1'b1;


#10 a=4'b0010; b=4'b0011; select_input=1'b1;

#10 $finish;

end

initial

begin

$monitor("$time a=%b b=%b select_input=%b sum=%b


carry_out=%b",a,b,select_input,sum,carry_out);

end

endmodule

SIMULATION RESULTS : -
$time a=0001 b=0010 select_input=0 sum=0011 cout=0

$time a=0110 b=0111 select_input=0 sum=1101 cout=0

$time a=1000 b=1011 select_input=0 sum=0011 cout=1

$time a=1111 b=1010 select_input=1 sum=0101 cout=1

$time a=0101 b=0101 select_input=1 sum=0000 cout=1

$time a=0010 b=0011 select_input=1 sum=1111 cout=0

SIMULATION WAVEFORM OF INPUT AND OUTPUT PORTS: -


SIMULATION WAVEFORM OF INPUT AND OUTPUT PORTS (EXPANDED) : -

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