POWER PC

A Brief Overview of PowerPC

ARKADIP RAY
M.Tech IT - 11

The PowerPC chip was one of several joint ventures

Abstract— This study provides an overview of the PowerPC involving the three, in their efforts to counter the growing
microprocessor features including a block diagram showing Microsoft-Intel dominance of personal computing. By July
the major functional components. It also provides an overview 2010, the POWER architecture IBM developed is still very
of the PowerPC architecture and working process.
much alive on their server offerings for large businesses and
continues to evolve (and current POWER processors
I. INTRODUCTION
implement the full PowerPC instruction set architecture).
PowerPC (Performance Optimization With Enhanced RISC
For example, IBM's servers based on POWER have the
– Performance Computing, sometimes abbreviated as PPC)
highest revenue market share (53.9%) among UNIX servers.
is a reduced instruction set computing (RISC) instruction set
The PowerPC specification is now handled by Power.org.
architecture (ISA) created by the 1991 Apple–IBM–
Motorola alliance, known as AIM. PowerPC was the III. OVERVIEW
cornerstone of AIM's PReP and Common Hardware
 The 601 is the first implementation of the PowerPC
Reference Platform initiatives in the 1990s. Originally
family of reduced instruction set computer (RISC)
intended for personal computers, the architecture is well
microprocessors.
known for being used by Apple's Power Macintosh,
 The 601 implements the 32-bit portion of the PowerPC
PowerBook, iMac, iBook, and Xserve lines from 1994 to
architecture, which provides 32- bit effective (logical)
2006. It has since become niche in personal computers, but
addresses, integer data types of 8, 16, and 32 bits, and
remain popular as embedded and high-performance
floating-point data types of 32 and 64 bits.
processors. Its use in video game consoles and embedded
 For 64-bit PowerPC implementations, the PowerPC
applications provided an array of uses.
architecture provides 64-bit integer data types, 64-bit
II. BRIEF HISTORY addressing, and other features required to complete the
The history of RISC began with IBM's 801 research project, 64-bit architecture.
where developed the concepts of RISC in 1975-78. 801-  The 601 is a superscalar processor capable of issuing
based microprocessors were used in a number of IBM and retiring three instructions per clock, one to each of
embedded products, eventually becoming the 16-register three execution units.
ROMP (Research Office Products Division Micro  The 601 integrates three execution units—an integer
Processor) processor used in the IBM RT. RT was a rapid unit (IU), a branch processing unit (BPU), and a
design implementing the RISC principles, and the floating-point unit (FPU). The ability to execute three
performance was disappointing in comparison to the high instructions in parallel and the use of simple
performance 68000 microprocessor from Motorola. instructions with rapid execution times yield high
Between the years of 1982-1984 IBM started a project to efficiency and throughput for 601-based systems.
build the fastest microprocessor on the market and  The 601 includes an on-chip, 32-Kbyte, eight-way set-
development was goes another 4-5 years. The result was the associative, physically addressed, unified instruction
POWER instruction set architecture, introduced with the data cache and an on-chip memory management unit
RISC System/6000 in early 1990. In 1991, the PowerPC (MMU).
was just one facet of a larger alliance among these three  The 601 has a 64-bit data bus and a 32-bit address bus.
companies. At the time, most of the personal computer
industry was shipping systems based on the Intel 80386 and IV. FEATURES
80486 chips, which had a CISC architecture, and Originally intended for personal computers, PowerPC CPUs
development of the Pentium processor was well underway. have since become popular with embedded and high-
performance processors as well. It is largely based and
compatible with POWER microprocessor. Design features  A 64-bit split-transaction external data bus with
of PowerPC are as follows - burst transfers
 High-performance, superscalar microprocessor  Support for address pipelining and limited out-of-
 As many as three instructions in execution per order bus transactions
clock (one to each of the three execution units)  Snooped copyback queues for cache block (sector)
 Single clock cycle execution for most instructions copyback operations
 Pipelined FPU for all single-precision and most  Bus extensions for I/O controller interface
operations
double-precision operations
 Multiprocessing support features that include the
 Three independent execution units and two register files following: Hardware enforced, four-state cache
 BPU featuring static branch prediction coherency protocol (MESI)
 Separate port into cache tags for bus snooping
 A 32-bit IU
 Fully IEEE 754-compliant FPU for both single-  In-system testability and debugging features through
and double-precision operations boundary-scan capability
 Thirty-two GPRs for integer operands
V. IMPLEMENTATION
 Thirty-two FPRs for single- or double-precision
The first implementation of the architecture was the Power-
operands
PC 601, released in 1992, based on the RSC, implementing
 High instruction and data throughput a hybrid of the POWER1 and Power-PC instructions. This
 Zero-cycle branch capability allowed the chip to be used by IBM in their existing
 Programmable static branch prediction on POWER1-based platforms, although it also meant some
unresolved conditional branches slight pain when switching to the 2nd generation "pure"
 Instruction unit capable of fetching eight PowerPC designs. Apple continued work on a new line of
instructions per clock from the cache Macintosh computers based on the chip, and eventually
 An eight-entry instruction queue that provides released them as the 601-based Power Macintosh on March
look-ahead capability 14, 1994.
 Interlocked pipelines with feed-forwarding that The first 64-bit implementation was the PowerPC
control data dependencies in hardware 620, but it appears to have seen little use because Apple
 Unified 32-Kbyte cache—eight-way set- didn't want to buy it and because, with its large die area, it
associative, physically addressed; LRU was too costly for the embedded market. It was later and
replacement algorithm slower than promised, and IBM used their own POWER3
 Cache write-back or write-through operation design instead, offering no 64-bit "small" version until the
programmable on a per page or per block basis late-2002 introduction of the PowerPC 970.
 Memory unit with a two-element read queue and a The 970 is a 64-bit processor derived from the
three-element write queue POWER4 server processor. To create it, the POWER4 core
 Run-time reordering of loads and stores was modified to be backward-compatible with 32-bit
 BPU that performs condition register (CR) look- PowerPC processors, and a vector was added. IBM
ahead operations developed a separate product line called the "4xx" line
 Address translation facilities for 4-Kbyte page size, focused on the embedded market. These designs included
variable block size, and 256-Mbyte segment size the 401, 403, 405, 440, and 460. In 2004, IBM sold their
 A 256-entry, two-way set-associative UTLB 4xx product line to Applied Micro Circuits Corporation.
 Four-entry BAT array providing 128-Kbyte to 8- Honda also uses PowerPC processors for ASIMO.
Mbyte blocks There are many implementation of PPC concept
 Four-entry, first-level ITLB after 1991, some of those are:
 Hardware table search (caused by UTLB misses)
through hashed page tables  Gekko Microprocessor:
 52-bit virtual address; 32-bit physical address It is a 32-bit microprocessor custom made by IBM in 2000.
Gekko’s role in the gamming system was to facilitate game
 Facilities for enhanced system performance
scripting, artificial intelligence, physics and collision
 Bus speed defined as selectable division of
detection, custom graphics lighting effects and geometry
operating frequency
such as smooth transformations, and moving graphics data  PowerPC e200 - 32 bit power architecture
through the system. The main features are: microprocessor - speed ranging up to 600 MHz - ideal
 Customized power Pc 750Cxe core. for embedded applications.
 Clock rate – 486MHz.  PowerPC e300 – similar to e200 with an increase in
 Integer unit 32-bit. speed upto 667 MHz.
 Floating point unit – 64-bit  PowerPC e600 – speed upto 2 Ghz – ideal for high
 SIMD instruction – PowerPC instructions + 50 performance routing and telecommunications
new SIMD instructions geared toward 3d graphics. applications.
 POWER5 – IBM – dual core μP
 Kilo core Microprocessor:
 POWER6 – IBM – Dual core μP - A notable difference
It is high performance, low power multi-core
from POWER5 is that the POWER6 executes
microprocessor that has 1025 core. It contains a single
instructions in-order instead of out-of-order
PowerPC processing core, and 1,024 eight-bit Processing
 PowerPC G3 - Apple Macintosh computers such as the
Elements running at 125 MHz each, which can be
PowerBook G3, the multicolored iMacs, iBooks and
dynamically reconfigured, connected by a shared
several desktops, including both the Beige and Blue and
interconnect. It allows high performance parallel processing.
White Power Macintosh G3s.
IBM says that the Kilocore1025 will enable "streaming live-
 PowerPC G4 - is a designation used by Apple
and high-definition video on a low-power, mobile device at
Computer to describe a fourth generation of 32-bit
five to 10 times the speed of existing processors.
PowerPC microprocessors.
 Power3, Power4, Power5 this all are invented by IBM.  PowerPC G5 - 64-bit Power Architecture processors
The differences on this are:  Xenon - based on IBM’s PowerPC ISA – XBOX 360
Frequency: (450MHz), (1.1GHz to 1.9GHz), (1.5GHz to game console.
2.3GHz).  Broadway – based on IBM’s PowerPC ISA – Nintendo
Produced: 1998, 2001, 2004. Wii gaming console
Min. feature size: (220nm to 180nm), (180nm to 130nm),  Blue Gene/L - dual core PowerPC 440, 700 MHz, 2004
(130nm to 90nm).  Blue Gene/P - quad core PowerPC 450, 850 MHz, 2007
Cores: 1, 2, 2.
VII. POWER PC ARCHITECTURE
 X704 Microprocessors:
It is a Microprocessor that implements the 32-bit version of
the PowerPC instruction set architecture (ISA) developed by
Exponential Technology. The microprocessor was notable
for its high clock frequency (for the time, circa 1997) in the
range of 400 to 533 MHz, its use of bipolar transistors for
logic and CMOS circuits for memory, and its failure to see
use in an Apple Macintosh, the opposite of what industry
observers.
From the beginning of the PowerPC to today’s
world, a huge change is observed. The frequency of
PowerPC is increased and cores are improved, also caches
of this type of microprocessors are changed hugely.

VI. POWER PC PROCESSOR

Many PowerPC designs are named and labelled by their
apparent technology generation. IBM and Motorola together
made G1, G2 and G3 series of processor. After that
Motorola made power-pc 7xx family and G4 series. IBM
produced separately POWER 3, 4, 5, 6, 6+, 7, 7+ series and
also RS64, G5 series. The POWER series are all 64-bit
processors. PowerPC Generations are as follows -
 VIII. OPERATING SYSTEMS the value zero and no other value can be written to it. One
 Operating systems that work on the PowerPC architecture advantage of a large number of registers is that it avoids the
are generally divided into those that are oriented toward use of the stack to store parameters. Although a stack can be
the general-purpose PowerPC systems, and those oriented implemented on a Power PC processor, it is not as necessary
toward the embedded PowerPC systems. as in a Pentium processor since there are so many registers
e.g. - Apple’s Classic mac OS, IBM i5/OS, Linux available. It must be noted that PowerPC processors have
(Debian, Fedora, Mint, Red Hat Enterprise Edition, another 32 registers for floating-point operations, besides
Ubuntu, Solaris), Windows NT, CellOS for Playstation the 32 general-purpose registers. The floating-point register
 Companies that produces 32/64 bit PowerPC till date: can be configured as 64-bit in order to handle double-
e.g. - Intel, Apple, Cisco Systems for Routers, Motorola, precision operands.
Samsung, Xilinx, Microsoft, HCL, Sony, Toshiba (5) Floating Point: The similarities of Pentium and PowerPC
 Gaming Consoles: in floating point are both of them complying with IEEE-754
e.g. - Bandai, Xbox, Nintendo, PlayStation standard single-and-double precision floating point
arithmetic and having regular multiply and divide
IX. PENTIUM VS. POWERPC instructions that operate entirely on registers. The main
(1) Background: Pentium is a member of the series 8086. differences are in the floating-point instructions. Both 32
It uses the same basic pattern as its predecessor. To keep single and 32 double precision floating-point registers are
its compatibility with the existing software base, each offered in the Power PC.
time it is improved, Intel’s engineers must retain its old
features. On the other hand, PowerPC uses the totally CONCLUSION
new technology called RISC. In RISC, the number of As we have seen, Reduced Instruction Set Computing
instructions, addressing modes, and format are reduced. (RISC) is an evolution in computer architectures that
RISC technology was developed. emphasizes speed and cost-effectiveness over ease of
(2) Instruction Size: Pentium use varies instruction set assembly-language programming and the conservation of
sizes. In the Pentium, instruction set format can be 1, 2, memory. In addition, RISC-based designs will continue to
or even 6 bytes. On the other hand, the PowerPC, like grow in speed and ability much more rapidly than
other RISC processors uses 4 byte instruction sets. All comparable CISC designs over the next several years. These
the instruction sets have the same length. If there are factors make RISC an irresistible choice for the future of the
instructions with size less than 4 bytes, then they are Macintosh product line. Yet, since Apple's customers have a
filled in with zeros. This difference of instruction sizes sizable investment in hardware and software, compatibility
affects the pipelining process between the two is a key word among Apple's PowerPC engineers. This
processors. compatibility is being maintained through software
emulation, significant amounts of compatibility testing, and
(3) Instruction Set: The PowerPC only has a few types of
making sure that existing NuBus cards can work in the first
instruction sets. If there are instructions which are not in
PowerPC machines.
the PowerPC’s instruction set library, then the
programmer/compiler has to implement those instructions
ACKNOWLEDGEMENT
by using available PowerPC instructions. That is one
I hereby like this opportunity to express my gratitude
reason why PowerPC programmers like to use high level
towards Ms. Paromita Dey, Professor of Dept. of
language rather than assembly language. Inversely,
Information Technology, GOVERNMENT COLLEGE OF
Pentium uses many instruction sets. This allows the
ENGINEERING AND CERAMIC TECHNOLOGY, for
programmers to implement their program using assembly
providing me the facility to undergo the presentation in the
language. It also decreases the length of program in CISC
organization. I also like to thank all the faculty members and
rather than in RISC.
staff of the department of the INFORMATION
(4) Number of Registers: One of the major characteristics
TECHNOLOGY. At the end, I am indebted to all, who have
of RISC architecture is a large number of registers.
directly helped, inspired and guided me in the completion of
PowerPC microprocessors have 32 general purpose
the presentation.
registers, GPR0 – GPR31, each 32 bits wide. Of these 32
registers, only a few of them are assigned to a dedicated
function. For example, GPR0 is automatically assigned
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