TMUX1208 5-V Bidirectional 8:1, 1-Channel Multiplexer: 1 Features 3 Description

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TMUX1208
SCDS389B – AUGUST 2018 – REVISED NOVEMBER 2018
TMUX1208 5-V Bidirectional 8:1, 1-Channel Multiplexer

1 Features 3 Description
•
1 Rail to Rail Operation The TMUX1208 is a general purpose complementary
metal-oxide semiconductor (CMOS) analog
• Bidirectional Signal Path multiplexers (MUX). The TMUX1208 offers 8:1 single-
• Low On-Resistance: 5 Ω ended channels. Wide operating supply of 1.08 V to
• Wide Supply Range: 1.08 V to 5.5 V 5.5 V allows for use in a wide array of applications
• -40°C to +125°C Operating Temperature from personal electronics to building automation
applications. The device supports bidirectional analog
• 1.8 V Logic Compatible and digital signals on the source (Sx) and drain (D)
• Fail-Safe Logic pins ranging from GND to VDD.
• Low Supply Current: 10 nA All logic inputs have 1.8 V logic compatible
• Transition Time: 14 ns thresholds, ensuring both TTL and CMOS logic
• Break-Before-Make Switching Action compatibility when operating in the valid supply
voltage range. Fail-Safe Logic circuitry allows
• ESD Protection HBM: 2000 V voltages on the control pins to be applied before the
• Industry-Standard TSSOP and QFN Packages supply pin, protecting the device from potential
damage.
2 Applications
Device Information(1)
• Analog and Digital Multiplexing / Demultiplexing
PART NUMBER PACKAGE BODY SIZE (NOM)
• HVAC: Heating, Ventilation, and Air Conditioning
TSSOP (16) 5.00 mm × 4.40 mm
• Smoke Detectors TMUX1208
QFN (16) 2.60 mm x 1.80 mm
• Video Surveillance
(1) For all available packages, see the package option addendum
• Electronic Point of Sale at the end of the data sheet.
• Battery-Powered Equipment SPACER
• Appliances
SPACER
• Consumer Audio
Application Example TMUX1208 Block Diagram
VDD
VDD
VDD VI/O TMUX1208
LDO #1
EN
S1
MCU S2
LDO #2 S1
S3
S2 RAM FLASH
LDO #3
S4
S3
S5 D
S4
D Integrated S6
LM20
S5 12-bit ADC S7
Analog Temp.
Sensor S6 S8
LM20 S7
Analog Temp. Port I/O TIMERS
Sensor
S8 1-OF-8
LM20 A1
A2 DECODER
A0
Analog Temp.
GND 1.8V Logic
Sensor
I/O
A0 A1 A2 EN
System Inputs &
Sensors
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1208
SCDS389B – AUGUST 2018 – REVISED NOVEMBER 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 19
2 Applications ........................................................... 1 9 Application and Implementation ........................ 21
3 Description ............................................................. 1 9.1 Application Information............................................ 21
4 Revision History..................................................... 2 9.2 Typical Application ................................................. 21
9.3 Design Requirements.............................................. 21
5 Device Comparison Table..................................... 3
9.4 Detailed Design Procedure ..................................... 22
6 Pin Configuration and Functions ......................... 3
9.5 Application Curve .................................................... 22
7 Specifications......................................................... 4
10 Power Supply Recommendations ..................... 22
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
7.3 Recommended Operating Conditions....................... 4
11.2 Layout Example .................................................... 23
7.4 Thermal Information .................................................. 4
7.5 Electrical Characteristics (VDD = 5 V ±10 %) ............ 5 12 Device and Documentation Support ................. 24
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %) ......... 7 12.1 Documentation Support ........................................ 24
7.7 Electrical Characteristics (VDD = 1.8 V ±10 %) ......... 9 12.2 Receiving Notification of Documentation Updates 24
7.8 Electrical Characteristics (VDD = 1.2 V ±10 %) ....... 11 12.3 Community Resources.......................................... 24
7.9 Typical Characteristics ............................................ 13 12.4 Trademarks ........................................................... 24
12.5 Electrostatic Discharge Caution ............................ 24
8 Detailed Description ............................................ 14
12.6 Glossary ................................................................ 24
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 19 13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2018) to Revision B Page
• Added RSV (QFN) thermal information to Thermal Information: table................................................................................... 4

• Added footnote to clarify test conditions ................................................................................................................................ 7
Changes from Original (August 2018) to Revision A Page
• Changed the document status From: Advanced Information To: Production data ................................................................ 1
2 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1208

TMUX1208
www.ti.com SCDS389B – AUGUST 2018 – REVISED NOVEMBER 2018
5 Device Comparison Table
PRODUCT DESCRIPTION
TMUX1208 8:1, 1-Ch. single-ended analog multiplexer
6 Pin Configuration and Functions
TMUX1208: PW Package
16-Pin TSSOP TMUX1208: RSV Package
Top View 16-Pin QFN
Top View
EN
A1
A0
A2
A0 1 16 A1
EN 2 15 A2
N.C. 3 14 GND
14
16
15
13
S1 4 13 VDD N.C. 1 12 GND
S2 5 12 S5
S1 2 11 VDD
S3 6 11 S6
S2 3 10 S5
S4 7 10 S7
S3 4 9 S6
D 8 9 S8
7
5
8
No t to scale
No t to scale
S8
S4
S7
Pin Functions TMUX1208
PIN
TYPE (1) DESCRIPTION
NAME TSSOP UQFN
A0 1 15 I Address line 0
Active high logic input. When this pin is low, all switches are turned off. When this pin is high,
EN 2 16 I
the A[2:0] logic inputs determine which switch is turned on.
N.C. 3 1 Not Connected Not Connected
S1 4 2 I/O Source pin 1. Can be an input or output.
D 8 6 I/O Drain pin. Can be an input or output.
Positive power supply. This pin is the most positive power-supply potential. For reliable
VDD 13 11 P
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND 14 12 P Ground (0 V) reference
(1) I = input, O = output, I/O = input and output, P = power
Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 3

TMUX1208
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN MAX UNIT

VDD Supply voltage –0.3 6 V
VSEL or VEN Logic control input pin voltage (EN, A0, A1, A2) –0.3 6 V
ISEL or IEN Logic control input pin current (EN, A0, A1, A2) –30 30 mA
VS or VD Source or drain voltage (Sx, D) –0.5 VDD+0.5 V
IS or ID (CONT) Source or drain continuous current (Sx, D) –30 30 mA
Tstg Storage temperature –65 150 °C
TJ Junction temperature 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins (1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC
±750
specification JESD22-C101, all pins (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 1.08 5.5 V
VS or VD Signal path input/output voltage (source or drain pin) (Sx, D) 0 VDD V
VSEL Address select pin voltage (A0, A1, A2) 0 5.5 V
VEN Enable pin voltage 0 5.5 V
TA Ambient temperature –40 125 °C
7.4 Thermal Information

DEVICE DEVICE
THERMAL METRIC PW (TSSOP) RSV (QFN) UNIT
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 118.9 134.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 49.3 74.3 °C/W
RθJB Junction-to-board thermal resistance 65.2 62.8 °C/W
ΨJT Junction-to-top characterization parameter 7.6 4.3 °C/W
ΨJB Junction-to-board characterization parameter 64.6 61.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

TMUX1208
7.5 Electrical Characteristics (VDD = 5 V ±10 %)

at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
ANALOG SWITCH
25°C 5 Ω
VS = 0 V to VDD
RON On-resistance –40°C to +85°C 7 Ω
ISD = 10 mA
–40°C to +125°C 9 Ω
25°C 0.15 Ω
On-resistance matching between VS = 0 V to VDD
ΔRON –40°C to +85°C 1 Ω
channels ISD = 10 mA
–40°C to +125°C 1 Ω
25°C 1.5 Ω
RON VS = 0 V to VDD
On-resistance flatness –40°C to +85°C 2 Ω
FLAT ISD = 10 mA
–40°C to +125°C 3 Ω
VDD = 5 V 25°C ±75 nA
Switch Off –40°C to +85°C -150 150 nA
IS(OFF) Source off leakage current (1)
VD = 4.5 V / 1 V
VS = 1 V / 4.5 V –40°C to +125°C -175 175 nA
VDD = 5 V 25°C ±200 nA
(1) Switch Off –40°C to +85°C -500 500 nA
ID(OFF) Drain off leakage current
VD = 4.5 V / 1 V
VS = 1 V / 4.5 V –40°C to +125°C -750 750 nA
VDD = 5 V 25°C ±200 nA

ID(ON)
Channel on leakage current Switch On –40°C to +85°C -500 500 nA
IS(ON)
VD = VS = 4.5 V / 1 V –40°C to +125°C -750 750 nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH Input logic high -40°C to 125°C 1.49 5.5 V
VIL Input logic low -40°C to 125°C 0 0.87 V
IIH
Input leakage current 25°C ±0.005 µA
IIL
IIH
Input leakage current –40°C to +125°C ±0.10 µA
IIL
CIN Logic input capacitance 25°C 1 pF
CIN Logic input capacitance –40°C to +125°C 2 pF
POWER SUPPLY
25°C 0.02 µA
IDD VDD supply current Logic inputs = 0 V or 5.5 V
–40°C to +125°C 2.7 µA
(1) When VS is 4.5 V, VD is 1 V, and vice versa.

TMUX1208
Electrical Characteristics (VDD = 5 V ±10 %) (continued)

DYNAMIC CHARACTERISTICS
25°C 14 ns
VS = 3 V
tTRAN Transition time between channels –40°C to +85°C 33 ns
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 33 ns
25°C 8 ns
tOPEN VS = 3 V
Break before make time –40°C to +85°C 1 ns
(BBM) RL = 200 Ω, CL = 15 pF
–40°C to +125°C 1 ns
25°C 14 ns
VS = 3 V
tON(EN) Enable turn-on time –40°C to +85°C 20 ns
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 20 ns
25°C 5 ns
VS = 3 V
tOFF(EN) Enable turn-off time –40°C to +85°C 20 ns
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 20 ns
VS = VDD/2
QC Charge Injection 25°C ±9 pC
RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF
25°C -62 dB
f = 1 MHz
OISO Off Isolation
RL = 50 Ω, CL = 5 pF
25°C -42 dB
f = 10 MHz
RL = 50 Ω, CL = 5 pF
25°C -62 dB
f = 1 MHz
XTALK Crosstalk
RL = 50 Ω, CL = 5 pF
25°C -42 dB
f = 10 MHz
BW Bandwidth RL = 50 Ω, CL = 5 pF 25°C 65 MHz
CSOFF Source off capacitance f = 1 MHz 25°C 13 pF
CDOFF Drain off capacitance f = 1 MHz 25°C 76 pF
CSON
On capacitance f = 1 MHz 25°C 85 pF
CDON

TMUX1208
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)

at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
ANALOG SWITCH
25°C 9 Ω
VS = 0 V to VDD
ISD = 10 mA
–40°C to +125°C 17 Ω
25°C 0.15 Ω
ΔRON –40°C to +85°C 1 Ω
–40°C to +125°C 1 Ω
25°C 3 Ω
RON VS = 0 V to VDD
On-resistance flatness –40°C to +85°C 5 Ω
FLAT ISD = 10 mA
–40°C to +125°C 6 Ω
VDD = 3.3 V 25°C ±75 nA
VD = 3 V / 1 V
VS = 1 V / 3 V –40°C to +125°C -175 175 nA
VDD = 3.3 V 25°C ±200 nA
VD = 3 V / 1 V
VS = 1 V / 3 V –40°C to +125°C -750 750 nA
VDD = 3.3 V 25°C ±200 nA

ID(ON)
IS(ON)
VD = VS = 3 V / 1 V –40°C to +125°C -750 750 nA
VIH Input logic high -40°C to 125°C 1.35 5.5 V
VIL Input logic low -40°C to 125°C 0 0.8 V
IIH
IIL
IIH
IIL
CIN Logic input capacitance 25°C 1 pF
CIN Logic input capacitance –40°C to +125°C 2 pF
POWER SUPPLY
25°C 0.01 µA
–40°C to +125°C 1.5 µA
(1) When VS is 3 V, VD is 1 V, and vice versa.

TMUX1208
Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)

25°C 14 ns
VS = 2 V
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 25 ns
25°C 8 ns
tOPEN VS = 2 V
(BBM) RL = 200 Ω, CL = 15 pF
–40°C to +125°C 1 ns
25°C 14 ns
VS = 2 V
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 25 ns
25°C 7 ns
VS = 2 V
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 13 ns
VS = VDD/2
RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF
25°C -62 dB
f = 1 MHz
OISO Off Isolation
RL = 50 Ω, CL = 5 pF
25°C -42 dB
f = 10 MHz
RL = 50 Ω, CL = 5 pF
25°C -62 dB
f = 1 MHz
XTALK Crosstalk
RL = 50 Ω, CL = 5 pF
25°C -42 dB
f = 10 MHz
CSON
CDON

TMUX1208

ANALOG SWITCH
25°C 40 Ω
VS = 0 V to VDD
ISD = 10 mA
–40°C to +125°C 80 Ω
25°C 0.15 Ω
ΔRON –40°C to +85°C 1.5 Ω
–40°C to +125°C 1.5 Ω
VDD = 1.98 V 25°C ±75 nA
VD = 1.8 V / 1 V
VS = 1 V / 1.8 V –40°C to +125°C -175 175 nA
VDD = 1.98 V 25°C ±200 nA
VD = 1.8 V / 1 V
VS = 1 V / 1.8 V –40°C to +125°C -750 750 nA
VDD = 1.98 V 25°C ±200 nA

ID(ON)
IS(ON)
VD = VS = 1.8 V / 1 V –40°C to +125°C -750 750 nA
VIH Input logic high –40°C to +125°C 1.07 5.5 V
VIL Input logic low –40°C to +125°C 0 0.68 V
IIH
IIL
IIH
IIL
25°C 1 pF
CIN Logic input capacitance
–40°C to +125°C 2 pF
POWER SUPPLY
25°C 0.006 µA
–40°C to +125°C 0.95 µA

TMUX1208

25°C 28 ns
VS = 1 V
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 48 ns
25°C 16 ns
tOPEN VS = 1 V
(BBM) RL = 200 Ω, CL = 15 pF
–40°C to +125°C 1 ns
25°C 28 ns
VS = 1 V
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 48 ns
25°C 16 ns
VS = 1 V
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 27 ns
VS = VDD/2
QC Charge Injection 25°C -2 pC
RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF
25°C -62 dB
f = 1 MHz
OISO Off Isolation
RL = 50 Ω, CL = 5 pF
25°C -42 dB
f = 10 MHz
RL = 50 Ω, CL = 5 pF
25°C -62 dB
f = 1 MHz
XTALK Crosstalk
RL = 50 Ω, CL = 5 pF
25°C -42 dB
f = 10 MHz
CSON
CDON

TMUX1208

ANALOG SWITCH
25°C 70 Ω
VS = 0 V to VDD
ISD = 10 mA
–40°C to +125°C 105 Ω
25°C 0.15 Ω
ΔRON –40°C to +85°C 1.5 Ω
–40°C to +125°C 1.5 Ω
VDD = 1.32 V 25°C ±75 nA
VD = 1.2 V / 1 V
VS = 1 V / 1.2 V –40°C to +125°C -175 175 nA
VDD = 1.32 V 25°C ±200 nA
VD = 1.2 V / 1 V
VS = 1 V / 1.2 V –40°C to +125°C -750 750 nA
VDD = 1.32 V 25°C ±200 nA

ID(ON)
IS(ON)
VD = VS = 1.2 V / 1 V –40°C to +125°C -750 750 nA
VIH Input logic high –40°C to +125°C 0.96 5.5 V
VIL Input logic low –40°C to +125°C 0 0.36 V
IIH
IIL
IIH
IIL
25°C 1 pF
CIN Logic input capacitance
–40°C to +125°C 2 pF
POWER SUPPLY
25°C 0.005 µA
–40°C to +125°C 0.8 µA

TMUX1208

25°C 60 ns
VS = 1 V
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 210 ns
25°C 28 ns
tOPEN VS = 1 V
(BBM) RL = 200 Ω, CL = 15 pF
–40°C to +125°C 1 ns
25°C 60 ns
VS = 1 V
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 190 ns
25°C 45 ns
VS = 1 V
RL = 200 Ω, CL = 15 pF
–40°C to +125°C 150 ns
VS = VDD/2
RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF
25°C -62 dB
f = 1 MHz
OISO Off Isolation
RL = 50 Ω, CL = 5 pF
25°C -42 dB
f = 10 MHz
RL = 50 Ω, CL = 5 pF
25°C -62 dB
f = 1 MHz
XTALK Crosstalk
RL = 50 Ω, CL = 5 pF
25°C -42 dB
f = 10 MHz
CSON
CDON

TMUX1208
7.9 Typical Characteristics

80 10
VDD= 1.08V 8
60 TA = +125qC TA = +85qC
On Resistance (:)
On Resistance (:)
6
40
VDD= 1.62V 4
20
2
VDD= 3V VDD= 4.5V TA = -40qC TA = +25qC
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5
Source or Drain Voltage (V) D001
TA = 25°C VDD= 3 V
Figure 1. On-Resistance vs Source or Drain Voltage Figure 2. On-Resistance vs Source or Drain Voltage
30 20
27 TON
24 16
21
12
Time (ns)
Time (ns)
18
TON
TOFF
15
8
12
9 4
TOFF
6
3 0
1.5 2 2.5 3 3.5 4 4.5 5 5.5 -60 -30 0 30 60 90 120 150
VDD - Supply Voltage (V) D003
TA - Temperature (qC) D004
TA = 25°C VDD= 3.3 V
Figure 3. TON (EN) and TOFF (EN) vs Supply Voltage Figure 4. TON (EN) and TOFF (EN) vs Temperature
30 0
-10 Bandwidth
25
-20
20 -30 Off-Isolation
Gain (dB)
Time (ns)
TTRANSITION_FALLING -40
15
-50
TTRANSITION_RISING
10 -60
-70
5
-80
0 -90
0.5 1.5 2.5 3.5 4.5 5.5 100k 1M 10M 100M
VDD - Supply Voltage (V) D005
Frequency (Hz) D006
TA = 25°C TA = 25°C
Figure 5. TTRANSITION vs Supply Voltage Figure 6. Frequency Response

TMUX1208
8 Detailed Description
8.1 Overview
8.1.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown below. Voltage (V) and current (ISD) are measured using
this setup, and RON is computed as shown in with RON = V / ISD:
ISD
Sx D
VS
Figure 7. On-Resistance Measurement Setup
8.1.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in .
VDD VDD
Is (OFF) VDD VDD
S1 S1
A
S2 ID (OFF)
S2 D
D
A
VS
S8
S8
VS
VD VD
GND GND
Figure 8. Off-Leakage Measurement Setup

TMUX1208
Overview (continued)
8.1.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. shows the circuit used for measuring
the on-leakage current, denoted by IS(ON) or ID(ON).
VDD VDD
VDD VDD
IS (ON)
S1 S1
N.C. A
S2 ID (ON) S2
D D
A N.C.
S8 S8
Vs
VS VS
VD
GND GND
Figure 9. On-Leakage Measurement Setup
8.1.4 Transition Time

Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device, system level timing can then account for the time constant added from the load resistance and load
capacitance. shows the setup used to measure transition time, denoted by the symbol tTRANSITION.
VDD
0.1…F
VDD
VDD
ADDRE SS
tr < 5ns tf < 5ns
DRIVE
(VSEL) VIH S1
VIL VS OUTPUT
D
0V S2
S8
RL CL
tTRAN SITION tTRAN SITION
A0
90%
A1
OUTPUT
VSEL
A2
10% GND
0V
Figure 10. Transition-Time Measurement Setup

TMUX1208
8.1.5 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. shows the setup
used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).
VDD
0.1…F
VDD
VDD
S1
ADDRE SS VS OUTPUT
DRIVE tr < 5ns tf < 5ns D
(VSEL) S2-S7
0V
RL CL
S8
90%
Output
A0
tBBM 1 tBBM 2
0V A1
tOPEN (BBM) = min ( tBBM 1, tBBM 2) VSEL
A2
GND
Figure 11. Break-Before-Make Delay Measurement Setup
8.1.6 Turn-On and Turn-Off Time

Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. shows the setup
used to measure transition time, denoted by the symbol tON(EN).
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. shows the setup
used to measure transition time, denoted by the symbol tOFF(EN).
VDD
0.1…F
VDD
VDD
tr < 5ns tf < 5ns
ENABL E
S1
DRIVE VS OUTPUT
VIH
(VEN) D
VIL
S2
0V RL CL
S8
tON (EN) tOFF (EN)
A0
EN
90%
A1
OUTPUT
VEN
A2
10% GND
0V
Figure 12. Turn-On and Turn-Off Time Measurement Setup

TMUX1208
8.1.7 Charge Injection
The TMUX1208 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted
by the symbol QC. shows the setup used to measure charge injection from source (Sx) to drain (D).
VDD
0.1…F
VDD
VDD
VS S1
OUTPUT
D
VOUT
0V S2
CL
S8
Output
VOUT
VS QC = CL × VOUT A0
EN
A1
VEN
A2
GND
Figure 13. Charge-Injection Measurement Setup
8.1.8 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. shows the setup used to measure off isolation. Use off isolation equation to
compute off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
S 50Q
VSIG
VOUT
RL
SX/DX
50Q
GND
RL
50Q
Figure 14. Off Isolation Measurement Setup
§V ·
Off Isolation 20 ˜ Log ¨ OUT ¸
© VS ¹ (1)

TMUX1208
8.1.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. shows the setup used to measure, and the equation used to compute
crosstalk.
0.1µF
NETWORK
VDD
ANALYZER
S1
VOUT
RL
D
50Q
VS
RL
S2 50Q
50Q
VSIG SX
RL GND
50Q
Figure 15. Channel-to-Channel Crosstalk Measurement Setup
§V ·
Channel-to-Channel Crosstalk 20 ˜ Log ¨ OUT ¸
© VS ¹ (2)
8.1.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. shows the
setup used to measure bandwidth.
0.1µF
NETWORK
VDD
ANALYZER
VS
S 50Q
VSIG
VOUT
RL
50Q
GND
Figure 16. Bandwidth Measurement Setup
§V ·
Attenuation 20 ˜ Log ¨ 2 ¸
© V1 ¹ (3)

TMUX1208
8.2 Functional Block Diagram

The TMUX1208 is an 8:1, single-ended (1-ch.), analog mux. Each channel is turned on or turned off based on
the state of the address lines and enable pin.
TMUX1208
S1
S2
S3
S4
S5 D
S6
S7
S8
1-OF-8
DECODER
A0 A1 A2 EN
Figure 17. TMUX1208 Functional Block Diagram
8.3 Feature Description

8.3.1 Bidirectional Operation
The TMUX1208 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
8.3.2 Rail to Rail Operation

The valid signal path input/output voltage for TMUX1208 ranges from GND to VDD.
8.3.3 1.8 V Logic Compatible Inputs

The TMUX1208 has 1.8-V logic compatible control for all logic control inputs. The logic input thresholds scale
with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level inputs
allows the TMUX1208 to interface with processors that have lower logic I/O rails and eliminates the need for an
external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches
8.3.4 Fail-Safe Logic

The TMUX1208 support Fail-Safe Logic on the control input pins (EN, A0. A1, A2) allowing for operation up to
5.5 V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied
before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity
by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX1208 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX1208 with VDD = 1.2 V while allowing the select pins to interface with a logic level
of another device up to 5.5 V.

TMUX1208
Feature Description (continued)

8.3.5 Device Functional Modes
When the EN pin of the TMUX1208 is pulled high, one of the switches is closed based on the state of the
address lines. When the EN pin is pulled low, all the switches are in an open state regardless of the state of the
address lines.
8.3.6 Truth Tables

Table 1 shows the truth table for the TMUX1208.
Table 1. TMUX1208 Truth Table

Selected Channel
EN A2 A1 A0
Connected To Drain (D) Pin
0 X (1) X (1) X (1) All channels are off
1 0 0 0 S1
1 0 0 1 S2
1 0 1 0 S3
1 0 1 1 S4
1 1 0 0 S5
1 1 0 1 S6
1 1 1 0 S7
1 1 1 1 S8
(1) X denotes don't care.

TMUX1208
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

The TMUX12xx family offers good system performance across a wide operating supply (1.08V to 5.5V). These
devices include 1.8V logic compatible control input pins that enable operation in systems with 1.8V I/O rails.
Additionally, the control input pins support Fail-Safe Logic which allows for operation up to 5.5V, regardless of
the state of the supply pin. This protection stops the logic pins from back-powering the supply rail. These
features make the TMUX12xx a family of general purpose multiplexers and switches that can reduce system
complexity, board size, and overall system cost.
9.2 Typical Application

One useful application to take advantage of the TMUX1208 features is multiplexing various signals into an ADC
that is integrated into a MCU. Utilizing an integrated ADC in a MCU allows a system to minimize cost with a
potential tradeoff of system performance when compared to an external ADC. The multiplexer allows for multiple
inputs/sensors to be monitored with a single ADC pin of the device, which is critical in systems with limited I/O.
VDD
VDD VI/O
VDD
LDO #1
EN
MCU
LDO #2 S1
S2 RAM FLASH
LDO #3
S3
S4
D Integrated
LM20
S5 12-bit ADC
Analog Temp.
Sensor S6
LM20 S7
Analog Temp. Port I/O TIMERS
S8
Sensor
A2
LM20 A1
A0
Analog Temp.
GND 1.8V Logic
Sensor
I/O
System Inputs &

Sensors
Figure 18. Multiplexing Signals to Integrated ADC
9.3 Design Requirements

For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters

PARAMETERS VALUES
Supply (VDD) 5.0 V
I/O signal range 0 V to VDD (Rail to Rail)
Control logic thresholds 1.8 V compatible

TMUX1208
9.4 Detailed Design Procedure

The TMUX1208 can be operated without any external components except for the supply decoupling capacitors. If
the parts desired power-up state is disabled, the enable pin should have a weak pull-down resistor and be
controlled by the MCU via GPIO. All inputs being muxed to the ADC of the MCU must fall within the recommend
operating conditions of the TMUX1208 including signal range and continuous current. For this design with a
supply of 5.0 V the signal range can be 0 V to 5.0 V and the max continuous current can be 30 mA.
9.5 Application Curve

80
VDD= 1.08V
60
On Resistance (:)
40
VDD= 1.62V
20
VDD= 3V VDD= 4.5V
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
TA = 25°C
Figure 19. On-Resistance vs Source or Drain Voltage
10 Power Supply Recommendations
The TMUX1208 operates across a wide supply range of 1.08 V to 5.5 V.. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.

TMUX1208
11 Layout
11.1 Layout Guidelines

11.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners.Figure 20 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST BETTER BEST
2W
1W min.
W
Figure 20. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, through-
hole pins are not recommended at high frequencies.
Figure 21 illustrates an example of a PCB layout with the TMUX1208. Some key considerations are:
• Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example

Via to
grou nd plane
A0 A1
EN A2 Wide (low inductance)
C
GND trace for power
N.C. Via to
grou nd plane VDD
S1
S2 S5
S3 TMUX120 8 S6
S4 S7
D S8
Figure 21. TMUX1208 Layout Example

TMUX1208
12 Device and Documentation Support
12.1 Documentation Support

12.1.1 Related Documentation
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 21-Nov-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TMUX1208PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 TM1208
& no Sb/Br)
TMUX1208RSVR ACTIVE UQFN RSV 16 3000 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 1B4
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1208PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TMUX1208RSVR UQFN RSV 16 3000 178.0 13.5 2.1 2.9 0.75 4.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMUX1208PWR TSSOP PW 16 2000 367.0 367.0 35.0
TMUX1208RSVR UQFN RSV 16 3000 189.0 185.0 36.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1 4.55
4.9
NOTE 3
8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 -8
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16
SYMM
14X (0.65)
8 9
(5.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16
SYMM
14X (0.65)
8 9
(5.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated

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Changes from Revision A (September 2018) to Revision B Page

• Added RSV (QFN) thermal information to Thermal Information: table................................................................................... 4

Changes from Original (August 2018) to Revision A Page

2 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: TMUX1208

5 Device Comparison Table

6 Pin Configuration and Functions

(1) I = input, O = output, I/O = input and output, P = power

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 3

MIN MAX UNIT

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

4 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: TMUX1208

7.5 Electrical Characteristics (VDD = 5 V ±10 %)

VDD = 5 V 25°C ±200 nA

(1) When VS is 4.5 V, VD is 1 V, and vice versa.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 5

Electrical Characteristics (VDD = 5 V ±10 %) (continued)

6 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: TMUX1208

7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)

VDD = 3.3 V 25°C ±200 nA

(1) When VS is 3 V, VD is 1 V, and vice versa.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 7

Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)

8 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: TMUX1208

7.7 Electrical Characteristics (VDD = 1.8 V ±10 %)

VDD = 1.98 V 25°C ±200 nA

(1) When VS is 1.8 V, VD is 1 V, and vice versa.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 9

Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)

10 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: TMUX1208

7.8 Electrical Characteristics (VDD = 1.2 V ±10 %)

VDD = 1.32 V 25°C ±200 nA

(1) When VS is 1.2 V, VD is 1 V, and vice versa.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 11

Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)

12 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: TMUX1208

7.9 Typical Characteristics

Figure 5. TTRANSITION vs Supply Voltage Figure 6. Frequency Response

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 13

Figure 7. On-Resistance Measurement Setup

8.1.2 Off-Leakage Current

Is (OFF) VDD VDD

Figure 8. Off-Leakage Measurement Setup

14 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

Product Folder Links: TMUX1208

Figure 9. On-Leakage Measurement Setup

8.1.4 Transition Time

tTRAN SITION tTRAN SITION

Figure 10. Transition-Time Measurement Setup