Organic Electronics 15 (2014) 1503–1508

Contents lists available at ScienceDirect

Organic Electronics
journal homepage: www.elsevier.com/locate/orgel

Numerical analysis of capacitance compact models for organic

thin-film transistors
Susanne Scheinert a,⇑, Tarek Zaki b,c, Reinhold Rödel d, Ingo Hörselmann a, Hagen Klauk d,
Joachim N. Burghartz b,c
a
Technische Universität Ilmenau, Institute of Solid State Electronics, 98684 Ilmenau, Germany
b
Institute for Nano- and Microelectronic Systems (INES), University of Stuttgart, 70569 Stuttgart, Germany
c
Institute for Microelectronics Stuttgart (IMS CHIPS), 70569 Stuttgart, Germany
d
Max Planck Institute for Solid State Research, 70569 Stuttgart, Germany

a r t i c l e i n f o a b s t r a c t

Article history: Analytical expressions for the gate-voltage dependence of the channel capacitance and the
Received 20 November 2013 gate-to-contacts overlap capacitances in top-contact organic thin-film transistors (OTFTs)
Received in revised form 31 March 2014 are derived and implemented in an organic compact capacitance model. The resulting
Accepted 10 April 2014
modified model is verified by experimental data of transistors with constant mobility.
Available online 24 April 2014
The same model is analyzed by numerical simulations for OTFTs with a voltage-dependent
mobility. The simulation results indicate that the quasistatic model describes well the sim-
Keywords:
ulated capacitances. In accumulation, the modeled values are slightly overestimated
OTFT modeling and simulation
Capacitance modeling
because of the generally accepted assumption of the charge-sheet model. It is also demon-
Voltage-dependent mobility strated that the quasistatic regime occurs at lower frequencies because of the reduced
Overlap capacitance mobility at lower charge carrier concentrations.
Ó 2014 Elsevier B.V. All rights reserved.

1. Introduction (VRH) in an exponential distributed density of states

(DOS) [9] was assumed.
In recent years substantial efforts have been made in The dynamic behavior is determined by the intrinsic
the fabrication and performance of discrete OTFTs. For and parasitic capacitances so that capacitance models are
commercial applications of these transistors in organic necessary for the description. Contrary to the DC models,
integrated circuits reliable compact models that allow the developed capacitance compact models of organic
the description of the electrical transistor behavior are transistors were not verified by experimental data since
required. The static properties are described by current– measurements of OTFTs in the quasistatic regime were
voltage (I–V) characteristics. Therefore, several DC models not available [1,3,5,10,11]. The common point of these
were developed and verified by experimental data [1–7]. models is again the consideration of the special mobility
In these models the increase of the mobility with the dependence on the gate-source voltage. As a consequence,
gate-source voltage was considered. Whereas in [2,4,7] this similar expressions have been derived with minor diverg-
mobility model was explained by the charge trapping in ing model parameters. This is confirmed in [11] where
deep tails of distributed states described by Shur and Hack the therein derived expressions are compared to the
[8], in [1,3,5,6] the model of the variable range hopping results given in [1]. Differences of the models are related
to the consideration of the overlap regions. For instance,
⇑ Corresponding author. Tel.: +49 3677693714. no expressions for the overlap capacitance are given in
E-mail address: [email protected] (S. Scheinert). [1,3,5]. In contrast, in [11,10] this capacitance is discussed

http://dx.doi.org/10.1016/j.orgel.2014.04.013
1566-1199/Ó 2014 Elsevier B.V. All rights reserved.
1504 S. Scheinert et al. / Organic Electronics 15 (2014) 1503–1508

more in detail but gate- and drain-voltage-independent a small-signal analysis was performed. In this case, the
equations are finally assumed. Such expressions are only response of the device to small sinusoidal signals superim-
valid in a source/drain (S/D) bottom-contact configuration. posed upon an established DC bias is computed as a func-
However, OTFTs are often prepared in a bottom-gate and S/ tion of frequency and DC operating point. The result is a
D top-contact (TOC) design as it offers a reduced contact complex admittance matrix. The simplified simulated
resistance [12,13]. In this configuration the S/D contacts structure is shown in the inset of Fig. 1. The used parame-
are on top of the organic layer with the result that the ters are summarized in Table 1. The values for the relative
overlap capacitances are voltage-dependent. permittivity of the insulator, the DNTT thickness and the
In [17] the measured gate-source ðC gs Þ and gate-drain doping concentration were extracted from the measured
ðC gd Þ capacitances of the prepared OTFT with constant capacitance–voltage curve for a drain-source voltage
mobility were modeled assuming the simple Meyer’s V DS ¼ 0 V (shown in [17]). The concentration of fixed inter-
capacitance model [18] and constant overlap capacitances face states was assumed to fit the flat-band voltage (V FB ).
despite of the TOC design. With the given parameters and V TH ¼ V FB þ eNA d=C 00is a
In this paper, we derive an expression to consider the threshold voltage of V TH ¼ 1:2 V results. C 00is is the insula-
gate- and drain-voltage dependence of the gate-to-con- tor capacitance per area. The intrinsic mobility was esti-
tacts overlap capacitances in S/D TOC transistors. This mated from measured current–voltage characteristics of
equation and a gate-voltage dependent channel capaci- the OTFT [17]. For these transistors no dependence of the
tance (an expression similar to the one in [18]) are imple- mobility on the gate-source voltage was observed.
mented in the organic capacitance model of [11] originated For the investigation of the capacitance model derived
from the DC model in [6] in which the mobility enhance- in [11], the voltage-dependent mobility model described
ment factor is explained either by charge trapping or by in [19] was implemented. This model is based on the hop-
VRH in an exponential DOS. The influence of contact resis- ping model of [9] only modified by the lateral field
tance effects, such as described in [14–16], are not consid- dependence.
ered in this paper.
For organic transistors with a constant mobility, the
4. Experimental and simulated results
modified model is verified against experimental data
adopted from [17]. For transistors with a voltage-depen-
As described above, in [17] the measured capacitances
dent mobility, the model of Marinov and Deen [11] is veri-
of the OTFTs were modeled with the Meyer’s capacitance
fied by two-dimensional device simulations in the
model [18]. Here, the quasistatic capacitance model
quasistatic regime. For this purpose, the voltage-dependent
mobility model for VRH in an exponentially distributed DOS
[19] was implemented in the Sentaurus Device simulator 400
[20]. Furthermore, the frequency dependence of the transis- Cgs
tor capacitances was investigated by the simulation. From 300
measured
Modeled [11] with
these results, the frequency was estimated up to which
Cgx (pF)

Cgxovby Eq. (3)

the quasistatic assumption is valid for the OTFT. "
200 Cgxov=W*Lgx*Cis
"
Cgxov=W*Lgx*Cgeo
2. Transistor fabrication 100 Cgd
(a)
OTFTs in a bottom-gate/top-contact design are pre- 0
pared on an alkali-free glass substrate covered with a thin -3 -2 -1 0
VDS (V)
(4 nm) adhesion layer of aluminum oxide [17]. The hybrid
dielectric on top of the aluminum gate consist of an oxy-
gen-plasma-grown AlOx layer (3.6 nm-thick) and a solu- 400
Cgs
tion-processed self-assembled monolayer (SAM) of n- Lgs L Lgd
tetradecylphosphonic acid (1.7 nm-thick). The active layer 300 Au
Au Au
Cgx (pF)

DNTT
of the OTFT, namely the 11-nm-thick organic semiconduc- AlOx+SAM
Al
tor (OSC) dinaphto[2,3-b:20 ,30 -f]thieno[3,2-b]thiophene 200
(DNTT) [21] and finally 25-nm-thick gold S/D contacts
were evaporated through silicon stencil masks [22]. The 100
transistors have a channel length and width of
Cgd (b)
L = 200 lm and W = 400 lm, respectively. The gate-to- 0
source (Lgs ) and gate-to-drain (Lgd ) overlaps are symmetri- -3 -2 -1 0
cal with Lgs ¼ Lgd ¼ 10 lm. VGS (V)

Fig. 1. Data adopted from [17] at a frequency of f ¼ 500 Hz and modeled

3. Simulation method quasi-static gate-source (C gs ) and gate-drain (C gd ) capacitances as a
function of V DS with V GS ¼ 3 V (a) and V GS with V DS ¼ 0:5 V (b),
respectively. Lines represent the model by [11] including the voltage
Numerical simulations have been carried out with the dependence of the channel capacitance, a constant fringe part of 13% and
Sentaurus Device simulator solving the Poisson and conti- the indicated equations of the overlap capacitances. The inset shows the
nuity equations [20]. To investigate the OTFT capacitances OTFT schematic representation used for the simulation.
 S. Scheinert et al. / Organic Electronics 15 (2014) 1503–1508 1505

Table 1 4.1. Channel and overlap capacitances

Simulation parameters.

Parameter Symbol Value In the model of [11] the channel capacitance C G0 is

Al-gate work function /Al 4:1 eV related to the insulator capacitance but this is only valid
Au-contacts work function /Au 5:0 eV for accumulation at the insulator interface. In depletion,
Hybrid dielectric thickness dis 5:3 nm the channel capacitance C ch is reduced. Therefore, we
Dielectric rel. permittivity eis 3:37 introduce a gate-voltage dependent expression equal to
DNTT affinity v 1:81 eV
the first summand of Eq. 6 with V X ¼ 0 (similar to the
DNTT band gap EG 3:38 eV
DNTT relative permittivity e 3 one in [18,3]) for C ch instead of C G0 to describe correctly
DNTT thickness d 11 nm the decrease of the gate-source capacitance near and
DNTT intrinsic mobility l 2:1 cm2 =V s below the threshold voltage.
DNTT doping concentration NA 1016 cm3 Furthermore, the extrinsic capacitances due to the
Fixed interface charges N if 1:1  1012 cm2 overlap regions of the gate with source (C gsov ) and drain
(C gdov ) will be considered. These capacitances have to be
added to the respective intrinsic capacitances. In [10] these
described in [11] will be applied. This model is based on capacitances are calculated with C ov ¼ WLov C 00is , only valid
the voltage-dependent mobility given in [6] for a S/D bottom contact structure. Contrary, in [17] the
2T  series connection of the insulator capacitance with the
0 2 one of the fully depleted semiconductor (C geo ) of the con-
l ¼ l0 ðV GS  V TH Þ T ¼ l0 ðV GS  V TH Þc ð1Þ
tact region is used for the S/D TOC OTFT. However, in this
with the gate-source voltage V GS , the threshold voltage V TH configuration a transition from the maximum capacitance
and the mobility at a low carrier concentration l0 . The C 00is down to the minimum value C 00geo depending on the oper-
parameter T 0 (and accordingly c) describes the steepness ation regime of the OTFT occurs. Consequently, here we
of the exponentially distributed DOS introduce an expression similar to the voltage dependence
of the channel capacitance for the overlap capacitances
 
Ns E  Eref
DOSðEÞ ¼ exp ð2Þ C 00is C 00geo
E0 E0 C 00ov ¼ þ ð6Þ
V GT V X V d
1 þ exp V SS
1 þ exp  V GT V X V d
V SS
where N s is the concentration of states, Eref is the conduc-
tion (or valence) band edge and E0 is the effective energy where V GT ¼ V GS  V TH and V d is a voltage fit parameter.
width E0 ¼ kT 0 . The resulting quasistatic gate charge is The voltage V X ¼ 0 or V X ¼ V DS for the overlap capaci-
given by (Eq. (18) in [11]) tances gate to source ðC gsov ¼ W Lgs C 00gsov Þ and gate to drain
ðC gdov ¼ W Lgd C 00gdov Þ, respectively. V SS is a voltage parame-
  c 3þc
2 þ c V 3þ
GTS  V GTD
ter introduced in [6] describing the inverse subthreshold
Q G ¼ C G0 c c ð3Þ slope. The parameter V d is introduced since depletion at
3 þ c V GTS  V 2þ
2þ
GTD
the insulator interface and associated with it the decrease
with the overdrive voltages V GTS ¼ V G  V T  V S and of the channel and overlap capacitances occurs above the
V GTD ¼ V G  V T  V D and the capacitance C G0 ¼ WLC 00is . The threshold voltage.
intrinsic capacitances C GG and C GD are the derivatives of Fig. 1 shows the measured capacitances at f ¼ 500 Hz
this charge with respect to the terminal voltages resulting along with the quasistatic curves calculated with the mod-
in Eq. (23) and (24) in [11]: ified model in [11] for constant mobility (c ¼ 0). The pre-
pared OTFT works in the quasistatic regime at this
  !" #
C GG 2 þ c 1  f3þc ð2 þ cÞf1þc frequency (see below). The modeled curves include the
¼ 1 þ ð1  fÞ  sum of the intrinsic and parasitic components. A contribu-
C G0 3 þ c 1  f2þc 1  f2þc
tion of about 13% was assumed for the fringe part. The
ð2 þ cÞf1þc transition into the subthreshold region is well described
 ð1  fÞ ð4Þ
1  f2þc by the included gate-voltage dependent channel capaci-
tance. The curves differ in the assumed model for the over-
  ! " # lap capacitances. Applying the constant insulator
C GD 2 þ c 1  f3þc ð2 þ cÞf1þc ð2 þ cÞf1þc capacitance (dashed green lines), the influence of the over-
¼ c  c  ð5Þ
C G0 3þc 1f 2þ
1f 2þ
1  f2þc lap regions is overestimated whenever depletion of the
semiconductor occurs in the contact regions. This is the
with f ¼ V GTD =V GTS . The capacitance C GS is obtained from case at low gate-source voltages (subthreshold) or at high
C GG ¼ C GD þ C GS . negative drain voltages (saturation). Using the geometric
In the case of a constant mobility (c ¼ 0), the derived capacitance (blue dash-dotted lines) smaller values are cal-
expressions for the capacitances reduce to the ones of the culated for the linear operation regime of the OTFT. In the
Meyer model and the experimental curves can be well latter case a fit to the measured curves is possible by
described as shown in [17]. Nevertheless, the curves will increasing the fringe factor. However, as a consequence,
be shown once more to demonstrate the quality of the the parasitic components are not exactly described. On
voltage-dependent expressions of the channel and overlap the contrary, the modeled curves including Eq. (6) with
capacitances. V TH ¼ 1:2 V; V SS ¼ 0:1 V and V d ¼ 0:2 V fit very well the
1506 S. Scheinert et al. / Organic Electronics 15 (2014) 1503–1508

measured capacitances. This is also visible in Fig. 2 where a ¼ 0:58  108 cm1 . The prefactor r0 ¼ 1:5  108 S=cm
the curves at different bias conditions are shown. Conse- was used to get a mobility of about 2 cm2 =V s at an applied
quently, the Marinov/Deen model, modified by the new gate-source voltage of 3 V. In Fig. 3 the simulated capac-
expression of the channel capacitance, describes well itances are compared to the results obtained for the model
OTFTs with constant mobility. But for the S/D TOC design [11] including the voltage dependence of the channel and
one has to include additionally the voltage-dependent overlap capacitances. To model the capacitance in the
expressions for the overlap regions (Eq. 6) to model cor- accumulation region, the generally accepted approxima-
rectly all the operation regimes of the transistors. The anal- tion of a conductive sheet near the interface to the dielec-
ysis of the model for OTFTs with a voltage-dependent tric is assumed. Consequently, the low-frequency MIS
mobility is presented in the following section. (metal–insulator–semiconductor) capacitance is close to
the dielectric capacitance C is . However, in the real device
4.2. Influence of voltage-dependent mobility there is a distribution of mobile carriers with depth also
in accumulation. This distribution is accurately simulated
The influence of a voltage-dependent mobility on the and therefore the capacitances are a little bit smaller than
intrinsic capacitances of an OTFT is described in detail in the dielectric capacitance because of the series connection
[11]. In conclusion, with increasing mobility enhancement with the semiconductor capacitance. For this reason, the
factor c the gate-source capacitance increases and the values of the modeled gate-source capacitances were
gate-drain capacitance decreases. Since measurements in divided by a factor of 1.06 . . . 1.08 to better fit the simu-
the quasistatic regime for OTFTs with voltage-dependent lated curves. With exception of this peculiarity, the mod-
mobility are not available yet, the applicability of the eled curves describe well the simulated capacitances.
model will be investigated by numerical simulation. Therefore at low frequencies, the model of Marinov/Deen
As given with Eq. (1), the parameter c increases for a [11] extended by analytical expressions for the channel
broader DOS distribution. As justified below, the quasistat- and overlap capacitances can also be applied for organic
ic assumption for OTFTs with voltage-dependent mobility transistors with bias-dependent mobility. However, one
is only valid at lower frequencies. Therefore, numerical has to investigate up to which frequency quasistatic
simulations at a frequency of f ¼ 1 Hz applying the mobil- behavior occurs.
ity model described in [19] with T 0 ¼ 600 K (c ¼ 2) have
been carried out. Further used mobility parameters are
Bc ¼ 2:8 corresponding to the formation of an infinite clus-
ter and the inverse decay length of the wave function
400
(a)
400 300 simulated
(a)
Cgx (pF)

modeled Cgs
300 200
VGS= -2V VGS= -2V
Cgx (pF)

Cgs
VGS= -2.5V VGS= -2.5V
200 100
VGS= -3V VGS= -3V
Cgd
measured 0
100
modeled -3 -2 -1 0
Cgd VDS (V)
0
-3 -2 -1 0
VDS (V) 400
Cgs (b)
simulated
400 300 modeled
(b)
Cgx (pF)

VDS=0V
Cgs measured 200 Cgd VDS=-0.5V
300 modeled
Cgx (pF)

VDS=-1V
Cgd VDS=0V
200 100 VDS=-1.5V
VDS=-0.5V
VDS=-1V
100 0
VDS=-1.5V -3 -2 -1 0
VGS (V)
0
-3 -2 -1 0
Fig. 3. Simulated (f ¼ 1 Hz) and modeled quasi-static gate-source (C gs )
VGS (V) and gate-drain (C gd ) capacitances as a function of V DS (a) and V GS (b),
respectively. Lines represent the model by [11] including the voltage
Fig. 2. Data adopted from [17] at a frequency of f ¼ 500 Hz and modeled dependence of the channel capacitance and the overlap capacitances
quasi-static gate-source (C gs ) and gate-drain (C gd ) capacitances as a calculated by Eq. (6). The modeled gate-source capacitance is divided by a
function of V DS (a) and V GS (b), respectively. Lines represent the model by factor of about 1:06 . . . 1:08 to better fit the simulated curves. This is
[11] including the voltage dependence of the channel capacitance, a because the simulation takes into consideration an additional series
constant fringe part of 13% and the overlap capacitances calculated by Eq. capacitance owing to the distribution of mobile carriers with depth in the
(6). DNTT also in accumulation.
 S. Scheinert et al. / Organic Electronics 15 (2014) 1503–1508 1507

2.5 12 400
Cgd Cgs (a)
2.0 10 300 f=1Hz

hole density (10 cm )

CGX (pF)
f=500Hz
mobility (cm /Vs)

f=1kHz
8 200 f=10kHz
1.5
2

f=50kHz
6 100
1.0

19
4 0
0.5 -3 -2 -1 0
VGS (V)

-3
2
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 400
Cgd Cgs (b)
300 f=1Hz
Fig. 4. Simulated low-frequency (f ¼ 1 Hz) values of the mobility (dashed

CGX (pF)
lines) and hole density (solid lines) near the interface to the dielectric and f=500Hz
different positions along the channel for V DS ¼ 0:5 V and different V GS . 200 f=1kHz
The position x ¼ 10 lm is directly at source and the middle of the channel f=10kHz
is at x ¼ 110 lm. f=50kHz
100

0
4.3. Frequency dependence of the capacitances -3 -2 -1 0
VGS (V)
In Fig. 4 simulated low-frequency values of the mobility
and hole density near the interface to the dielectric are Fig. 5. Simulated gate-source (C gs ) and gate-drain (C gd ) capacitances at
shown to demonstrate what the peculiarity in the case of different frequencies for V DS ¼ 0:5 V as a function of V GS for constant
a voltage-dependent mobility is. To get these results, a (c ¼ 0) (a) and voltage-dependent mobility (c ¼ 2) (b).

sinusoidal signal was applied at source superimposed upon

the established DC bias. At V GS ¼ 3 V, the average value of
dependent. This effect is shown in Fig. 6. For the depicted
the mobility near source (x ¼ 10 lm) is about 2 cm2 =V s. At
frequencies, no difference in the charge variation is simu-
the lower negative gate-source voltage, but even in accu-
lated in transistors with a constant mobility. However, in
mulation, the mobility at this position is reduced by a fac-
OTFTs with a voltage-dependent mobility, the accumu-
tor of about 3. Furthermore, since the hole density (solid
lated charges cannot follow the signal. Therefore, as the
lines) depends on the position along the channel also the
frequency increases, the gate charge variation reduces
mobility (dashed lines) is position dependent at both gate
and a phase shift occurs resulting in reduced gate-source
bias. Therefore, a modified frequency behavior of the
capacitances.
capacitances compared to the case of constant mobility is
In conclusion, in the case of the assumed mobility
expected.
parameters, the transistor works in the quasistatic regime
To verify this prediction a small-signal analysis with the
up to a frequency of only 1 Hz. Since some of the material
device simulator was performed. Fig. 5 shows the simu-
and device parameters (doping concentration, flat-band
lated capacitances at different frequencies for OTFTs with
voltage) can only be estimated from quasistatic CV curves,
both a constant mobility and a voltage-dependent mobil-
ity. Comparing figure (a) and (b), the above-described ten-
dencies regarding the influence of the mobility
-4.4
enhancement factor are visible. At the highest gate-source f=1Hz f=500Hz f=1kHz
voltage C gs is higher in figure (b) whereas C gd is smaller. As 0.1
gate charge (10 As/cm )
2

expected for an applied drain-source voltage, in both cases

source voltage (V)

for c the gate-drain capacitance is smaller than the gate- -4.8

source one and noticeable influence on C gd occurs for fre-
-7

quencies f > 1 kHz. Contrary, the simulated gate-source 0.0

capacitances depend strongly on the used mobility model. -5.2
For OTFTs with a constant mobility, a negligible difference
is simulated between the curves at 1 Hz and 500 Hz so that
quasistatic behavior can be assumed also for the higher -5.6
frequency. But in transistors with a voltage-dependent -0.1
voltage-dependent constant source voltage
mobility, the gate-source capacitance at 500 Hz is strongly
0.0 0.2 0.4 0.6 0.8 1.0
reduced for negative gate-source voltages smaller than 2 V.
t/tmax
The reason is the above-described lower mobility at these
gate biases resulting in a higher time constant. Since Fig. 6. Simulated gate charge for V GS ¼ 2 V and V DS ¼ 0:5 V as a
C gs ¼ @Q G =@V S the variation of the gate charge caused function of time (time divided by maximum time for three periods) with
by a sinusoidal signal at source should be frequency sinusoidal signal applied at source.
1508 S. Scheinert et al. / Organic Electronics 15 (2014) 1503–1508

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