VLSI Design

Chapter 1

Introduction to CMOS Circuit

Design

Jin-Fu Li
 Chapter 1 Introduction to CMOS Circuit Design

• MOS transistor switches

• CMOS logic
• Circuit and system representation
• CMOS Score Board

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 MOS Transistor - NMOS
gate gate oxide
Polysilicon
field oxide source drain
N+ N+
Cross
P+ field
section
implant
P-substrate

poly
G G

Notation layout
S D S D S G D

diffusion

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 CMOS Switches - Basic
• NMOS symbol and characteristics
Vth
5v
5v 5v-Vth
0v 0v

• PMOS symbol and characteristics

0v Vth
5v 5v
0v Vth

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 CMOS Switches
• A complementary CMOS switch (Transmission
gate)

-s -s

Symbols a C b a b a b

s s s

0v
5v 5v
Characteristics 0v 0v
5v

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 CMOS Logic - Inverter
• Symbol and operation of the inverter
Vdd

Vin Vout Vin Vout

Vdd Vdd Vdd

Vdd/2 Indeterminate
0 1 1 0
logic level

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 Combinational Logic
• Serial structure
S1=0 S1=0 S1=1 S1=1
a S2=0 S2=1 S2=0 S2=1
S1
0 1
S1
0 a!=b a!=b
S2
S2 1 a!=b a=b

b
S1=0 S1=0 S1=1 S1=1
a S2=0 S2=1 S2=0 S2=1
S1
0 1
S1
0 a=b a!=b
S2
1 a!=b a!=b
S2

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 Combinational Logic
• Parallel structure
S1=0 S1=0 S1=1 S1=1
a S2=0 S2=1 S2=0 S2=1 S1
0 1
0 a!=b a=b
S1 S2 S2
1 a=b a=b

b
S1=0 S1=0 S1=1 S1=1 S1
a S2=0 S2=1 S2=0 S2=1
0 1
0 a=b a=b
S1 S2 S2
1 a=b a!=b

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 NAND Gate

Output A
A 0 1

0 1 1
B B
1 1 0

A
Output
B

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 NOR Gate

B A
0 1
Output
0 1 0
B
1 0 0

A
Output
B

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 Compound Gate
• F = (( AB) + (CD))

A B

A
C D B
F
F C
D
A C

B D

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 Properties of static CMOS
• The voltage swing is equal to the supply voltage
− High noise margin

• The logic levels are not dependent on the relative device

sizes
− Ratioless
• In steady state, there always exists a path with finite
resistance between the output and either Vdd or GND
− Low output impedance

• The gate of an MOS transistor us a virtually perfect

insulator
− High input resistance

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 CMOS Logic - Multiplexer
A 11
B 10
C 01 Y
A 1 Y D 00
B 0

S S1 S0
-S A

A
B
Y Y
S
B C

-S D

S1 -S1 S0 -S0

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 CMOS Logic - Latches

D -Q

Q
CLK

D D
-Q -Q

CLK

Q Q

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 CMOS Logic – Flip Flops
Master Slave
-Q
D Q

CLK
-Q -Q
D Q D Q

CLK

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 Circuit & System Representations
• Behavioral representation
− Functional, high level
− For documentation, simulation, verification

• Structural representation
− System level – CPU, RAM, I/O
− Functional level – ALU, Multiplier, Adder
− Gate level – AND, OR, XOR
− Circuit level – Transistors, R, L, C
− For design & simulation
• Physical representation
− For fabrication

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 Behavioral Representation
• A one-bit full adder (Verilog)

module fadder(sum,cout,a,b,ci);
a b
output sum, cout;
input a, b, ci;
reg sum, cout;
ci fadder cout

always @(a or b or ci) begin

sum = a^b^ci;
cout = (a&b)|(b&ci)|(ci&a); sum
end
endmodule

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 Structural Representation
• A four-bit adder (Verilog)
a b
module adder4(s,c4,a,b,ci);
output[3:0] sum;
a[0] b[0] a[1] b[1] a[2] b[2] a[3] b[3]
output c4;
input[3:0] a, b; co[0] co[1] co[2]
ci a0 a1 a2 a3
input ci;
c4
reg[3:0] s; s[0] s[1] s[2] s3]
reg c4;
wire[2:0] co;
s adder4
fadder a0(s[0],co[0],a[0],b[0],ci);
fadder a1(s[1],co[1],a[1],b[1],co[0]);
fadder a2(s[2],co[2],a[2],b[2],co[1]);
fadder a3(s[3],c4,a[3],b[3],co[2]);
endmodule

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 Physical Representation
• Layout of a four-input NAND gate

Vdd

in1 in2 in3 in4

Out
in1

Out in2

in3

in4

Gnd

in1 in2 in3 in4

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 Scorecards
• Full restored logic level, i.e., output settles at Vdd or Vss
• Transition times – rises and fall times are of the same order
• Memories are implemented both densely and with low power
dissipation
• Transmission Gates pass both logic levels well
• Power dissipation – almost zero static power dissipation for fully
complementary circuits
• Precharging Characteristics – both n-type and p-type devices are
available for precharging a bus to Vdd and Vss
• Power supply – voltage required to switch a gate is fixed percentage of
Vdd
• Packing density – requires 2n devices for n inputs for complementary
static gate
• Layout – CMOS encourages regular and easily automated layout styles

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