An Ultra Low Power 5 - Phase Ring Oscillator Using Lector Technique

Volume 3, Issue 10, October – 2018 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
An Ultra Low Power 5 – Phase Ring Oscillator using

Lector Technique
Suraj Singh Bhadouria1, Nikhil Saxena2
PG Scolar1, Assistant professor 2
Department of Electronics & Communication Engineering, ITM Gwalior
Abstract:- In this current article 5- stage ring oscillator communications, musical instruments etc. which are
designed with lector technique for reduction in leakage especially designed [3]. They can be made from the cascaded
power without increasing the propagation delay. a lector stages of inverter along with the LC tank circuits which
technique to used two LCT transistor in which one of p- depends over the frequency range which is essential and
type and another one is n-type at each stage of ring required. The main function of a conventional ring oscillator is
oscillator and LCT is manage by source of second LCT producing oscillations varying from MHz range of frequency
transistor. In this current article is simulate and compare oscillation can be changed by adding stages number to it.
the various parameter are power dissipation, frequency, Although the adding number of levels affects the oscillation
average power of 5- stage ring oscillator based CMOS as frequency as enhancing the number of levels increases the
well as CNT at 32nm transistor based technology with the circuit’s propagation delay [4]. The practical acceptance of the
help of lector technique then comparison CNT based addition of stages beyond 9 is negligible as the dissipation of
transistor better result display as compare to the CMOS the power is enhanced in the circuits and if the oscillations are
based transistor using SPICE simulation tools. being added in several hundreds of inverter stages then the
oscillations of the frequency obtained is low whose further
Keywords:- CMOS, carbon nano tube (CNT), lector, leakage application is impractical and its fabrication and designing is
power, leakage current. not possible [5]. The best future nano-electric circuit is
CNTFET circuit. This is the best and possible transistor for the
I. INTRODUCTION future purposes. The conventional technology of CMOS
approaches its physical limits which are fundamental whilst
From the former two decades the electronic industries the downscaling as reported by Moore’s law for the digital
have acquired an exceptional excellent growth. This rapid electronic is performed and done by CNTFET. In today’s
change in the market exists because of the quick and the rapid world as the significance and the consequence of the system-
advancement in the technologies which are integrated because on-chips is increased therefore for the verification of the
of the VLSI advent. In the current scenario the market has digital circuit performance, the only parameter to verify and
been captured via wireless devices being computers, GPS, cell check it should not only be the digital performance. CNTFET
phone, Wi-Fi, Bluetooth etc. these aforementioned devices are functions over transistor which is based on single carbon. This
compact and they also make the wireless data available to CNTFET was first introduced in 1998, since then there have
other devices. There are certain frequencies which are to be been disparate alterations and changes done in it and if
worked upon for the transmittance and the receiving of the counted or developed according to the Moore’s law each year
data [1]. There is a common circuit which is being used as a the transistor should be double [6].
key for the modern communication is VCO. In any of the RF
transceivers, CMOS VCO which is integrated completely II. LITERATURE REVIEW
exhibits a significant block. The main function of an oscillator
is generating an analog and periodic signal whose frequency is Mahani et.al (2017) reported a new fault tolerant delay
stable and predictable. The output frequency provides AC cell for ring oscillators. In the phased and delayed locked loop
waveform depends over the input voltage. A controllable and the clock data recovery, RO is considered as better crucial
frequency from a clock is generated by VCO. In this circuits blocks, if discovered at faults they should be stuck for harsh
to be used phase locked loop for the generation of clock VCO environments and shouldn’t be tolerated against SET (single
[2]. event transient). ). Hybrid tolerant fault topology to be design
of delay cell whose is dependent and based over the role of
Regarding the ring oscillators, there are several sensitivity of each transistor. The mixture of three and four
applications of oscillators which form the vital building blocks transistors redundancy forms hybrid tolerant fault topology.
in the circuits of RF and various mixed signals. The targeted The software used by them is Cadence; their simulation results
field of applications varies along with the frequency of exhibit the fault tolerant delay cell dissipation of 34.34 µW
oscillators. It ranges and varies from Hz to MHz. Like all power occupying the chip area of 127.2 µm2. This technology
those oscillators pursuing high frequencies are utilized in which was proposed by them exhibited decrease in the power
phase locked loops, cyclotrons etc and there are various consumption when compared to the current fault tolerant delay
oscillators pursuing low frequency are utilized in radio cells. Simultaneously, they depicted more reliability against
IJISRT18OC374 www.ijisrt.com 684

ISSN No:-2456-2165
single and multiple stuck faults along with SETs. If this input. The path resistance is increased to ground and therefore
proposed reliable delay cell was used in the ring oscillators, the leakage current is decreased. First net-listing to the gate
the acquired dissipation of power and the phase noise were level is converted to complex gate implementation in the given
about 249 µW and -96dBc/Hz respectively. Their higher CMOS circuit, after this the introduction of the LCTs take
reliability was to be acquired when they were compared to place to attain a circuit which is leakage controlled. The
non-redundant ring oscillators [9]. importance of LECTOR technique is that it efficiently works
in active as well as idle circuit state and when the results are
Wu et.al (2017) stated the design ring oscillator which compared they found that the leakage reduction was better in
was applied using a pseudo-CMOS inverter; this was realized LECTOR than other techniques. The limitations which were
by n type transistors. They compared 11 stages using the exhibited by several other existing methods regarding the
conventional as well as proposed ring oscillator but both of reduction of leakage were overcome by their proposed
them were fabricated by thin film metal oxide transistors method. The average leakage reduction found in their
comprising of the structure of etch stop layer. The results and experimental results were 79.4% in MCNC benchmarks
the investigations depicted the delay product of power more circuits [7].
than 50% by the proposed technology using the same supply
voltage value. Oscillation frequency is increased the III. RESEARCH METHODOLOGY
consumption of the power is reduced by 18% over the similar
oscillation frequency. At the supply voltage a full swing can In the family of oscillator, a ring oscillator circuit is a
be received by acme voltage using their proposed ring simple way of scheme to reducing power dissipation. Ring
oscillators [10]. oscillator also called the relaxation oscillator so that the old
number of inverter are connected in series connection and to
Dhakad et.al (2017) stated VCO design in which the obtain a natural oscillation as shown in a figure (1) CMOS
technique used was injection locking. The software used based transistor to be used for design 5 stage ring oscillator. In
through which all the simulations were performed was this circuit input of first inverter are connected to the output of
Virtuoso Cadence Analog Design Environment using the SCL final inverter. Therefore the name of this circuit is ring
180 nm CMOS process. The simulation results exhibited oscillator.
150% tuning range was achieved by VCO over the range of
508 MHz to 3.56 GHz with phase noise of -126 dBc/Hz at 1
MHz offset frequency. When the voltage supply was 1.8V
then the dissipation of the power of the circuit as an output
was obtained to be 110.4µW [11].
Balaji et.al (2016) reported a novel method for designing

low frequency CMOS ring oscillator producing the range of 1
Hz. The oscillator is designed in such a way that it comprises
of structure of CMOS thyristor which was designed with the
current mirror producing low frequency oscillations attaining
less space of device comparing to conventional N stage ring Fig 1:- 5- stage ring oscillator with CMOS technology
oscillators. To achieve oscillations to the desired aspect ratios
as well as the device parameters are designed with 90 nm Now design 5- stage ring oscillator with carbon nanotube
technology. For analyzing the oscillator performance they transistor based technology because CNT reduce leakage
investigated variation effect of voltage and temperature over power due to smaller and shorter channel length and CNT
frequency and the results of the simulations are exhibited [8]. made of rolded sheet of grapheme so that it is like a
cylindrical shape as showing in a figure (2).
Hanchate (2004) reported the enhancement of the
leakage current sub-threshold along with increase in power
dissipation to be statics which takes place due to the decrease
in the threshold voltage because of the scaling of the voltage
in the CMOS circuits. They proposed a LECTOR technique
for CMOS gates designing, as these gates without enhancing
the dynamic power consumption to be decreases leakage
current. In their technique they have introduced two LCT
transistors within the reach of the logic gates. In these logic
gates the terminal of the gate of each control transistor is not Fig 2:- five stage ring oscillator with CNT technology
controlled by itself they are controlled by the other sources.
The arrangement is made in such a way that one of the LCT is Lector technique to apply in CMOS based 5 stage ring
always “near its cutoff voltage” regarding the combinations of oscillator as showing in a figure (3). In this circuit (a) is the

ISSN No:-2456-2165
input/output node, five inverter is connected in parallel at each lector CNT. The transient retaliation of lector CMOS are
inverter has made of one PMOS and other one NMOS captured in the figure (5).
transistor in that circuit.
Fig 5:- Transient retaliation of lector CMOS

Fig 3:- 5 stage ring oscillator design with CMOS technology
with lector technique Now transient retaliation of lector CNT is captured in the
figure (6). The transient retaliation of CMOS lector is
In the control box, Leakage controlled transistor (LCT) simulated using the spice tools with 32nm channel length at
is attached in series connection of each five inverter M2 1V and the transient
(PMOS) and M3 (NMOS) which are LCT. Leakage controlled
transistor are join among pull up and pull down network. Gate
terminal M2 is connect to the source of M3 and gate M3 is
connect to the source M2. Similarly design CNT transistor
based ring oscillator operates lector technique as showing in a
figure (4).
Fig 6:- Transient analysis of lector CNT
response of CMOS and CNT without lector technique

generates oscillation frequency to 335MHz to 365MHz with
110% truing where as the transient response of CMOS and
Fig 4:- CNT transistor based ring oscillator circuit applying CNT with lector technique is simulated using spice tools with
lector technique 32nm channel length at 1V then transient response of CMOS
and CNT with lector technique is generate more oscillation
IV. SIMULATION AND RESULT frequency to 335MHz to 365MHz with 160% turning and the
number of oscillation is more than the CMOS and CNT with
The proposed design is simulated using spice tool at
lector technique.
32nm. The length and width are taken as L=32nm and
W=32nm at 1V supply is applied. First of all 5-stage ring
oscillator is simulation with CMOS and CNT technology.
Then second rig oscillator simulates with lector CMOS and
Performance LECTOR LECTOR

parameter CMOS CNT CMOS CNT
Technology 32nm 32nm 32nm 32nm
Supply voltage 1V 1V 1V 1V
Frequency 300MHz 340MHz 335MHz 365MHz
Leakage power 29.01E-10W 5.579E-10W 1.517E-10W 6.085E-05W
Leakage current 29.01E-10A 5.579E-10A 1.517E-10A 6.085E-05A
Table 1:- comparison with CMOS, CNT, lector CMOS, and lector CNT with spice tools.

ISSN No:-2456-2165
The result are simulated of proposed circuit with application in 65 nm CMOS technology, IET Circuits
pervious work are shown in table (1). In this table determine Devices Syst., 2018, Vol. 12 Iss. 3, pp. 233-241.
the four parameter using spice tools with 32nm such as [10]. Jian-Dong Wu, Fan Zhan, Lei Zhou, Wei-Jing Wu ,
leakage power, leakage current, frequency, average power at Member, IEEE, Miao Xu, A Low-Power Ring Oscillator
1V. Using Pull-Up Control Scheme Integrated by Metal–
Oxide TFTs, IEEE Transactions On Electron Devices,
V. CONCLUSION Vol. 64, No. 12, December 2017.
[11]. Narendra Singh Dhakad, R. C. Gurjar, A Wide Tuning
A 5- stage ring oscillator was successfully designed and Range Voltage Controlled Ring Oscillator Using
simulated using spice tools at 32nm channel length. The main Injection Locking, Proceeding International conference
target of this paper is to be reduced the power dissipation and on Recent Innovations is Signal Processing and
leakage power. We create the previous paper work by Embedded Systems (RISE-2017) 27-29 October, 2017.
reducing voltage and using CNT technology and the result in
the table (1) presently comparison between CMOS and CNT.
According to the acquired simulation results we judge that the
proposed 5- stage ring oscillator with lector technique perform
better result in the term of power dissipation and leakage
current is reduce 23% at 1V. thus this lector technique to
control leakage power for the circuit designers.
REFERENCE
[1]. Ahmet Tekin, Mehmet R. Yuce, and Wentai Liu,

“Integrated VCO Design for MICS Transceivers”, IEEE
Custom Integrated Circuits Conference (CICC) 2006.
[2]. S.L. Jang, Y.H. Chuang, S.H. Lee, L.R. Chi, and C.F.
Lee, “An Integrated 5–2.5 GHz Direct-Injection Locked
Quadrature LC VCO”, IEEE Microwave And Wireless
Components Letters, vol. 17, no. 2, February 2007.
[3]. Ajay Kumar Mahato, “Ultra Low Frequency CMOS
Ring Oscillator Design,” Proceedings of RAECS UIET
Panjab University Chandigarh, 06 – 08 March, 978-1-
4799-2291-8/14,” IEEE2014.
[4]. Shruti Suman, Monika. Bharadwaj, and B.P. Singh, “An
Improved Performance Ring Oscllator Design,” IEEE
Computer Society, pp. 236-239, 2012.
[5]. Piyush Keshri, Biplab Deka, "CMOS Thyristor based
Low FrequencyRing Oscillator," Indian Institute of
Technology, Kanpur.
[6]. Chandramohan K, Nikhil Saxena, Sapna Navre, Sonal
Soni, Carbon Nanotube Transistor Based Novel Ring
Oscillator with Minimum Power Consumption at 32 nm
Technology Node , JoVDTT (2017) 51-54.
[7]. Narender Hanchate, LECTOR: A Technique for Leakage
Reduction in CMOS Circuits, IEEE Transactions On
Very Large Scale Integration (Vlsi) Systems, Vol. 12,
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[8]. Balaji Ramakrishna S., Shivananda Yalpi, Nithin Kumar
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Saneei, Fault-tolerant delay cell for ring oscillator

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Volume 3, Issue 10, October – 2018 International Journal of Innovative Science and Research Technology

An Ultra Low Power 5 – Phase Ring Oscillator using

IJISRT18OC374 www.ijisrt.com 684

Balaji et.al (2016) reported a novel method for designing

IJISRT18OC374 www.ijisrt.com 685

Fig 5:- Transient retaliation of lector CMOS

Fig 6:- Transient analysis of lector CNT

response of CMOS and CNT without lector technique

Performance LECTOR LECTOR

IJISRT18OC374 www.ijisrt.com 686

[1]. Ahmet Tekin, Mehmet R. Yuce, and Wentai Liu,

IJISRT18OC374 www.ijisrt.com 687

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