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Bit 201 Computer Organization & Architecture Mid Semester Examination Section A (Answer All Questions in This Section)

1. The document is a mid-semester examination for a BIT 201 Computer Organization & Architecture course. It contains 10 multiple choice questions testing knowledge of topics like register transfer language, micro operations, computer architecture, logic gates, binary addition/subtraction, and representations like two's complement.

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Kewsi Cobbina
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84 views1 page

Bit 201 Computer Organization & Architecture Mid Semester Examination Section A (Answer All Questions in This Section)

1. The document is a mid-semester examination for a BIT 201 Computer Organization & Architecture course. It contains 10 multiple choice questions testing knowledge of topics like register transfer language, micro operations, computer architecture, logic gates, binary addition/subtraction, and representations like two's complement.

Uploaded by

Kewsi Cobbina
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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BIT 201 COMPUTER ORGANIZATION & ARCHITECTURE

Mid Semester Examination


Section A (Answer All questions in this section)
1. RTL stands for:
A. Random transfer language 9. On subtracting 010101 from 11110
B. Register transfer language using 1’s complement, we get
C. Required transfer language A. 01001
D. All of the above B. 11010
C. 10101
2. Micro operation is shown as: D. 10100
A. R1 -> R2 10. On addition of -46 and +28 using 2’s
B. R1<-R2 complement, we get
C. Both A. -10010
D. None of the above B. -00101
C. 01011
3. is concerned with the way D. 0100101
hardware components operate to form
a computer system.
A. Computer organization
B. Computer design
C. Computer Architecture
D. Computer Implementation
4. If both inputs A and B are equal to 1
in an AND gate, the output is
A. Zero
B. One
C. Undetermined
D. Binary
5. The addition of two binary digits is
done by circuit.
A. Half adder
B. Full adder
C. BCD adder
D. Composite adder
6. In 32-bit representation the scale
factor has a range of
A. -128 to 127
B. -256 to 255
C. 0 to 255
D. -127 to 127
7. The ALU uses for
implementing its integer portion.
A. Sign-Magnitude
representation
B. Two’s Complement
representation
C. Binary representation
D. Hexadecimal representation
8. 1’s complement of 1011101 is
A. 0101110
B. 1001101
C. 0100010
D. 1100101

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