Term End Examination - November 2012

Course : ECE301 - VLSI System Design Slot: B1+TB1

Class NBR : 3771/3775/3777/3773

Time : Three Hours Max.Marks:100

Answer ALL the Questions

1. Consider the following figure.

(i) Identify the region of operation and voltage range of VDS and VGS. [2]
(ii) Derive the equation taking the non linearity into consideration. [4]
(iii) Given kp’ = -30× 10-6, W= 0.375µm, L=0.25µm,Vt0 = -0.4V, Vgs = -0.9V, [4]
Vds = -1.2V, = -0.1. Find the drain current.

2. a) Implement 4:1 MUX using 2:1 MUX with transmission gates. [4]
b) The following figure shows a simple logic function realized with Boolean gates. [4]

Implement the function Z using static CMOS as a one stage “Complex Gate”. A
maximum of 12 transistors is allowed.

Page 1 of 6
 c) Find the function, F, implemented by the following circuit [2]

3. a) Define the mode of operation of PMOS & NMOS for all the 5 regions of operations in [3]
inverter.

b) In the transfer characteristics of a inverter, P(Vin = 1.2V, Vout = 2.6V) & Q(Vin = 1.4, [2]
Vout = 0.4V) are the points at which the slope is -1. Calculate the Noise Margins (NML
& NMH).
c) Draw the stick diagram for the logic function F = (A+BC)' [5]
4. a) For the circuit shown, determine the capacitances x, y and z to minimize the delay [10]
along the path of interest. Calculate the normalised delay.

OR
4. b) Calculate the path optimum delay and the gate sizes. CINV is the input capacitance of a [10]
minimum size inverter. Assume r=2.

Page 2 of 6
5. Use RTL Verilog code to implement an 8-bit trailing one detector with the following [10]
interface:
module trailing_one_detector(input [7:0] A, output [2:0] count);

Your trailing one detector should output a count of the number of consecutive bits
in A that are one, starting from the rightmost bit. For example, if A = 8’b01010111
then count = 3’b011, and if A = 8’b00011011 then count = 3’b010. When
A = 8’b11111111, your module should output count = 3’b000.
Also write a Verilog test bench to verify the functionality of the above program.

6. a) Code the following conditional logic with data flow modeling: [4]

b) Write RTL verilog code that take an 8-bit number X and shifts it by 3 bits to the left to [6]
produce an 8-bit number Y, where the three least significant bits of Y are set to zeros.
For example, if X = 8’b1010_1101, then Y = 8’b0110_1000.
module right_shift_by_3(input [7:0] X, output [7:0] Y);

endmodule

7. Derive a state diagram for an FSM that has an input w and an output z. The machine [10]
has to generate z = 1 when the previous four values of w were 1001 or 1111; otherwise,
z =0. Overlapping input patterns are allowed. An example of the desired behavior is
w:010111100110011111
z:000000100100010011

Write the Verilog code for the above state diagram.

Page 3 of 6
8. a) Will the following two program will produce the same hardware? Draw the equivalent [4]
hardware.
//program 1
always @ (posedge clk )
begin
b = a;
c = b;
d =c;
end

//program 2
always @ (posedge clk )
begin
b <= a;
c <= b;
d< =c;
end
b) What things this wrong, or probably wrong, with the following code segments intended [6]
for synthesis?
(a) always @(A or B or C or D or E) (b) always @(SEL or A or B
if (A < B) or C or D)
else if (A > B) begin
OUT <= D; case (SEL)
else if (A == B) 2’b00 : OUT <= A;
OUT <= E; 2’b01 : OUT <= B;
2’b10 : OUT <= C;
2’b11 : OUT <= D;
endcase
end

(c) module add (sum, a, b); (d) always @(SEL or A or

output [15:0] sum; B or C)
input [15:0] a, b; begin
wire temp; if (SEL)
assign {sum, temp} = {a, 1’b1} + {b, 1’b1}; Z = A+B;
endmodule else
Z = A+C;
End
Page 4 of 6
9. a) Design a 3-bit counter that implements the following sequence: 000, 010, 100, 110, [10]
111, 101, 011, 001, and repeat. Design the counter with a reset input that causes the
counter to enter the 000 state. Write a Verilog specification for this counter.

OR
9. b) The figure and truth table below describe a positive-edge triggered J-K flip-flop with [10]
active-low asynchronous preset and clear.

Inputs Outputs

preset clear Clk J K Q Qbar

0 X X X X 1 0

1 0 X X X 0 1

1 1 no edge X X Q Qbar

1 1 <="" td=""> 0 0 Q Qbar

1 1 <="" td=""> 1 0 1 0

1 1 <="" td=""> 0 1 0 1

1 1 <="" td=""> 1 1 toggle

Write a Verilog program (behavioral level) that implements the J-K flip-flop described
above.

Page 5 of 6
10. a) What is skew, what are problems associated with it and how to minimize it? [4]
b) The parameters of the components are as follows: [6]
Inverter: tpd = 200ps, tcd = 100ps
2-input NOR: tpd = 200ps, tcd = 150ps
D-flop: tpd = 200ps tcd = 0ps, Setup time = 300 ps, Hold time = 100 ps.

− What is the highest frequency at which the following circuit can be operated
correctly?
− Determine the minimum clock period time if there is 1ns positive clock skew
between adjacent registers.
− Derive the maximum positive clock skew that can be tolerated before the circuit
fails.

⇔⇔⇔

Page 6 of 6